Index: clang-tools-extra/test/clang-tidy/fix.cpp =================================================================== --- clang-tools-extra/test/clang-tidy/fix.cpp +++ clang-tools-extra/test/clang-tidy/fix.cpp @@ -9,10 +9,10 @@ } // CHECK: } // namespace i // CHECK-MESSAGES: note: FIX-IT applied suggested code changes -// CHECK-YAML: ReplacementText: ' // namespace i' +// CHECK-YAML: ReplacementText: " // namespace i" class A { A(int i); }; // CHECK: class A { explicit A(int i); }; // CHECK-MESSAGES: note: FIX-IT applied suggested code changes // CHECK-MESSAGES: clang-tidy applied 2 of 2 suggested fixes. -// CHECK-YAML: ReplacementText: 'explicit ' +// CHECK-YAML: ReplacementText: "explicit " Index: clang-tools-extra/test/clang-tidy/google-module.cpp =================================================================== --- clang-tools-extra/test/clang-tidy/google-module.cpp +++ clang-tools-extra/test/clang-tidy/google-module.cpp @@ -1,10 +1,10 @@ // RUN: clang-tidy -checks='-*,google*' -config='{}' -dump-config - -- | FileCheck %s // CHECK: CheckOptions: // CHECK: {{- key: *google-readability-braces-around-statements.ShortStatementLines}} -// CHECK-NEXT: {{value: *'1'}} +// CHECK-NEXT: {{value: *"1"}} // CHECK: {{- key: *google-readability-function-size.StatementThreshold}} -// CHECK-NEXT: {{value: *'800'}} +// CHECK-NEXT: {{value: *"800"}} // CHECK: {{- key: *google-readability-namespace-comments.ShortNamespaceLines}} -// CHECK-NEXT: {{value: *'10'}} +// CHECK-NEXT: {{value: *"10"}} // CHECK: {{- key: *google-readability-namespace-comments.SpacesBeforeComments}} -// CHECK-NEXT: {{value: *'2'}} +// CHECK-NEXT: {{value: *"2"}} Index: clang/unittests/Tooling/RefactoringTest.cpp =================================================================== --- clang/unittests/Tooling/RefactoringTest.cpp +++ clang/unittests/Tooling/RefactoringTest.cpp @@ -1120,9 +1120,9 @@ // NOTE: If this test starts to fail for no obvious reason, check whitespace. ASSERT_STREQ("---\n" - "Key: 'input.cpp:20'\n" + "Key: \"input.cpp:20\"\n" "FilePath: input.cpp\n" - "Error: ''\n" + "Error: \"\"\n" "InsertedHeaders: [ a.h ]\n" "RemovedHeaders: [ b.h ]\n" "Replacements: \n" // Extra whitespace here! @@ -1140,9 +1140,9 @@ TEST_F(AtomicChangeTest, YAMLToAtomicChange) { std::string YamlContent = "---\n" - "Key: 'input.cpp:20'\n" + "Key: \"input.cpp:20\"\n" "FilePath: input.cpp\n" - "Error: 'ok'\n" + "Error: \"ok\"\n" "InsertedHeaders: [ a.h ]\n" "RemovedHeaders: [ b.h ]\n" "Replacements: \n" // Extra whitespace here! Index: clang/unittests/Tooling/ReplacementsYamlTest.cpp =================================================================== --- clang/unittests/Tooling/ReplacementsYamlTest.cpp +++ clang/unittests/Tooling/ReplacementsYamlTest.cpp @@ -38,11 +38,11 @@ " - FilePath: /path/to/file1.h\n" " Offset: 232\n" " Length: 56\n" - " ReplacementText: 'replacement #1'\n" + " ReplacementText: \"replacement #1\"\n" " - FilePath: /path/to/file2.h\n" " Offset: 301\n" " Length: 2\n" - " ReplacementText: 'replacement #2'\n" + " ReplacementText: \"replacement #2\"\n" "...\n", YamlContentStream.str().c_str()); } @@ -54,11 +54,11 @@ " - FilePath: /path/to/file1.h\n" " Offset: 232\n" " Length: 56\n" - " ReplacementText: 'replacement #1'\n" + " ReplacementText: \"replacement #1\"\n" " - FilePath: /path/to/file2.h\n" " Offset: 301\n" " Length: 2\n" - " ReplacementText: 'replacement #2'\n" + " ReplacementText: \"replacement #2\"\n" "...\n"; TranslationUnitReplacements DocActual; yaml::Input YAML(YamlContent); Index: lld/test/COFF/pdb-none.test =================================================================== --- lld/test/COFF/pdb-none.test +++ lld/test/COFF/pdb-none.test @@ -7,7 +7,7 @@ # CHECK: PdbStream: # CHECK-NEXT: Age: 0 -# CHECK-NEXT: Guid: '{00000000-0000-0000-0000-000000000000}' +# CHECK-NEXT: Guid: "{00000000-0000-0000-0000-000000000000}" # CHECK-NEXT: Signature: 0 # CHECK-NEXT: Version: VC70 Index: lld/test/COFF/pdb.test =================================================================== --- lld/test/COFF/pdb.test +++ lld/test/COFF/pdb.test @@ -79,22 +79,22 @@ # CHECK-NEXT: - Kind: LF_STRING_ID # CHECK-NEXT: StringId: # CHECK-NEXT: Id: 0 -# CHECK-NEXT: String: 'D:\b' +# CHECK-NEXT: String: "D:\\b" # CHECK-NEXT: - Kind: LF_STRING_ID # CHECK-NEXT: StringId: # CHECK-NEXT: Id: 0 -# CHECK-NEXT: String: 'C:\vs14\VC\BIN\amd64\cl.exe' +# CHECK-NEXT: String: "C:\\vs14\\VC\\BIN\\amd64\\cl.exe" # CHECK-NEXT: - Kind: LF_STRING_ID # CHECK-NEXT: StringId: # CHECK-NEXT: Id: 0 -# CHECK-NEXT: String: '-Z7 -c -MT -IC:\vs14\VC\INCLUDE -IC:\vs14\VC\ATLMFC\INCLUDE -I"C:\Program Files (x86)\Windows Kits\10\include\10.0.10150.0\ucrt" -I"C:\Program Files (x86)\Windows Kits\NETFXSDK\4.6\include\um" -I"C:\Program Files (x86)\Windows Kits\8.1\include\shared"' +# CHECK-NEXT: String: "-Z7 -c -MT -IC:\\vs14\\VC\\INCLUDE -IC:\\vs14\\VC\\ATLMFC\\INCLUDE -I\"C:\\Program Files (x86)\\Windows Kits\\10\\include\\10.0.10150.0\\ucrt\" -I\"C:\\Program Files (x86)\\Windows Kits\\NETFXSDK\\4.6\\include\\um\" -I\"C:\\Program Files (x86)\\Windows Kits\\8.1\\include\\shared\"" # CHECK-NEXT: - Kind: LF_SUBSTR_LIST # CHECK-NEXT: StringList: # CHECK-NEXT: StringIndices: [ 4100 ] # CHECK-NEXT: - Kind: LF_STRING_ID # CHECK-NEXT: StringId: # CHECK-NEXT: Id: 4101 -# CHECK-NEXT: String: ' -I"C:\Program Files (x86)\Windows Kits\8.1\include\um" -I"C:\Program Files (x86)\Windows Kits\8.1\include\winrt" -TC -X' +# CHECK-NEXT: String: " -I\"C:\\Program Files (x86)\\Windows Kits\\8.1\\include\\um\" -I\"C:\\Program Files (x86)\\Windows Kits\\8.1\\include\\winrt\" -TC -X" # CHECK-NEXT: - Kind: LF_STRING_ID # CHECK-NEXT: StringId: # CHECK-NEXT: Id: 0 @@ -102,7 +102,7 @@ # CHECK-NEXT: - Kind: LF_STRING_ID # CHECK-NEXT: StringId: # CHECK-NEXT: Id: 0 -# CHECK-NEXT: String: 'D:\b\vc140.pdb' +# CHECK-NEXT: String: "D:\\b\\vc140.pdb" # CHECK-NEXT: - Kind: LF_BUILDINFO # CHECK-NEXT: BuildInfo: # CHECK-NEXT: ArgIndices: [ 4098, 4099, 4103, 4104, 4102 ] Index: lld/test/ELF/lto/opt-remarks.ll =================================================================== --- lld/test/ELF/lto/opt-remarks.ll +++ lld/test/ELF/lto/opt-remarks.ll @@ -20,13 +20,13 @@ ; YAML-NEXT: Function: main ; YAML-NEXT: Args: ; YAML-NEXT: - Callee: tinkywinky -; YAML-NEXT: - String: ' can be inlined into ' +; YAML-NEXT: - String: " can be inlined into " ; YAML-NEXT: - Caller: main -; YAML-NEXT: - String: ' with cost=' -; YAML-NEXT: - Cost: '0' -; YAML-NEXT: - String: ' (threshold=' -; YAML-NEXT: - Threshold: '337' -; YAML-NEXT: - String: ')' +; YAML-NEXT: - String: " with cost=" +; YAML-NEXT: - Cost: "0" +; YAML-NEXT: - String: " (threshold=" +; YAML-NEXT: - Threshold: "337" +; YAML-NEXT: - String: ")" ; YAML-NEXT: ... ; YAML-NEXT: --- !Passed ; YAML-NEXT: Pass: inline @@ -34,7 +34,7 @@ ; YAML-NEXT: Function: main ; YAML-NEXT: Args: ; YAML-NEXT: - Callee: tinkywinky -; YAML-NEXT: - String: ' inlined into ' +; YAML-NEXT: - String: " inlined into " ; YAML-NEXT: - Caller: main ; YAML-NEXT: ... @@ -46,7 +46,7 @@ ; YAML-HOT-NEXT: Hotness: 300 ; YAML-HOT-NEXT: Args: ; YAML-HOT-NEXT: - Callee: tinkywinky -; YAML-HOT-NEXT: - String: ' inlined into ' +; YAML-HOT-NEXT: - String: " inlined into " ; YAML-HOT-NEXT: - Caller: main ; YAML-HOT-NEXT: ... Index: lld/test/mach-o/bind-opcodes.yaml =================================================================== --- lld/test/mach-o/bind-opcodes.yaml +++ lld/test/mach-o/bind-opcodes.yaml @@ -90,21 +90,21 @@ # CHECK: BindOpcodes: # CHECK: - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM # CHECK: Imm: 1 -# CHECK: Symbol: '' +# CHECK: Symbol: "" # CHECK: - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM # CHECK: Imm: 0 # CHECK: Symbol: dyld_stub_binder # CHECK: - Opcode: BIND_OPCODE_SET_TYPE_IMM # CHECK: Imm: 1 -# CHECK: Symbol: '' +# CHECK: Symbol: "" # CHECK: - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB # CHECK: Imm: 2 # CHECK: ULEBExtraData: # CHECK: - 0x0000000000000000 -# CHECK: Symbol: '' +# CHECK: Symbol: "" # CHECK: - Opcode: BIND_OPCODE_DO_BIND # CHECK: Imm: 0 -# CHECK: Symbol: '' +# CHECK: Symbol: "" # CHECK: - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM # CHECK: Imm: 0 # CHECK: Symbol: ___stdoutp @@ -112,32 +112,32 @@ # CHECK: Imm: 2 # CHECK: ULEBExtraData: # CHECK: - 0x0000000000000010 -# CHECK: Symbol: '' +# CHECK: Symbol: "" # CHECK: - Opcode: BIND_OPCODE_DO_BIND # CHECK: Imm: 0 -# CHECK: Symbol: '' +# CHECK: Symbol: "" # CHECK: - Opcode: BIND_OPCODE_DONE # CHECK: Imm: 0 -# CHECK: Symbol: '' +# CHECK: Symbol: "" # CHECK: LazyBindOpcodes: # CHECK: - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB # CHECK: Imm: 2 # CHECK: ULEBExtraData: # CHECK: - 0x0000000000000018 -# CHECK: Symbol: '' +# CHECK: Symbol: "" # CHECK: - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM # CHECK: Imm: 1 -# CHECK: Symbol: '' +# CHECK: Symbol: "" # CHECK: - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM # CHECK: Imm: 0 # CHECK: Symbol: _fprintf # CHECK: - Opcode: BIND_OPCODE_DO_BIND # CHECK: Imm: 0 -# CHECK: Symbol: '' +# CHECK: Symbol: "" # CHECK: - Opcode: BIND_OPCODE_DONE # CHECK: Imm: 0 -# CHECK: Symbol: '' +# CHECK: Symbol: "" # CHECK: - Opcode: BIND_OPCODE_DONE # CHECK: Imm: 0 -# CHECK: Symbol: '' \ No newline at end of file +# CHECK: Symbol: "" \ No newline at end of file Index: lld/test/mach-o/eh-frame-relocs-arm64.yaml =================================================================== --- lld/test/mach-o/eh-frame-relocs-arm64.yaml +++ lld/test/mach-o/eh-frame-relocs-arm64.yaml @@ -210,7 +210,7 @@ ... # CHECK: --- !native -# CHECK: path: '' +# CHECK: path: "" # CHECK: defined-atoms: # CHECK: - ref-name: L000 # CHECK: type: unwind-cfi @@ -296,7 +296,7 @@ # CHECK: alignment: 4 # CHECK: ... -# # Make sure we don't have any relocations in the __eh_frame section +# # Make sure we don"t have any relocations in the __eh_frame section # CODE-NOT: RELOCATION RECORDS FOR [__eh_frame] # Also make sure the reloc for the CIE->personality function is the Index: lld/test/mach-o/objc-category-list-atom.yaml =================================================================== --- lld/test/mach-o/objc-category-list-atom.yaml +++ lld/test/mach-o/objc-category-list-atom.yaml @@ -46,7 +46,7 @@ # Make sure we atomize the category list section by pointer sized atoms. -# CHECK: path: '' +# CHECK: path: "" # CHECK: defined-atoms: # CHECK: - type: objc-category-list # CHECK: content: [ 00, 00, 00, 00, 00, 00, 00, 00 ] Index: lld/test/mach-o/objc-image-info-pass-output.yaml =================================================================== --- lld/test/mach-o/objc-image-info-pass-output.yaml +++ lld/test/mach-o/objc-image-info-pass-output.yaml @@ -21,10 +21,10 @@ ... # CHECK: --- !native -# CHECK: path: '' +# CHECK: path: "" # CHECK: defined-atoms: # CHECK: - scope: hidden # CHECK: type: objc-image-info # CHECK: content: [ 00, 00, 00, 00, 20, 02, 00, 00 ] # CHECK: alignment: 4 # CHECK: ... \ No newline at end of file Index: lld/test/mach-o/parse-tlv-relocs-x86-64.yaml =================================================================== --- lld/test/mach-o/parse-tlv-relocs-x86-64.yaml +++ lld/test/mach-o/parse-tlv-relocs-x86-64.yaml @@ -57,7 +57,7 @@ extern: true symbol: 3 local-symbols: - - name: '_x$tlv$init' + - name: "_x$tlv$init" type: N_SECT sect: 2 value: 0x0000000000000014 @@ -90,7 +90,7 @@ # CHECK-NEXT: target: __tlv_bootstrap # CHECK-NEXT: - kind: tlvInitSectionOffset # CHECK-NEXT: offset: 16 -# CHECK-NEXT: target: '_x$tlv$init' +# CHECK-NEXT: target: "_x$tlv$init" # CHECK: - name: _main # CHECK-NOT: - name: # CHECK-NEXT: scope: global Index: lld/test/mach-o/run-tlv-pass-x86-64.yaml =================================================================== --- lld/test/mach-o/run-tlv-pass-x86-64.yaml +++ lld/test/mach-o/run-tlv-pass-x86-64.yaml @@ -68,7 +68,7 @@ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ] local-symbols: - - name: '_x$tlv$init' + - name: "_x$tlv$init" type: N_SECT sect: 2 value: 0x0000000000000014 @@ -83,17 +83,17 @@ scope: [ N_EXT ] sect: 3 value: 0x0000000000000018 - - name: '__tlv_bootstrap' + - name: "__tlv_bootstrap" type: N_SECT scope: [ N_EXT ] sect: 4 value: 0x00000000000000C0 - - name: 'dyld_stub_binder' + - name: "dyld_stub_binder" type: N_SECT scope: [ N_EXT ] sect: 4 value: 0x00000000000000C8 - - name: 'start' + - name: "start" type: N_SECT scope: [ N_EXT ] sect: 4 @@ -111,8 +111,8 @@ # CHECK-NEXT: target: __tlv_bootstrap # CHECK-NEXT: - kind: tlvInitSectionOffset # CHECK-NEXT: offset: 16 -# CHECK-NEXT: target: '_x$tlv$init' -# CHECK: - name: '_x$tlv$init' +# CHECK-NEXT: target: "_x$tlv$init" +# CHECK: - name: "_x$tlv$init" # CHECK-NEXT: type: tlv-zero-fill # CHECK: - name: _main # CHECK-NOT: - name: Index: lld/test/mach-o/sectcreate.yaml =================================================================== --- lld/test/mach-o/sectcreate.yaml +++ lld/test/mach-o/sectcreate.yaml @@ -2,7 +2,7 @@ # RUN: %p/Inputs/hw.raw_bytes -print_atoms | FileCheck %s # CHECK: --- !native -# CHECK: path: '' +# CHECK: path: "" # CHECK: defined-atoms: # CHECK: - scope: global # CHECK: type: sectcreate Index: lld/test/mach-o/string-table.yaml =================================================================== --- lld/test/mach-o/string-table.yaml +++ lld/test/mach-o/string-table.yaml @@ -1,7 +1,7 @@ # RUN: lld -flavor darwin -arch i386 %s %p/Inputs/hello-world-x86.yaml -o %t # RUN: obj2yaml %t | FileCheck %s # -# Test that the string table contains a ' ' as its first symbol +# Test that the string table contains a " " as its first symbol # --- !mach-o @@ -58,9 +58,9 @@ ... # CHECK: StringTable: -# CHECK-NEXT: - ' ' +# CHECK-NEXT: - " " # CHECK-NEXT: - __mh_execute_header # CHECK-NEXT: - _main # CHECK-NEXT: - _printf # CHECK-NEXT: - dyld_stub_binder -# CHECK-NEXT: - '' +# CHECK-NEXT: - "" Index: llvm/lib/Support/YAMLTraits.cpp =================================================================== --- llvm/lib/Support/YAMLTraits.cpp +++ llvm/lib/Support/YAMLTraits.cpp @@ -9,6 +9,7 @@ #include "llvm/Support/YAMLTraits.h" #include "llvm/ADT/SmallString.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/ADT/Twine.h" #include "llvm/Support/Casting.h" #include "llvm/Support/Errc.h" @@ -605,9 +606,9 @@ void Output::scalarString(StringRef &S, bool MustQuote) { this->newLineCheck(); if (S.empty()) { - // Print '' for the empty string because leaving the field empty is not + // Print "" for the empty string because leaving the field empty is not // allowed. - this->outputUpToEndOfLine("''"); + this->outputUpToEndOfLine("\"\""); return; } if (!MustQuote) { @@ -615,22 +616,22 @@ this->outputUpToEndOfLine(S); return; } - unsigned i = 0; - unsigned j = 0; unsigned End = S.size(); - output("'"); // Starting single quote. + SmallString<24> Encoded("\""); const char *Base = S.data(); - while (j < End) { - // Escape a single quote by doubling it. - if (S[j] == '\'') { - output(StringRef(&Base[i], j - i + 1)); - output("'"); - i = j + 1; + for (unsigned i = 0; i < End; i++) { + char C = Base[i]; + if (isprint(C)) { + if (C == '\"' || C == '\\') { + Encoded += '\\'; + } + Encoded += C; + } else { + Encoded += "\\x" + toHex(StringRef(&C, 1)); } - ++j; } - output(StringRef(&Base[i], j - i)); - this->outputUpToEndOfLine("'"); // Ending single quote. + Encoded += '\"'; + this->outputUpToEndOfLine(Encoded); } void Output::blockScalarString(StringRef &S) { Index: llvm/test/CodeGen/MIR/Generic/frame-info.mir =================================================================== --- llvm/test/CodeGen/MIR/Generic/frame-info.mir +++ llvm/test/CodeGen/MIR/Generic/frame-info.mir @@ -36,13 +36,13 @@ # CHECK-NEXT: maxAlignment: # CHECK-NEXT: adjustsStack: false # CHECK-NEXT: hasCalls: false -# CHECK-NEXT: stackProtector: '' +# CHECK-NEXT: stackProtector: "" # CHECK-NEXT: maxCallFrameSize: # CHECK-NEXT: hasOpaqueSPAdjustment: false # CHECK-NEXT: hasVAStart: false # CHECK-NEXT: hasMustTailInVarArgFunc: false -# CHECK-NEXT: savePoint: '' -# CHECK-NEXT: restorePoint: '' +# CHECK-NEXT: savePoint: "" +# CHECK-NEXT: restorePoint: "" # CHECK: body frameInfo: maxAlignment: 4 @@ -65,7 +65,7 @@ # CHECK-NEXT: maxAlignment: # CHECK-NEXT: adjustsStack: true # CHECK-NEXT: hasCalls: true -# CHECK-NEXT: stackProtector: '' +# CHECK-NEXT: stackProtector: "" # CHECK-NEXT: maxCallFrameSize: 4 # CHECK-NEXT: hasOpaqueSPAdjustment: true # CHECK-NEXT: hasVAStart: true Index: llvm/test/CodeGen/MIR/X86/callee-saved-info.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/callee-saved-info.mir +++ llvm/test/CodeGen/MIR/X86/callee-saved-info.mir @@ -50,15 +50,15 @@ adjustsStack: true hasCalls: true # CHECK: fixedStack: -# CHECK: , callee-saved-register: '%rbx' } +# CHECK: , callee-saved-register: "%rbx" } fixedStack: - - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' } + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: "%rbx" } # CHECK: stack: # CHECK-NEXT: - { id: 0 -# CHECK: callee-saved-register: '%edi' +# CHECK: callee-saved-register: "%edi" stack: - { id: 0, name: b, offset: -20, size: 4, alignment: 4 } - - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi' } + - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: "%edi" } body: | bb.0.entry: successors: %bb.1.check Index: llvm/test/CodeGen/MIR/X86/constant-pool.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/constant-pool.mir +++ llvm/test/CodeGen/MIR/X86/constant-pool.mir @@ -44,18 +44,18 @@ # CHECK: name: test # CHECK: constants: # CHECK-NEXT: - id: 0 -# CHECK-NEXT: value: 'double 3.250000e+00' +# CHECK-NEXT: value: "double 3.250000e+00" # CHECK-NEXT: alignment: 8 # CHECK-NEXT: - id: 1 -# CHECK-NEXT: value: 'float 6.250000e+00' +# CHECK-NEXT: value: "float 6.250000e+00" # CHECK-NEXT: alignment: 4 name: test constants: - id: 0 - value: 'double 3.250000e+00' + value: "double 3.250000e+00" alignment: 8 - id: 1 - value: 'float 6.250000e+00' + value: "float 6.250000e+00" alignment: 4 body: | bb.0.entry: @@ -72,17 +72,17 @@ # CHECK: name: test2 # CHECK: constants: # CHECK-NEXT: - id: 0 -# CHECK-NEXT: value: 'double 3.250000e+00' +# CHECK-NEXT: value: "double 3.250000e+00" # CHECK-NEXT: alignment: 8 # CHECK-NEXT: - id: 1 -# CHECK-NEXT: value: 'float 6.250000e+00' +# CHECK-NEXT: value: "float 6.250000e+00" # CHECK-NEXT: alignment: 4 name: test2 constants: - id: 0 - value: 'double 3.250000e+00' + value: "double 3.250000e+00" - id: 1 - value: 'float 6.250000e+00' + value: "float 6.250000e+00" body: | bb.0.entry: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ @@ -96,18 +96,18 @@ # CHECK: name: test3 # CHECK: constants: # CHECK-NEXT: - id: 0 -# CHECK-NEXT: value: 'double 3.250000e+00' +# CHECK-NEXT: value: "double 3.250000e+00" # CHECK-NEXT: alignment: 128 # CHECK-NEXT: - id: 1 -# CHECK-NEXT: value: 'float 6.250000e+00' +# CHECK-NEXT: value: "float 6.250000e+00" # CHECK-NEXT: alignment: 1 name: test3 constants: - id: 0 - value: 'double 3.250000e+00' + value: "double 3.250000e+00" alignment: 128 - id: 1 - value: 'float 6.250000e+00' + value: "float 6.250000e+00" alignment: 1 body: | bb.0.entry: @@ -124,9 +124,9 @@ name: test4 constants: - id: 0 - value: 'double 3.250000e+00' + value: "double 3.250000e+00" - id: 1 - value: 'float 6.250000e+00' + value: "float 6.250000e+00" body: | bb.0.entry: ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _ Index: llvm/test/CodeGen/MIR/X86/dynamic-regmask.ll =================================================================== --- llvm/test/CodeGen/MIR/X86/dynamic-regmask.ll +++ llvm/test/CodeGen/MIR/X86/dynamic-regmask.ll @@ -1,30 +1,30 @@ -; RUN: llc -mtriple=x86_64-pc-win32 -stop-after machine-sink %s -o %t.mir -; RUN: FileCheck %s < %t.mir -; RUN: llc %t.mir -mtriple=x86_64-pc-win32 -run-pass machine-sink -; Check that callee saved registers are printed in a format that can then be parsed. - -declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) - -define i32 @caller(i32 %a0) nounwind { - %b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0) - %b2 = add i32 %b1, %a0 - ret i32 %b2 -} -; CHECK: name: caller -; CHECK: CALL64pcrel32 @callee, CustomRegMask(%bh,%bl,%bp,%bpl,%bx,%ebp,%ebx,%esp,%rbp,%rbx,%rsp,%sp,%spl,%r10,%r11,%r12,%r13,%r14,%r15,%xmm8,%xmm9,%xmm10,%xmm11,%xmm12,%xmm13,%xmm14,%xmm15,%r10b,%r11b,%r12b,%r13b,%r14b,%r15b,%r10d,%r11d,%r12d,%r13d,%r14d,%r15d,%r10w,%r11w,%r12w,%r13w,%r14w,%r15w) -; CHECK: RET 0, %eax - -define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind { - %b1 = mul i32 7, %e0 - %b2 = udiv i32 5, %e0 - %b3 = mul i32 7, %d0 - %b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0 - %b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1 - %b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2 - ret {i32, i32, i32} %b6 -} -; CHECK: name: test_callee -; CHECK: calleeSavedRegisters: [ '%rbx', '%rbp', '%rsp', '%r10', '%r11', '%r12', -; CHECK: '%r13', '%r14', '%r15', '%xmm8', '%xmm9', '%xmm10', -; CHECK: '%xmm11', '%xmm12', '%xmm13', '%xmm14', '%xmm15' ] -; CHECK: RET 0, %eax, %ecx, %edx +; RUN: llc -mtriple=x86_64-pc-win32 -stop-after machine-sink %s -o %t.mir +; RUN: FileCheck %s < %t.mir +; RUN: llc %t.mir -mtriple=x86_64-pc-win32 -run-pass machine-sink +; Check that callee saved registers are printed in a format that can then be parsed. + +declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) + +define i32 @caller(i32 %a0) nounwind { + %b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0) + %b2 = add i32 %b1, %a0 + ret i32 %b2 +} +; CHECK: name: caller +; CHECK: CALL64pcrel32 @callee, CustomRegMask(%bh,%bl,%bp,%bpl,%bx,%ebp,%ebx,%esp,%rbp,%rbx,%rsp,%sp,%spl,%r10,%r11,%r12,%r13,%r14,%r15,%xmm8,%xmm9,%xmm10,%xmm11,%xmm12,%xmm13,%xmm14,%xmm15,%r10b,%r11b,%r12b,%r13b,%r14b,%r15b,%r10d,%r11d,%r12d,%r13d,%r14d,%r15d,%r10w,%r11w,%r12w,%r13w,%r14w,%r15w) +; CHECK: RET 0, %eax + +define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind { + %b1 = mul i32 7, %e0 + %b2 = udiv i32 5, %e0 + %b3 = mul i32 7, %d0 + %b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0 + %b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1 + %b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2 + ret {i32, i32, i32} %b6 +} +; CHECK: name: test_callee +; CHECK: calleeSavedRegisters: [ "%rbx", "%rbp", "%rsp", "%r10", "%r11", "%r12", +; CHECK: "%r13", "%r14", "%r15", "%xmm8", "%xmm9", "%xmm10", +; CHECK: "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15" ] +; CHECK: RET 0, %eax, %ecx, %edx Index: llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir +++ llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir @@ -14,10 +14,10 @@ tracksRegLiveness: true registers: - { id: 0, class: gr32 } - # CHECK: - { id: 1, class: gr32, preferred-register: '%0' } - # CHECK: - { id: 2, class: gr32, preferred-register: '%edi' } - - { id: 1, class: gr32, preferred-register: '%0' } - - { id: 2, class: gr32, preferred-register: '%edi' } + # CHECK: - { id: 1, class: gr32, preferred-register: "%0" } + # CHECK: - { id: 2, class: gr32, preferred-register: "%edi" } + - { id: 1, class: gr32, preferred-register: "%0" } + - { id: 2, class: gr32, preferred-register: "%edi" } body: | bb.0.body: liveins: %edi, %esi Index: llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir +++ llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir @@ -27,17 +27,17 @@ name: foo tracksRegLiveness: true liveins: - - { reg: '%edi' } - - { reg: '%esi' } + - { reg: "%edi" } + - { reg: "%esi" } # CHECK: frameInfo: -# CHECK: savePoint: '%bb.2.true' -# CHECK-NEXT: restorePoint: '%bb.2.true' +# CHECK: savePoint: "%bb.2.true" +# CHECK-NEXT: restorePoint: "%bb.2.true" # CHECK: stack frameInfo: maxAlignment: 4 hasCalls: true - savePoint: '%bb.2.true' - restorePoint: '%bb.2.true' + savePoint: "%bb.2.true" + restorePoint: "%bb.2.true" stack: - { id: 0, name: tmp, offset: 0, size: 4, alignment: 4 } body: | Index: llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir +++ llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir @@ -41,11 +41,11 @@ hasCalls: true # CHECK-LABEL: name: test # CHECK: frameInfo -# CHECK: stackProtector: '%stack.0.StackGuardSlot' - stackProtector: '%stack.0.StackGuardSlot' +# CHECK: stackProtector: "%stack.0.StackGuardSlot" + stackProtector: "%stack.0.StackGuardSlot" fixedStack: - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, - callee-saved-register: '%rbx' } + callee-saved-register: "%rbx" } stack: - { id: 0, name: StackGuardSlot, offset: -24, size: 8, alignment: 8 } - { id: 1, name: test, offset: -40, size: 8, alignment: 8 } Index: llvm/test/CodeGen/MIR/X86/function-liveins.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/function-liveins.mir +++ llvm/test/CodeGen/MIR/X86/function-liveins.mir @@ -1,5 +1,5 @@ # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s -# This test ensures that the MIR parser parses machine function's liveins +# This test ensures that the MIR parser parses machine function"s liveins # correctly. --- | @@ -19,11 +19,11 @@ - { id: 1, class: gr32 } - { id: 2, class: gr32 } # CHECK: liveins: -# CHECK-NEXT: - { reg: '%edi', virtual-reg: '%0' } -# CHECK-NEXT: - { reg: '%esi', virtual-reg: '%1' } +# CHECK-NEXT: - { reg: "%edi", virtual-reg: "%0" } +# CHECK-NEXT: - { reg: "%esi", virtual-reg: "%1" } liveins: - - { reg: '%edi', virtual-reg: '%0' } - - { reg: '%esi', virtual-reg: '%1' } + - { reg: "%edi", virtual-reg: "%0" } + - { reg: "%esi", virtual-reg: "%1" } body: | bb.0.body: liveins: %edi, %esi Index: llvm/test/CodeGen/MIR/X86/generic-instr-type.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/generic-instr-type.mir +++ llvm/test/CodeGen/MIR/X86/generic-instr-type.mir @@ -19,11 +19,11 @@ --- name: test_vregs # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: _, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: _, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: _, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: _, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } Index: llvm/test/CodeGen/MIR/X86/jump-table-info.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/jump-table-info.mir +++ llvm/test/CodeGen/MIR/X86/jump-table-info.mir @@ -61,13 +61,13 @@ # CHECK-NEXT: kind: label-difference32 # CHECK-NEXT: entries: # CHECK-NEXT: - id: 0 -# CHECK-NEXT: blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] +# CHECK-NEXT: blocks: [ "%bb.3.lbl1", "%bb.4.lbl2", "%bb.5.lbl3", "%bb.6.lbl4" ] # CHECK-NEXT: body: jumpTable: kind: label-difference32 entries: - id: 0 - blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] + blocks: [ "%bb.3.lbl1", "%bb.4.lbl2", "%bb.5.lbl3", "%bb.6.lbl4" ] body: | bb.0.entry: successors: %bb.2.def, %bb.1.entry @@ -110,7 +110,7 @@ kind: label-difference32 entries: - id: 1 - blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] + blocks: [ "%bb.3.lbl1", "%bb.4.lbl2", "%bb.5.lbl3", "%bb.6.lbl4" ] body: | bb.0.entry: successors: %bb.2.def, %bb.1.entry Index: llvm/test/CodeGen/MIR/X86/register-operand-class.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/register-operand-class.mir +++ llvm/test/CodeGen/MIR/X86/register-operand-class.mir @@ -6,11 +6,11 @@ --- # CHECK-LABEL: name: func # CHECK: registers: -# CHECK: - { id: 0, class: gr32, preferred-register: '' } -# CHECK: - { id: 1, class: gr64, preferred-register: '' } -# CHECK: - { id: 2, class: gr32, preferred-register: '' } -# CHECK: - { id: 3, class: gr16, preferred-register: '' } -# CHECK: - { id: 4, class: _, preferred-register: '' } +# CHECK: - { id: 0, class: gr32, preferred-register: "" } +# CHECK: - { id: 1, class: gr64, preferred-register: "" } +# CHECK: - { id: 2, class: gr32, preferred-register: "" } +# CHECK: - { id: 3, class: gr16, preferred-register: "" } +# CHECK: - { id: 4, class: _, preferred-register: "" } name: func body: | bb.0: Index: llvm/test/CodeGen/MIR/X86/roundtrip.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/roundtrip.mir +++ llvm/test/CodeGen/MIR/X86/roundtrip.mir @@ -2,8 +2,8 @@ --- # CHECK-LABEL: name: func0 # CHECK: registers: -# CHECK: - { id: 0, class: gr32, preferred-register: '' } -# CHECK: - { id: 1, class: gr32, preferred-register: '' } +# CHECK: - { id: 0, class: gr32, preferred-register: "" } +# CHECK: - { id: 1, class: gr32, preferred-register: "" } # CHECK: body: | # CHECK: bb.0: # CHECK: %0 = MOV32r0 implicit-def %eflags Index: llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir +++ llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir @@ -15,13 +15,13 @@ name: test tracksRegLiveness: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '%esi' } -# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '%edi' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "%esi" } +# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: "%edi" } registers: - { id: 0, class: gr32 } - - { id: 1, class: gr32, preferred-register: '%esi' } - - { id: 2, class: gr32, preferred-register: '%edi' } + - { id: 1, class: gr32, preferred-register: "%esi" } + - { id: 2, class: gr32, preferred-register: "%edi" } body: | bb.0.body: liveins: %edi, %esi Index: llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir +++ llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir @@ -19,7 +19,7 @@ frameInfo: maxAlignment: 4 # CHECK: fixedStack: -# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, callee-saved-register: '' } +# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, callee-saved-register: "" } fixedStack: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 } stack: Index: llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir +++ llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir @@ -1,5 +1,5 @@ # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s -# This test ensures that the MIR parser parses the stack object's debug info +# This test ensures that the MIR parser parses the stack object"s debug info # correctly. --- | declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 @@ -52,11 +52,11 @@ # CHECK-LABEL: foo # CHECK: stack: # CHECK: - { id: 0, name: y.i, type: default, offset: 0, size: 256, alignment: 16, -# CHECK-NEXT: callee-saved-register: '', di-variable: '!4', di-expression: '!10', -# CHECK-NEXT: di-location: '!11' } +# CHECK-NEXT: callee-saved-register: "", di-variable: "!4", di-expression: "!10", +# CHECK-NEXT: di-location: "!11" } stack: - - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4', - di-expression: '!7', di-location: '!8' } + - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: "!4", + di-expression: "!7", di-location: "!8" } body: | bb.0.entry: successors: %bb.1.for.body Index: llvm/test/CodeGen/MIR/X86/stack-objects.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/stack-objects.mir +++ llvm/test/CodeGen/MIR/X86/stack-objects.mir @@ -22,11 +22,11 @@ maxAlignment: 8 # CHECK: stack: # CHECK-NEXT: - { id: 0, name: b, type: default, offset: -12, size: 4, alignment: 4, -# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } +# CHECK-NEXT: callee-saved-register: "", di-variable: "", di-expression: "", di-location: "" } # CHECK-NEXT: - { id: 1, name: x, type: default, offset: -24, size: 8, alignment: 8, -# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } -# CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, -# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } +# CHECK-NEXT: callee-saved-register: "", di-variable: "", di-expression: "", di-location: "" } +# CHECK-NEXT: - { id: 2, name: "", type: spill-slot, offset: -32, size: 4, alignment: 4, +# CHECK-NEXT: callee-saved-register: "", di-variable: "", di-expression: "", di-location: "" } stack: - { id: 0, name: b, offset: -12, size: 4, alignment: 4 } - { id: 1, name: x, offset: -24, size: 8, alignment: 8 } Index: llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir +++ llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir @@ -24,10 +24,10 @@ maxAlignment: 8 adjustsStack: true # CHECK: stack: -# CHECK-NEXT: - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4, -# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } -# CHECK-NEXT: - { id: 1, name: '', type: default, offset: -32, size: 8, alignment: 8, -# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } +# CHECK-NEXT: - { id: 0, name: "", type: default, offset: -20, size: 4, alignment: 4, +# CHECK-NEXT: callee-saved-register: "", di-variable: "", di-expression: "", di-location: "" } +# CHECK-NEXT: - { id: 1, name: "", type: default, offset: -32, size: 8, alignment: 8, +# CHECK-NEXT: callee-saved-register: "", di-variable: "", di-expression: "", di-location: "" } # CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1, stack: - { id: 0, offset: -20, size: 4, alignment: 4 } Index: llvm/test/CodeGen/MIR/X86/virtual-registers.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/virtual-registers.mir +++ llvm/test/CodeGen/MIR/X86/virtual-registers.mir @@ -33,9 +33,9 @@ name: bar tracksRegLiveness: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: "" } registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } @@ -67,9 +67,9 @@ tracksRegLiveness: true # CHECK: name: foo # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: "" } registers: - { id: 2, class: gr32 } - { id: 0, class: gr32 } Index: llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir +++ llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir @@ -24,9 +24,9 @@ legalized: false regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: _, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: _, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -56,9 +56,9 @@ legalized: false regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: _, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: _, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -88,9 +88,9 @@ legalized: false regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: _, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: _, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } Index: llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir +++ llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir @@ -26,9 +26,9 @@ legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -56,9 +56,9 @@ legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -86,9 +86,9 @@ legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } Index: llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir +++ llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir @@ -26,9 +26,9 @@ legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -56,9 +56,9 @@ legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -86,9 +86,9 @@ legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } Index: llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir +++ llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir @@ -28,9 +28,9 @@ legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -58,9 +58,9 @@ legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -88,9 +88,9 @@ legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: _, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: _, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } Index: llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir +++ llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir @@ -33,8 +33,8 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_mul_vec256 # CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } +# CHECK: - { id: 0, class: vecr, preferred-register: "" } +# CHECK: - { id: 1, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -56,8 +56,8 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_add_vec256 # CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } +# CHECK: - { id: 0, class: vecr, preferred-register: "" } +# CHECK: - { id: 1, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -79,8 +79,8 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_sub_vec256 # CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } +# CHECK: - { id: 0, class: vecr, preferred-register: "" } +# CHECK: - { id: 1, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -100,8 +100,8 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -122,8 +122,8 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } Index: llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir +++ llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir @@ -33,8 +33,8 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -53,8 +53,8 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -73,8 +73,8 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -93,8 +93,8 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -115,8 +115,8 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } Index: llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir +++ llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir @@ -14,11 +14,11 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } Index: llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir +++ llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir @@ -145,9 +145,9 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_add_i8 # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } -# CHECK: - { id: 2, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } +# CHECK: - { id: 2, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -172,9 +172,9 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_add_i16 # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } -# CHECK: - { id: 2, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } +# CHECK: - { id: 2, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -199,9 +199,9 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_add_i32 # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } -# CHECK: - { id: 2, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } +# CHECK: - { id: 2, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -226,9 +226,9 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_add_i64 # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } -# CHECK: - { id: 2, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } +# CHECK: - { id: 2, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -253,14 +253,14 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_mul_gpr # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } -# CHECK: - { id: 2, class: gpr, preferred-register: '' } -# CHECK: - { id: 3, class: gpr, preferred-register: '' } -# CHECK: - { id: 4, class: gpr, preferred-register: '' } -# CHECK: - { id: 5, class: gpr, preferred-register: '' } -# CHECK: - { id: 6, class: gpr, preferred-register: '' } -# CHECK: - { id: 7, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } +# CHECK: - { id: 2, class: gpr, preferred-register: "" } +# CHECK: - { id: 3, class: gpr, preferred-register: "" } +# CHECK: - { id: 4, class: gpr, preferred-register: "" } +# CHECK: - { id: 5, class: gpr, preferred-register: "" } +# CHECK: - { id: 6, class: gpr, preferred-register: "" } +# CHECK: - { id: 7, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -292,9 +292,9 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_add_float # CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } -# CHECK: - { id: 2, class: vecr, preferred-register: '' } +# CHECK: - { id: 0, class: vecr, preferred-register: "" } +# CHECK: - { id: 1, class: vecr, preferred-register: "" } +# CHECK: - { id: 2, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -319,9 +319,9 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_add_double # CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } -# CHECK: - { id: 2, class: vecr, preferred-register: '' } +# CHECK: - { id: 0, class: vecr, preferred-register: "" } +# CHECK: - { id: 1, class: vecr, preferred-register: "" } +# CHECK: - { id: 2, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -346,9 +346,9 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_add_v4i32 # CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } -# CHECK: - { id: 2, class: vecr, preferred-register: '' } +# CHECK: - { id: 0, class: vecr, preferred-register: "" } +# CHECK: - { id: 1, class: vecr, preferred-register: "" } +# CHECK: - { id: 2, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -373,9 +373,9 @@ tracksRegLiveness: true # CHECK-LABEL: name: test_add_v4f32 # CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } -# CHECK: - { id: 2, class: vecr, preferred-register: '' } +# CHECK: - { id: 0, class: vecr, preferred-register: "" } +# CHECK: - { id: 1, class: vecr, preferred-register: "" } +# CHECK: - { id: 2, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -399,8 +399,8 @@ selected: false # CHECK-LABEL: name: test_load_i8 # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -422,8 +422,8 @@ selected: false # CHECK-LABEL: name: test_load_i16 # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -445,8 +445,8 @@ selected: false # CHECK-LABEL: name: test_load_i32 # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -469,8 +469,8 @@ selected: false # CHECK-LABEL: name: test_load_i64 # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -492,8 +492,8 @@ selected: false # CHECK-LABEL: name: test_load_float # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -515,8 +515,8 @@ selected: false # CHECK-LABEL: name: test_load_double # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -538,8 +538,8 @@ selected: false # CHECK-LABEL: name: test_load_v4i32 # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: vecr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -561,8 +561,8 @@ selected: false # CHECK-LABEL: name: test_store_i32 # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -585,8 +585,8 @@ selected: false # CHECK-LABEL: name: test_store_i64 # CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 0, class: gpr, preferred-register: "" } +# CHECK: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -610,12 +610,12 @@ # CHECK-LABEL: name: test_store_float # CHECK: registers: -# FAST-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# FAST-NEXT: - { id: 2, class: gpr, preferred-register: '' } +# FAST-NEXT: - { id: 0, class: vecr, preferred-register: "" } +# FAST-NEXT: - { id: 1, class: gpr, preferred-register: "" } +# FAST-NEXT: - { id: 2, class: gpr, preferred-register: "" } -# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: "" } +# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } @@ -647,12 +647,12 @@ # CHECK-LABEL: name: test_store_double # CHECK: registers: -# FAST-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# FAST-NEXT: - { id: 2, class: gpr, preferred-register: '' } +# FAST-NEXT: - { id: 0, class: vecr, preferred-register: "" } +# FAST-NEXT: - { id: 1, class: gpr, preferred-register: "" } +# FAST-NEXT: - { id: 2, class: gpr, preferred-register: "" } -# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: "" } +# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } @@ -682,10 +682,10 @@ legalized: true # CHECK-LABEL: name: constInt_check # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -706,10 +706,10 @@ legalized: true # CHECK-LABEL: name: trunc_check # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -729,11 +729,11 @@ legalized: true # CHECK-LABEL: name: test_gep # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -757,9 +757,9 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -782,9 +782,9 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -807,9 +807,9 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -832,9 +832,9 @@ legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: "" } registers: - { id: 0, class: _ } - { id: 1, class: _ } Index: llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir @@ -32,19 +32,19 @@ legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -74,19 +74,19 @@ legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -116,19 +116,19 @@ legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -158,19 +158,19 @@ legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } Index: llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir @@ -30,19 +30,19 @@ legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -70,19 +70,19 @@ legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -110,19 +110,19 @@ legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -150,19 +150,19 @@ legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } Index: llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir @@ -31,9 +31,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -57,9 +57,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -83,9 +83,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -109,9 +109,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } Index: llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir @@ -13,16 +13,16 @@ legalized: true regBankSelected: true # X32: registers: -# X32-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# X32-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# X32-NEXT: - { id: 2, class: gr32, preferred-register: '' } -# X32-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# X32-NEXT: - { id: 4, class: gpr, preferred-register: '' } -# X32-NEXT: - { id: 5, class: gr32, preferred-register: '' } -# X32-NEXT: - { id: 6, class: gr32, preferred-register: '' } -# X32-NEXT: - { id: 7, class: gr32, preferred-register: '' } -# X32-NEXT: - { id: 8, class: gr32, preferred-register: '' } -# X32-NEXT: - { id: 9, class: gpr, preferred-register: '' } +# X32-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# X32-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# X32-NEXT: - { id: 2, class: gr32, preferred-register: "" } +# X32-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# X32-NEXT: - { id: 4, class: gpr, preferred-register: "" } +# X32-NEXT: - { id: 5, class: gr32, preferred-register: "" } +# X32-NEXT: - { id: 6, class: gr32, preferred-register: "" } +# X32-NEXT: - { id: 7, class: gr32, preferred-register: "" } +# X32-NEXT: - { id: 8, class: gr32, preferred-register: "" } +# X32-NEXT: - { id: 9, class: gpr, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } Index: llvm/test/CodeGen/X86/GlobalISel/select-add.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-add.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-add.mir @@ -51,9 +51,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr64, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr64, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -78,9 +78,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -106,9 +106,9 @@ regBankSelected: true selected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr16, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr16, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -135,9 +135,9 @@ regBankSelected: true selected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr8, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr8, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -165,12 +165,12 @@ selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -200,12 +200,12 @@ selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -235,12 +235,12 @@ selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -271,12 +271,12 @@ selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } Index: llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir @@ -87,11 +87,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -124,11 +124,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr16, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr16, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -161,11 +161,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr64, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -198,11 +198,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -235,11 +235,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -272,11 +272,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -309,11 +309,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -346,11 +346,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -383,11 +383,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -420,11 +420,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -457,11 +457,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -494,11 +494,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -531,11 +531,11 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: "" } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } Index: llvm/test/CodeGen/X86/GlobalISel/select-constant.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-constant.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-constant.mir @@ -33,7 +33,7 @@ selected: false # CHECK-LABEL: name: const_i8 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr8, preferred-register: "" } registers: - { id: 0, class: gpr } # CHECK: body: @@ -52,7 +52,7 @@ selected: false # CHECK-LABEL: name: const_i16 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr16, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr16, preferred-register: "" } registers: - { id: 0, class: gpr } # CHECK: body: @@ -71,7 +71,7 @@ selected: false # CHECK-LABEL: name: const_i32 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } # CHECK: body: @@ -90,7 +90,7 @@ selected: false # CHECK-LABEL: name: const_i64 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: "" } registers: - { id: 0, class: gpr } # CHECK: body: @@ -110,7 +110,7 @@ selected: false # CHECK-LABEL: name: const_i64_u32 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: "" } registers: - { id: 0, class: gpr } # CHECK: body: @@ -129,7 +129,7 @@ selected: false # CHECK-LABEL: name: const_i64_i32 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: "" } registers: - { id: 0, class: gpr } # CHECK: body: Index: llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir @@ -25,10 +25,10 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr8, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr64, preferred-register: "" } +# ALL-NEXT: - { id: 3, class: gr64, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -57,8 +57,8 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr64, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -83,8 +83,8 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr64, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } Index: llvm/test/CodeGen/X86/GlobalISel/select-ext.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-ext.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-ext.mir @@ -35,9 +35,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -63,8 +63,8 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -89,8 +89,8 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -115,8 +115,8 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -141,8 +141,8 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } Index: llvm/test/CodeGen/X86/GlobalISel/select-gep.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-gep.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-gep.mir @@ -14,9 +14,9 @@ selected: false # CHECK-LABEL: name: test_gep_i32 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr64_nosp, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr64, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr64_nosp, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: gr64, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } Index: llvm/test/CodeGen/X86/GlobalISel/select-inc.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-inc.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-inc.mir @@ -13,10 +13,10 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# INC-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# ADD-NEXT: - { id: 1, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: "" } +# INC-NEXT: - { id: 1, class: gpr, preferred-register: "" } +# ADD-NEXT: - { id: 1, class: gr8, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr8, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } Index: llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir @@ -29,7 +29,7 @@ selected: false # CHECK-LABEL: name: const_i32_1 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } # CHECK: body: @@ -47,7 +47,7 @@ selected: false # CHECK-LABEL: name: const_i32_1_optsize # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } # CHECK: body: @@ -65,7 +65,7 @@ selected: false # CHECK-LABEL: name: const_i32_1b # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } # CHECK: body: @@ -83,7 +83,7 @@ selected: false # CHECK-LABEL: name: const_i32_1_optsizeb # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } # CHECK: body: Index: llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir @@ -49,9 +49,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr8, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -79,9 +79,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr16, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -109,9 +109,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -139,10 +139,10 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 3, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -176,10 +176,10 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 3, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -213,10 +213,10 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 3, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -250,9 +250,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -280,10 +280,10 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 3, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } Index: llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir @@ -91,8 +91,8 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr8, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# ALL: - { id: 1, class: gr8, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -115,8 +115,8 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr16, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# ALL: - { id: 1, class: gr16, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -139,8 +139,8 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr32, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# ALL: - { id: 1, class: gr32, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -163,8 +163,8 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -187,8 +187,8 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr32, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# ALL: - { id: 1, class: gr32, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -211,9 +211,9 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# NO_AVX512F: - { id: 1, class: fr32, preferred-register: '' } -# AVX512ALL: - { id: 1, class: fr32x, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# NO_AVX512F: - { id: 1, class: fr32, preferred-register: "" } +# AVX512ALL: - { id: 1, class: fr32x, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: vecr } # ALL: %0 = COPY %rdi @@ -238,8 +238,8 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -262,9 +262,9 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# NO_AVX512F: - { id: 1, class: fr64, preferred-register: '' } -# AVX512ALL: - { id: 1, class: fr64x, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# NO_AVX512F: - { id: 1, class: fr64, preferred-register: "" } +# AVX512ALL: - { id: 1, class: fr64x, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: vecr } # ALL: %0 = COPY %rdi @@ -289,8 +289,8 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr32, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } +# ALL: - { id: 0, class: gr32, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %edi @@ -315,8 +315,8 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -341,9 +341,9 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: fr32x, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } -# ALL: - { id: 2, class: gr32, preferred-register: '' } +# ALL: - { id: 0, class: fr32x, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } +# ALL: - { id: 2, class: gr32, preferred-register: "" } - { id: 0, class: vecr } - { id: 1, class: gpr } - { id: 2, class: gpr } @@ -371,9 +371,9 @@ legalized: true regBankSelected: true registers: -# NO_AVX512F: - { id: 0, class: fr32, preferred-register: '' } -# AVX512ALL: - { id: 0, class: fr32x, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } +# NO_AVX512F: - { id: 0, class: fr32, preferred-register: "" } +# AVX512ALL: - { id: 0, class: fr32x, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } - { id: 0, class: vecr } - { id: 1, class: gpr } # ALL: %0 = COPY %xmm0 @@ -400,9 +400,9 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: fr64x, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } -# ALL: - { id: 2, class: gr64, preferred-register: '' } +# ALL: - { id: 0, class: fr64x, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } +# ALL: - { id: 2, class: gr64, preferred-register: "" } - { id: 0, class: vecr } - { id: 1, class: gpr } - { id: 2, class: gpr } @@ -430,9 +430,9 @@ legalized: true regBankSelected: true registers: -# NO_AVX512F: - { id: 0, class: fr64, preferred-register: '' } -# AVX512ALL: - { id: 0, class: fr64x, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } +# NO_AVX512F: - { id: 0, class: fr64, preferred-register: "" } +# AVX512ALL: - { id: 0, class: fr64x, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } - { id: 0, class: vecr } - { id: 1, class: gpr } # ALL: %0 = COPY %xmm0 @@ -460,8 +460,8 @@ regBankSelected: true selected: false registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1) @@ -483,8 +483,8 @@ regBankSelected: true selected: false registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into %ir.ptr1) Index: llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir @@ -32,9 +32,9 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# NO_AVX512F: - { id: 1, class: vr128, preferred-register: '' } -# AVX512ALL: - { id: 1, class: vr128x, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# NO_AVX512F: - { id: 1, class: vr128, preferred-register: "" } +# AVX512ALL: - { id: 1, class: vr128x, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: vecr } # ALL: %0 = COPY %rdi @@ -60,9 +60,9 @@ legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# NO_AVX512F: - { id: 1, class: vr128, preferred-register: '' } -# AVX512ALL: - { id: 1, class: vr128x, preferred-register: '' } +# ALL: - { id: 0, class: gr64, preferred-register: "" } +# NO_AVX512F: - { id: 1, class: vr128, preferred-register: "" } +# AVX512ALL: - { id: 1, class: vr128x, preferred-register: "" } - { id: 0, class: gpr } - { id: 1, class: vecr } # ALL: %0 = COPY %rdi @@ -88,9 +88,9 @@ legalized: true regBankSelected: true registers: -# NO_AVX512F: - { id: 0, class: vr128, preferred-register: '' } -# AVX512ALL: - { id: 0, class: vr128x, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } +# NO_AVX512F: - { id: 0, class: vr128, preferred-register: "" } +# AVX512ALL: - { id: 0, class: vr128x, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } - { id: 0, class: vecr } - { id: 1, class: gpr } # ALL: %0 = COPY %xmm0 @@ -118,9 +118,9 @@ legalized: true regBankSelected: true registers: -# NO_AVX512F: - { id: 0, class: vr128, preferred-register: '' } -# AVX512ALL: - { id: 0, class: vr128x, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } +# NO_AVX512F: - { id: 0, class: vr128, preferred-register: "" } +# AVX512ALL: - { id: 0, class: vr128x, preferred-register: "" } +# ALL: - { id: 1, class: gr64, preferred-register: "" } - { id: 0, class: vecr } - { id: 1, class: gpr } # ALL: %0 = COPY %xmm0 Index: llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir @@ -33,12 +33,12 @@ legalized: true regBankSelected: true # NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: "" } # # AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: vecr } @@ -73,12 +73,12 @@ legalized: true regBankSelected: true # NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: "" } # # AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: vecr } @@ -113,12 +113,12 @@ legalized: true regBankSelected: true # NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: "" } # # AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: gpr } @@ -153,12 +153,12 @@ legalized: true regBankSelected: true # NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: "" } # # AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: gpr } Index: llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir @@ -28,8 +28,8 @@ legalized: true regBankSelected: true # AVX512F: registers: -# AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# AVX512F-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# AVX512F-NEXT: - { id: 1, class: vr512, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: vecr } @@ -54,8 +54,8 @@ legalized: true regBankSelected: true # AVX512F: registers: -# AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# AVX512F-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# AVX512F-NEXT: - { id: 1, class: vr512, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: vecr } @@ -80,8 +80,8 @@ legalized: true regBankSelected: true # AVX512F: registers: -# AVX512F-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# AVX512F-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: gpr } @@ -106,8 +106,8 @@ legalized: true regBankSelected: true # AVX512F: registers: -# AVX512F-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# AVX512F-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: gpr } Index: llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir @@ -24,9 +24,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr16, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr16, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -55,9 +55,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -86,9 +86,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr64, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr64, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } Index: llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir @@ -95,9 +95,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -121,9 +121,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -147,9 +147,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -173,9 +173,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -199,9 +199,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -225,9 +225,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -251,9 +251,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -277,9 +277,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr256, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -303,9 +303,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -329,9 +329,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr256, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -355,9 +355,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -381,9 +381,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -407,9 +407,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -433,9 +433,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -459,9 +459,9 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: "" } +# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } Index: llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir @@ -32,19 +32,19 @@ legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -74,19 +74,19 @@ legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -116,19 +116,19 @@ legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -158,19 +158,19 @@ legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } Index: llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir @@ -30,19 +30,19 @@ legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -70,19 +70,19 @@ legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -110,19 +110,19 @@ legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -150,19 +150,19 @@ legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: "" } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: "" } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: "" } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } Index: llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir @@ -31,9 +31,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -57,9 +57,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -83,9 +83,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -109,9 +109,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } Index: llvm/test/CodeGen/X86/GlobalISel/select-sub.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-sub.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-sub.mir @@ -40,9 +40,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr64, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr64, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -66,9 +66,9 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: "" } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -94,12 +94,12 @@ selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -128,12 +128,12 @@ selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: "" } +# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: "" } +# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -161,12 +161,12 @@ selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -196,12 +196,12 @@ selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: "" } +# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: "" } +# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: "" } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: "" } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: "" } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } Index: llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir =================================================================== --- llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir +++ llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir @@ -38,8 +38,8 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -64,8 +64,8 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -90,8 +90,8 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -116,8 +116,8 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64_with_sub_8bit, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr64_with_sub_8bit, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -142,8 +142,8 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -168,8 +168,8 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: "" } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: "" } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } Index: llvm/test/CodeGen/X86/stack-protector-remarks.ll =================================================================== --- llvm/test/CodeGen/X86/stack-protector-remarks.ll +++ llvm/test/CodeGen/X86/stack-protector-remarks.ll @@ -37,9 +37,9 @@ ; YAML-NEXT: Name: StackProtectorRequested ; YAML-NEXT: Function: attribute_ssp ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'Stack protection applied to function ' +; YAML-NEXT: - String: "Stack protection applied to function " ; YAML-NEXT: - Function: attribute_ssp -; YAML-NEXT: - String: ' due to a function attribute or command-line switch' +; YAML-NEXT: - String: " due to a function attribute or command-line switch" ; YAML-NEXT: ... define void @nossp() ssp { Index: llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll =================================================================== --- llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll +++ llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=x86_64-unknown-unknown -o - -stop-after machine-scheduler %s | FileCheck %s --check-prefix=PRE-RA ; RUN: llc -mtriple=x86_64-unknown-unknown -o - -stop-after prologepilog %s | FileCheck %s --check-prefix=POST-RA -; This test verifies that the virtual register references in machine function's +; This test verifies that the virtual register references in machine function"s ; liveins are cleared after register allocation. define i32 @test(i32 %a, i32 %b) { @@ -11,9 +11,9 @@ } ; PRE-RA: liveins: -; PRE-RA-NEXT: - { reg: '%edi', virtual-reg: '%0' } -; PRE-RA-NEXT: - { reg: '%esi', virtual-reg: '%1' } +; PRE-RA-NEXT: - { reg: "%edi", virtual-reg: "%0" } +; PRE-RA-NEXT: - { reg: "%esi", virtual-reg: "%1" } ; POST-RA: liveins: -; POST-RA-NEXT: - { reg: '%edi', virtual-reg: '' } -; POST-RA-NEXT: - { reg: '%esi', virtual-reg: '' } +; POST-RA-NEXT: - { reg: "%edi", virtual-reg: "" } +; POST-RA-NEXT: - { reg: "%esi", virtual-reg: "" } Index: llvm/test/DebugInfo/PDB/Inputs/one-symbol.yaml =================================================================== --- llvm/test/DebugInfo/PDB/Inputs/one-symbol.yaml +++ llvm/test/DebugInfo/PDB/Inputs/one-symbol.yaml @@ -7,5 +7,5 @@ - Kind: S_OBJNAME ObjNameSym: Signature: 0 - ObjectName: 'c:\foo\one-symbol.yaml' + ObjectName: "c:\\foo\\one-symbol.yaml" ... Index: llvm/test/DebugInfo/PDB/pdb-yaml-symbols.test =================================================================== --- llvm/test/DebugInfo/PDB/pdb-yaml-symbols.test +++ llvm/test/DebugInfo/PDB/pdb-yaml-symbols.test @@ -24,15 +24,15 @@ YAML: Flags: 1 YAML: MachineType: x86 YAML: Modules: -YAML: - Module: 'd:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj' -YAML: ObjFile: 'd:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj' +YAML: - Module: "d:\\src\\llvm\\test\\DebugInfo\\PDB\\Inputs\\empty.obj" +YAML: ObjFile: "d:\\src\\llvm\\test\\DebugInfo\\PDB\\Inputs\\empty.obj" YAML: Modi: YAML: Signature: 4 YAML: Records: YAML: - Kind: S_OBJNAME YAML: ObjNameSym: YAML: Signature: 0 -YAML: ObjectName: 'd:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj' +YAML: ObjectName: "d:\\src\\llvm\\test\\DebugInfo\\PDB\\Inputs\\empty.obj" YAML: - Kind: S_COMPILE3 YAML: Compile3Sym: YAML: Flags: [ SecurityChecks ] @@ -45,7 +45,7 @@ YAML: BackendMinor: 0 YAML: BackendBuild: 31101 YAML: BackendQFE: 0 -YAML: Version: 'Microsoft (R) Optimizing Compiler' +YAML: Version: "Microsoft (R) Optimizing Compiler" YAML: - Kind: S_GPROC32 YAML: ProcSym: YAML: PtrParent: 0 @@ -72,15 +72,15 @@ YAML: - Kind: S_BUILDINFO YAML: BuildInfoSym: YAML: BuildId: 4110 -YAML: - Module: '* Linker *' -YAML: ObjFile: '' +YAML: - Module: "* Linker *" +YAML: ObjFile: "" YAML: Modi: YAML: Signature: 4 YAML: Records: YAML: - Kind: S_OBJNAME YAML: ObjNameSym: YAML: Signature: 0 -YAML: ObjectName: '* Linker *' +YAML: ObjectName: "* Linker *" YAML: - Kind: S_COMPILE3 YAML: Compile3Sym: YAML: Flags: [ ] @@ -93,16 +93,16 @@ YAML: BackendMinor: 0 YAML: BackendBuild: 31101 YAML: BackendQFE: 0 -YAML: Version: 'Microsoft (R) LINK' +YAML: Version: "Microsoft (R) LINK" YAML: - Kind: S_ENVBLOCK YAML: EnvBlockSym: YAML: Entries: YAML: - cwd -YAML: - 'd:\src\llvm\test\DebugInfo\PDB\Inputs' +YAML: - "d:\\src\\llvm\\test\\DebugInfo\\PDB\\Inputs" YAML: - exe -YAML: - 'C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\BIN\link.exe' +YAML: - "C:\\Program Files (x86)\\Microsoft Visual Studio 12.0\\VC\\BIN\\link.exe" YAML: - pdb -YAML: - 'd:\src\llvm\test\DebugInfo\PDB\Inputs\empty.pdb' +YAML: - "d:\\src\\llvm\\test\\DebugInfo\\PDB\\Inputs\\empty.pdb" YAML: - Kind: S_TRAMPOLINE YAML: TrampolineSym: YAML: Type: TrampIncremental @@ -125,7 +125,7 @@ YAML: Characteristics: 1610612768 YAML: Offset: 0 YAML: Segment: 1 -YAML: Name: '.text$mn' +YAML: Name: ".text$mn" YAML: - Kind: S_SECTION YAML: SectionSym: YAML: SectionNumber: 2 @@ -154,7 +154,7 @@ YAML: Characteristics: 1073741888 YAML: Offset: 324 YAML: Segment: 2 -YAML: Name: '.rdata$debug' +YAML: Name: ".rdata$debug" YAML: - Kind: S_SECTION YAML: SectionSym: YAML: SectionNumber: 3 Index: llvm/test/DebugInfo/PDB/pdbdump-debug-subsections.test =================================================================== --- llvm/test/DebugInfo/PDB/pdbdump-debug-subsections.test +++ llvm/test/DebugInfo/PDB/pdbdump-debug-subsections.test @@ -25,17 +25,17 @@ YAML-NEXT: Imports: YAML-NEXT: - Module: Foo.obj YAML-NEXT: Imports: [ 4852, 2147487875 ] -YAML: - Module: 'd:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj' -YAML-NEXT: ObjFile: 'd:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj' +YAML: - Module: "d:\\src\\llvm\\test\\DebugInfo\\PDB\\Inputs\\empty.obj" +YAML-NEXT: ObjFile: "d:\\src\\llvm\\test\\DebugInfo\\PDB\\Inputs\\empty.obj" YAML-NEXT: SourceFiles: -YAML-NEXT: - 'd:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp' +YAML-NEXT: - "d:\\src\\llvm\\test\\debuginfo\\pdb\\inputs\\empty.cpp" YAML-NEXT: Subsections: YAML-NEXT: - !FileChecksums YAML-NEXT: Checksums: -YAML-NEXT: - FileName: 'd:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp' +YAML-NEXT: - FileName: "d:\\src\\llvm\\test\\debuginfo\\pdb\\inputs\\empty.cpp" YAML-NEXT: Kind: MD5 YAML-NEXT: Checksum: A0A5BD0D3ECD93FC29D19DE826FBF4BC -YAML-NEXT: - FileName: 'f:\dd\externalapis\windows\10\sdk\inc\winerror.h' +YAML-NEXT: - FileName: "f:\\dd\\externalapis\\windows\\10\\sdk\\inc\\winerror.h" YAML-NEXT: Kind: MD5 YAML-NEXT: Checksum: 1154D69F5B2650196E1FC34F4134E56B YAML-NEXT: - !Lines @@ -44,7 +44,7 @@ YAML-NEXT: RelocOffset: 100016 YAML-NEXT: RelocSegment: 1 YAML-NEXT: Blocks: -YAML-NEXT: - FileName: 'd:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp' +YAML-NEXT: - FileName: "d:\\src\\llvm\\test\\debuginfo\\pdb\\inputs\\empty.cpp" YAML-NEXT: Lines: YAML-NEXT: - Offset: 0 YAML-NEXT: LineStart: 5 @@ -62,7 +62,7 @@ YAML-NEXT: - !InlineeLines YAML-NEXT: HasExtraFiles: false YAML-NEXT: Sites: -YAML-NEXT: - FileName: 'f:\dd\externalapis\windows\10\sdk\inc\winerror.h' +YAML-NEXT: - FileName: "f:\\dd\\externalapis\\windows\\10\\sdk\\inc\\winerror.h" YAML-NEXT: LineNum: 26950 YAML-NEXT: Inlinee: 22767 Index: llvm/test/DebugInfo/PDB/pdbdump-source-names.test =================================================================== --- llvm/test/DebugInfo/PDB/pdbdump-source-names.test +++ llvm/test/DebugInfo/PDB/pdbdump-source-names.test @@ -14,7 +14,7 @@ RUN: | FileCheck -check-prefix=CHECK2 %s CHECK1: SourceFiles: -CHECK1: 'C:\src\test.c' +CHECK1: "C:\\src\\test.c" CHECK2: SourceFiles: -CHECK2: 'C:\src\test.cc' +CHECK2: "C:\\src\\test.cc" Index: llvm/test/DebugInfo/PDB/pdbdump-yaml-types.test =================================================================== --- llvm/test/DebugInfo/PDB/pdbdump-yaml-types.test +++ llvm/test/DebugInfo/PDB/pdbdump-yaml-types.test @@ -55,16 +55,16 @@ YAML: NumEnumerators: 5 YAML: Options: [ None, Nested, HasUniqueName ] YAML: FieldList: 4098 -YAML: Name: '__vc_attributes::threadingAttribute::threading_e' -YAML: UniqueName: '.?AW4threading_e@threadingAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::threadingAttribute::threading_e" +YAML: UniqueName: ".?AW4threading_e@threadingAttribute@__vc_attributes@@" YAML: UnderlyingType: 116 YAML: - Kind: LF_STRUCTURE YAML: Class: YAML: MemberCount: 0 YAML: Options: [ None, ForwardReference, HasUniqueName ] YAML: FieldList: 0 -YAML: Name: '__vc_attributes::threadingAttribute' -YAML: UniqueName: '.?AUthreadingAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::threadingAttribute" +YAML: UniqueName: ".?AUthreadingAttribute@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 0 @@ -101,11 +101,11 @@ YAML: - Type: 4103 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Type: 4104 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Kind: LF_FIELDLIST YAML: FieldList: YAML: - Kind: LF_NESTTYPE @@ -128,8 +128,8 @@ YAML: MemberCount: 4 YAML: Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] YAML: FieldList: 4106 -YAML: Name: '__vc_attributes::threadingAttribute' -YAML: UniqueName: '.?AUthreadingAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::threadingAttribute" +YAML: UniqueName: ".?AUthreadingAttribute@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 4 @@ -155,16 +155,16 @@ YAML: NumEnumerators: 3 YAML: Options: [ None, Nested, HasUniqueName ] YAML: FieldList: 4108 -YAML: Name: '__vc_attributes::event_receiverAttribute::type_e' -YAML: UniqueName: '.?AW4type_e@event_receiverAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::event_receiverAttribute::type_e" +YAML: UniqueName: ".?AW4type_e@event_receiverAttribute@__vc_attributes@@" YAML: UnderlyingType: 116 YAML: - Kind: LF_STRUCTURE YAML: Class: YAML: MemberCount: 0 YAML: Options: [ None, ForwardReference, HasUniqueName ] YAML: FieldList: 0 -YAML: Name: '__vc_attributes::event_receiverAttribute' -YAML: UniqueName: '.?AUevent_receiverAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::event_receiverAttribute" +YAML: UniqueName: ".?AUevent_receiverAttribute@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 0 @@ -214,15 +214,15 @@ YAML: - Type: 4113 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Type: 4115 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Type: 4116 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Kind: LF_FIELDLIST YAML: FieldList: YAML: - Kind: LF_NESTTYPE @@ -251,8 +251,8 @@ YAML: MemberCount: 6 YAML: Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] YAML: FieldList: 4118 -YAML: Name: '__vc_attributes::event_receiverAttribute' -YAML: UniqueName: '.?AUevent_receiverAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::event_receiverAttribute" +YAML: UniqueName: ".?AUevent_receiverAttribute@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 8 @@ -278,16 +278,16 @@ YAML: NumEnumerators: 3 YAML: Options: [ None, Nested, HasUniqueName ] YAML: FieldList: 4120 -YAML: Name: '__vc_attributes::aggregatableAttribute::type_e' -YAML: UniqueName: '.?AW4type_e@aggregatableAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::aggregatableAttribute::type_e" +YAML: UniqueName: ".?AW4type_e@aggregatableAttribute@__vc_attributes@@" YAML: UnderlyingType: 116 YAML: - Kind: LF_STRUCTURE YAML: Class: YAML: MemberCount: 0 YAML: Options: [ None, ForwardReference, HasUniqueName ] YAML: FieldList: 0 -YAML: Name: '__vc_attributes::aggregatableAttribute' -YAML: UniqueName: '.?AUaggregatableAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::aggregatableAttribute" +YAML: UniqueName: ".?AUaggregatableAttribute@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 0 @@ -324,11 +324,11 @@ YAML: - Type: 4125 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Type: 4126 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Kind: LF_FIELDLIST YAML: FieldList: YAML: - Kind: LF_NESTTYPE @@ -351,8 +351,8 @@ YAML: MemberCount: 4 YAML: Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] YAML: FieldList: 4128 -YAML: Name: '__vc_attributes::aggregatableAttribute' -YAML: UniqueName: '.?AUaggregatableAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::aggregatableAttribute" +YAML: UniqueName: ".?AUaggregatableAttribute@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 4 @@ -361,8 +361,8 @@ YAML: NumEnumerators: 3 YAML: Options: [ None, Nested, HasUniqueName ] YAML: FieldList: 4108 -YAML: Name: '__vc_attributes::event_sourceAttribute::type_e' -YAML: UniqueName: '.?AW4type_e@event_sourceAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::event_sourceAttribute::type_e" +YAML: UniqueName: ".?AW4type_e@event_sourceAttribute@__vc_attributes@@" YAML: UnderlyingType: 116 YAML: - Kind: LF_FIELDLIST YAML: FieldList: @@ -381,16 +381,16 @@ YAML: NumEnumerators: 2 YAML: Options: [ None, Nested, HasUniqueName ] YAML: FieldList: 4131 -YAML: Name: '__vc_attributes::event_sourceAttribute::optimize_e' -YAML: UniqueName: '.?AW4optimize_e@event_sourceAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::event_sourceAttribute::optimize_e" +YAML: UniqueName: ".?AW4optimize_e@event_sourceAttribute@__vc_attributes@@" YAML: UnderlyingType: 116 YAML: - Kind: LF_STRUCTURE YAML: Class: YAML: MemberCount: 0 YAML: Options: [ None, ForwardReference, HasUniqueName ] YAML: FieldList: 0 -YAML: Name: '__vc_attributes::event_sourceAttribute' -YAML: UniqueName: '.?AUevent_sourceAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::event_sourceAttribute" +YAML: UniqueName: ".?AUevent_sourceAttribute@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 0 @@ -427,11 +427,11 @@ YAML: - Type: 4136 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Type: 4137 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Kind: LF_FIELDLIST YAML: FieldList: YAML: - Kind: LF_NESTTYPE @@ -470,8 +470,8 @@ YAML: MemberCount: 7 YAML: Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] YAML: FieldList: 4139 -YAML: Name: '__vc_attributes::event_sourceAttribute' -YAML: UniqueName: '.?AUevent_sourceAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::event_sourceAttribute" +YAML: UniqueName: ".?AUevent_sourceAttribute@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 12 @@ -512,16 +512,16 @@ YAML: NumEnumerators: 6 YAML: Options: [ None, Nested, HasUniqueName ] YAML: FieldList: 4141 -YAML: Name: '__vc_attributes::moduleAttribute::type_e' -YAML: UniqueName: '.?AW4type_e@moduleAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::moduleAttribute::type_e" +YAML: UniqueName: ".?AW4type_e@moduleAttribute@__vc_attributes@@" YAML: UnderlyingType: 116 YAML: - Kind: LF_STRUCTURE YAML: Class: YAML: MemberCount: 0 YAML: Options: [ None, ForwardReference, HasUniqueName ] YAML: FieldList: 0 -YAML: Name: '__vc_attributes::moduleAttribute' -YAML: UniqueName: '.?AUmoduleAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::moduleAttribute" +YAML: UniqueName: ".?AUmoduleAttribute@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 0 @@ -580,15 +580,15 @@ YAML: - Type: 4148 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Type: 4150 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Type: 4151 YAML: Attrs: 3 YAML: VFTableOffset: -1 -YAML: Name: '' +YAML: Name: "" YAML: - Kind: LF_FIELDLIST YAML: FieldList: YAML: - Kind: LF_NESTTYPE @@ -695,8 +695,8 @@ YAML: MemberCount: 19 YAML: Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] YAML: FieldList: 4153 -YAML: Name: '__vc_attributes::moduleAttribute' -YAML: UniqueName: '.?AUmoduleAttribute@__vc_attributes@@' +YAML: Name: "__vc_attributes::moduleAttribute" +YAML: UniqueName: ".?AUmoduleAttribute@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 56 @@ -857,16 +857,16 @@ YAML: NumEnumerators: 30 YAML: Options: [ None, Nested, HasUniqueName ] YAML: FieldList: 4155 -YAML: Name: '__vc_attributes::helper_attributes::usageAttribute::usage_e' -YAML: UniqueName: '.?AW4usage_e@usageAttribute@helper_attributes@__vc_attributes@@' +YAML: Name: "__vc_attributes::helper_attributes::usageAttribute::usage_e" +YAML: UniqueName: ".?AW4usage_e@usageAttribute@helper_attributes@__vc_attributes@@" YAML: UnderlyingType: 116 YAML: - Kind: LF_STRUCTURE YAML: Class: YAML: MemberCount: 0 YAML: Options: [ None, ForwardReference, HasUniqueName ] YAML: FieldList: 0 -YAML: Name: '__vc_attributes::helper_attributes::usageAttribute' -YAML: UniqueName: '.?AUusageAttribute@helper_attributes@__vc_attributes@@' +YAML: Name: "__vc_attributes::helper_attributes::usageAttribute" +YAML: UniqueName: ".?AUusageAttribute@helper_attributes@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 0 @@ -910,8 +910,8 @@ YAML: MemberCount: 3 YAML: Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] YAML: FieldList: 4161 -YAML: Name: '__vc_attributes::helper_attributes::usageAttribute' -YAML: UniqueName: '.?AUusageAttribute@helper_attributes@__vc_attributes@@' +YAML: Name: "__vc_attributes::helper_attributes::usageAttribute" +YAML: UniqueName: ".?AUusageAttribute@helper_attributes@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 4 @@ -942,16 +942,16 @@ YAML: NumEnumerators: 4 YAML: Options: [ None, Nested, HasUniqueName ] YAML: FieldList: 4163 -YAML: Name: '__vc_attributes::helper_attributes::v1_alttypeAttribute::type_e' -YAML: UniqueName: '.?AW4type_e@v1_alttypeAttribute@helper_attributes@__vc_attributes@@' +YAML: Name: "__vc_attributes::helper_attributes::v1_alttypeAttribute::type_e" +YAML: UniqueName: ".?AW4type_e@v1_alttypeAttribute@helper_attributes@__vc_attributes@@" YAML: UnderlyingType: 116 YAML: - Kind: LF_STRUCTURE YAML: Class: YAML: MemberCount: 0 YAML: Options: [ None, ForwardReference, HasUniqueName ] YAML: FieldList: 0 -YAML: Name: '__vc_attributes::helper_attributes::v1_alttypeAttribute' -YAML: UniqueName: '.?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@' +YAML: Name: "__vc_attributes::helper_attributes::v1_alttypeAttribute" +YAML: UniqueName: ".?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 0 @@ -995,8 +995,8 @@ YAML: MemberCount: 3 YAML: Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] YAML: FieldList: 4169 -YAML: Name: '__vc_attributes::helper_attributes::v1_alttypeAttribute' -YAML: UniqueName: '.?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@' +YAML: Name: "__vc_attributes::helper_attributes::v1_alttypeAttribute" +YAML: UniqueName: ".?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@" YAML: DerivationList: 0 YAML: VTableShape: 0 YAML: Size: 4 Index: llvm/test/DebugInfo/PDB/pdbdump-yaml.test =================================================================== --- llvm/test/DebugInfo/PDB/pdbdump-yaml.test +++ llvm/test/DebugInfo/PDB/pdbdump-yaml.test @@ -37,12 +37,12 @@ ; YAML-NEXT: - Stream: [ 21 ] ; YAML-NEXT: - Stream: [ 22 ] ; YAML-NEXT: StringTable: -; YAML-NEXT: - 'd:\src\llvm\test\debuginfo\pdb\inputs\predefined c++ attributes (compiler internal)' -; YAML-NEXT: - 'd:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp' -; YAML-NEXT: - '$T0 $ebp = $eip $T0 4 + ^ = $ebp $T0 ^ = $esp $T0 8 + = ' +; YAML-NEXT: - "d:\\src\\llvm\\test\\debuginfo\\pdb\\inputs\\predefined c++ attributes (compiler internal)" +; YAML-NEXT: - "d:\\src\\llvm\\test\\debuginfo\\pdb\\inputs\\empty.cpp" +; YAML-NEXT: - "$T0 $ebp = $eip $T0 4 + ^ = $ebp $T0 ^ = $esp $T0 8 + = " ; YAML-NEXT: PdbStream: ; YAML-NEXT: Age: 1 -; YAML-NEXT: Guid: '{0B355641-86A0-A249-896F-9988FAE52FF0}' +; YAML-NEXT: Guid: "{0B355641-86A0-A249-896F-9988FAE52FF0}" ; YAML-NEXT: Signature: 1424295906 ; YAML-NEXT: Features: [ VC110 ] ; YAML-NEXT: Version: VC70 Index: llvm/test/LTO/Resolution/X86/diagnostic-handler-remarks-with-hotness.ll =================================================================== --- llvm/test/LTO/Resolution/X86/diagnostic-handler-remarks-with-hotness.ll +++ llvm/test/LTO/Resolution/X86/diagnostic-handler-remarks-with-hotness.ll @@ -15,7 +15,7 @@ ; YAML-NEXT: Hotness: 300 ; YAML-NEXT: Args: ; YAML-NEXT: - Callee: tinkywinky -; YAML-NEXT: - String: ' inlined into ' +; YAML-NEXT: - String: " inlined into " ; YAML-NEXT: - Caller: main ; YAML-NEXT: ... Index: llvm/test/LTO/Resolution/X86/diagnostic-handler-remarks.ll =================================================================== --- llvm/test/LTO/Resolution/X86/diagnostic-handler-remarks.ll +++ llvm/test/LTO/Resolution/X86/diagnostic-handler-remarks.ll @@ -13,7 +13,7 @@ ; YAML-NEXT: Function: main ; YAML-NEXT: Args: ; YAML-NEXT: - Callee: tinkywinky -; YAML-NEXT: - String: ' inlined into ' +; YAML-NEXT: - String: " inlined into " ; YAML-NEXT: - Caller: main ; YAML-NEXT: ... Index: llvm/test/LTO/X86/diagnostic-handler-remarks-with-hotness.ll =================================================================== --- llvm/test/LTO/X86/diagnostic-handler-remarks-with-hotness.ll +++ llvm/test/LTO/X86/diagnostic-handler-remarks-with-hotness.ll @@ -15,7 +15,7 @@ ; YAML-NEXT: Hotness: 300 ; YAML-NEXT: Args: ; YAML-NEXT: - Callee: foo -; YAML-NEXT: - String: ' inlined into ' +; YAML-NEXT: - String: " inlined into " ; YAML-NEXT: - Caller: main ; YAML-NEXT: ... Index: llvm/test/LTO/X86/diagnostic-handler-remarks.ll =================================================================== --- llvm/test/LTO/X86/diagnostic-handler-remarks.ll +++ llvm/test/LTO/X86/diagnostic-handler-remarks.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s >%t.bc -; PR21108: Diagnostic handlers get pass remarks, even if they're not enabled. +; PR21108: Diagnostic handlers get pass remarks, even if they"re not enabled. ; Confirm that there are -pass-remarks. ; RUN: llvm-lto -pass-remarks=inline \ @@ -51,7 +51,7 @@ ; YAML-NEXT: Function: main ; YAML-NEXT: Args: ; YAML-NEXT: - Callee: foo -; YAML-NEXT: - String: ' inlined into ' +; YAML-NEXT: - String: " inlined into " ; YAML-NEXT: - Caller: main ; YAML-NEXT: ... Index: llvm/test/Object/obj2yaml-coff-section-aux-symbol.test =================================================================== --- llvm/test/Object/obj2yaml-coff-section-aux-symbol.test +++ llvm/test/Object/obj2yaml-coff-section-aux-symbol.test @@ -3,91 +3,91 @@ COFF-I386: sections: COFF-I386-NEXT: - Name: .CRT COFF-I386: symbols: -COFF-I386: - Name: '.CRT$XCAA' +COFF-I386: - Name: ".CRT$XCAA" COFF-I386-NEXT: Value: 4 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 1 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XIAA' +COFF-I386: - Name: ".CRT$XIAA" COFF-I386-NEXT: Value: 16 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 1 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XLD' +COFF-I386: - Name: ".CRT$XLD" COFF-I386-NEXT: Value: 36 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 1 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XLC' +COFF-I386: - Name: ".CRT$XLC" COFF-I386-NEXT: Value: 32 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 1 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XDZ' +COFF-I386: - Name: ".CRT$XDZ" COFF-I386-NEXT: Value: 48 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 0 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XDA' +COFF-I386: - Name: ".CRT$XDA" COFF-I386-NEXT: Value: 44 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 0 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XLZ' +COFF-I386: - Name: ".CRT$XLZ" COFF-I386-NEXT: Value: 40 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 0 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XLA' +COFF-I386: - Name: ".CRT$XLA" COFF-I386-NEXT: Value: 28 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 0 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XIC' +COFF-I386: - Name: ".CRT$XIC" COFF-I386-NEXT: Value: 20 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 1 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XCZ' +COFF-I386: - Name: ".CRT$XCZ" COFF-I386-NEXT: Value: 8 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 0 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XCA' +COFF-I386: - Name: ".CRT$XCA" COFF-I386-NEXT: Value: 0 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 0 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XIZ' +COFF-I386: - Name: ".CRT$XIZ" COFF-I386-NEXT: Value: 24 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: COFF-I386-NEXT: Length: 4 COFF-I386-NEXT: NumberOfRelocations: 0 COFF-I386-NEXT: NumberOfLinenumbers: 0 -COFF-I386: - Name: '.CRT$XIA' +COFF-I386: - Name: ".CRT$XIA" COFF-I386-NEXT: Value: 12 COFF-I386: StorageClass: IMAGE_SYM_CLASS_STATIC COFF-I386-NEXT: SectionDefinition: Index: llvm/test/Object/obj2yaml-invalid-reloc.test =================================================================== --- llvm/test/Object/obj2yaml-invalid-reloc.test +++ llvm/test/Object/obj2yaml-invalid-reloc.test @@ -20,7 +20,7 @@ CHECK-NEXT: Info: .text CHECK-NEXT: Relocations: CHECK-NEXT: - Offset: 0x0000000000000000 -CHECK-NEXT: Symbol: '' +CHECK-NEXT: Symbol: "" CHECK-NEXT: Type: R_X86_64_NONE CHECK-NEXT: Symbols: CHECK-NEXT: Local: @@ -30,7 +30,7 @@ CHECK-NEXT: Size: 0x0000000000000005 CHECK-NEXT: Global: CHECK-NEXT: - Name: __dtraceenabled_ruby___array-create -CHECK-NEXT: - Name: '$dtrace1316529.rb_ary_new_capa' +CHECK-NEXT: - Name: "$dtrace1316529.rb_ary_new_capa" CHECK-NEXT: Type: STT_FUNC CHECK-NEXT: Section: .text CHECK-NEXT: Size: 0x0000000000000005 Index: llvm/test/Object/obj2yaml.test =================================================================== --- llvm/test/Object/obj2yaml.test +++ llvm/test/Object/obj2yaml.test @@ -117,14 +117,14 @@ COFF-X86-64-NEXT: Alignment: 1 COFF-X86-64-NEXT: SectionData: 48656C6C6F20576F726C642100 -COFF-X86-64: - Name: '.CRT$XCU' +COFF-X86-64: - Name: ".CRT$XCU" COFF-X86-64-NEXT: Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ ] COFF-X86-64-NEXT: Alignment: 8 -COFF-X86-64-NEXT: SectionData: '0000000000000000' +COFF-X86-64-NEXT: SectionData: "0000000000000000" COFF-X86-64: Relocations: COFF-X86-64-NEXT: - VirtualAddress: 0 -COFF-X86-64-NEXT: SymbolName: '??__Ex@@YAXXZ' +COFF-X86-64-NEXT: SymbolName: "??__Ex@@YAXXZ" COFF-X86-64-NEXT: Type: IMAGE_REL_AMD64_ADDR64 COFF-X86-64: symbols: @@ -182,7 +182,7 @@ COFF-X86-64-NEXT: ComplexType: IMAGE_SYM_DTYPE_NULL COFF-X86-64-NEXT: StorageClass: IMAGE_SYM_CLASS_EXTERNAL -COFF-X86-64: - Name: '??__Ex@@YAXXZ' +COFF-X86-64: - Name: "??__Ex@@YAXXZ" COFF-X86-64-NEXT: Value: 0 COFF-X86-64-NEXT: SectionNumber: 3 COFF-X86-64-NEXT: SimpleType: IMAGE_SYM_TYPE_NULL @@ -215,10 +215,10 @@ ELF-MIPSEL-NEXT: Symbol: _gp_disp ELF-MIPSEL-NEXT: Type: R_MIPS_LO16 ELF-MIPSEL-NEXT: - Offset: 0x0000000000000018 -ELF-MIPSEL-NEXT: Symbol: '$.str' +ELF-MIPSEL-NEXT: Symbol: "$.str" ELF-MIPSEL-NEXT: Type: R_MIPS_GOT16 ELF-MIPSEL-NEXT: - Offset: 0x000000000000001C -ELF-MIPSEL-NEXT: Symbol: '$.str' +ELF-MIPSEL-NEXT: Symbol: "$.str" ELF-MIPSEL-NEXT: Type: R_MIPS_LO16 ELF-MIPSEL-NEXT: - Offset: 0x0000000000000020 ELF-MIPSEL-NEXT: Symbol: puts @@ -230,7 +230,7 @@ ELF-MIPSEL-NEXT: Type: SHT_PROGBITS ELF-MIPSEL-NEXT: Flags: [ SHF_WRITE, SHF_ALLOC ] ELF-MIPSEL-NEXT: AddressAlign: 0x0000000000000004 -ELF-MIPSEL-NEXT: Content: '' +ELF-MIPSEL-NEXT: Content: "" ELF-MIPSEL-NEXT: - Name: .bss ELF-MIPSEL-NEXT: Type: SHT_NOBITS ELF-MIPSEL-NEXT: Flags: [ SHF_WRITE, SHF_ALLOC ] @@ -239,7 +239,7 @@ ELF-MIPSEL-NEXT: - Name: .mdebug.abi32 ELF-MIPSEL-NEXT: Type: SHT_PROGBITS ELF-MIPSEL-NEXT: AddressAlign: 0x0000000000000001 -ELF-MIPSEL-NEXT: Content: '' +ELF-MIPSEL-NEXT: Content: "" ELF-MIPSEL-NEXT: - Name: .rodata.str1.1 ELF-MIPSEL-NEXT: Type: SHT_PROGBITS ELF-MIPSEL-NEXT: Flags: [ SHF_ALLOC, SHF_MERGE, SHF_STRINGS ] @@ -249,7 +249,7 @@ ELF-MIPSEL-NEXT: Type: SHT_MIPS_REGINFO ELF-MIPSEL-NEXT: Flags: [ SHF_ALLOC ] ELF-MIPSEL-NEXT: AddressAlign: 0x0000000000000001 -ELF-MIPSEL-NEXT: Content: '000000000000000000000000000000000000000000000000' +ELF-MIPSEL-NEXT: Content: "000000000000000000000000000000000000000000000000" ELF-MIPSEL-NEXT: - Name: .MIPS.abiflags ELF-MIPSEL-NEXT: Type: SHT_MIPS_ABIFLAGS ELF-MIPSEL-NEXT: Flags: [ SHF_ALLOC ] @@ -264,7 +264,7 @@ ELF-MIPSEL-NEXT: Local: ELF-MIPSEL-NEXT: - Name: trivial.ll ELF-MIPSEL-NEXT: Type: STT_FILE -ELF-MIPSEL-NEXT: - Name: '$.str' +ELF-MIPSEL-NEXT: - Name: "$.str" ELF-MIPSEL-NEXT: Type: STT_OBJECT ELF-MIPSEL-NEXT: Section: .rodata.str1.1 ELF-MIPSEL-NEXT: Size: 0x000000000000000D @@ -306,12 +306,12 @@ ELF-MIPS64EL-NEXT: Type: SHT_PROGBITS ELF-MIPS64EL-NEXT: Flags: [ SHF_ALLOC, SHF_EXECINSTR ] ELF-MIPS64EL-NEXT: AddressAlign: 0x0000000000000010 -ELF-MIPS64EL-NEXT: Content: '' +ELF-MIPS64EL-NEXT: Content: "" ELF-MIPS64EL-NEXT: - Name: .data ELF-MIPS64EL-NEXT: Type: SHT_PROGBITS ELF-MIPS64EL-NEXT: Flags: [ SHF_WRITE, SHF_ALLOC ] ELF-MIPS64EL-NEXT: AddressAlign: 0x0000000000000010 -ELF-MIPS64EL-NEXT: Content: '00000000000000000000000000000000' +ELF-MIPS64EL-NEXT: Content: "00000000000000000000000000000000" ELF-MIPS64EL-NEXT: - Name: .rela.data ELF-MIPS64EL-NEXT: Type: SHT_RELA ELF-MIPS64EL-NEXT: Link: .symtab @@ -329,11 +329,11 @@ ELF-MIPS64EL-NEXT: Type: SHT_MIPS_OPTIONS ELF-MIPS64EL-NEXT: Flags: [ SHF_ALLOC, SHF_MIPS_NOSTRIP ] ELF-MIPS64EL-NEXT: AddressAlign: 0x0000000000000008 -ELF-MIPS64EL-NEXT: Content: '01280000000000000000000000000000000000000000000000000000000000000000000000000000' +ELF-MIPS64EL-NEXT: Content: "01280000000000000000000000000000000000000000000000000000000000000000000000000000" ELF-MIPS64EL-NEXT: - Name: .pdr ELF-MIPS64EL-NEXT: Type: SHT_PROGBITS ELF-MIPS64EL-NEXT: AddressAlign: 0x0000000000000004 -ELF-MIPS64EL-NEXT: Content: '' +ELF-MIPS64EL-NEXT: Content: "" ELF-MIPS64EL-NEXT: Symbols: ELF-MIPS64EL-NEXT: Local: ELF-MIPS64EL-NEXT: - Type: STT_SECTION @@ -373,7 +373,7 @@ ELF-X86-64-NEXT: Type: SHT_PROGBITS ELF-X86-64-NEXT: Address: 0x0000000000000033 ELF-X86-64-NEXT: AddressAlign: 0x0000000000000001 -ELF-X86-64-NEXT: Content: '' +ELF-X86-64-NEXT: Content: "" ELF-X86-64-NEXT: - Name: .rela.text ELF-X86-64-NEXT: Type: SHT_RELA ELF-X86-64-NEXT: Address: 0x0000000000000038 @@ -382,7 +382,7 @@ ELF-X86-64-NEXT: Info: .text ELF-X86-64-NEXT: Relocations: ELF-X86-64-NEXT: - Offset: 0x000000000000000D -ELF-X86-64-NEXT: Symbol: '' +ELF-X86-64-NEXT: Symbol: "" ELF-X86-64-NEXT: Type: R_X86_64_32S ELF-X86-64-NEXT: - Offset: 0x0000000000000012 ELF-X86-64-NEXT: Symbol: puts @@ -428,7 +428,7 @@ ELF-AVR-NEXT: Flags: [ SHF_WRITE, SHF_ALLOC ] ELF-AVR-NEXT: Address: 0x0000000000800060 ELF-AVR-NEXT: AddressAlign: 0x0000000000000001 -ELF-AVR-NEXT: Content: '' +ELF-AVR-NEXT: Content: "" ELF-AVR-NEXT: Symbols: ELF-AVR-NEXT: Local: ELF-AVR-NEXT: - Type: STT_SECTION @@ -475,7 +475,7 @@ ELF-X86-64-UNWIND-NEXT: Type: SHT_X86_64_UNWIND ELF-X86-64-UNWIND-NEXT: Flags: [ SHF_ALLOC ] ELF-X86-64-UNWIND-NEXT: AddressAlign: 0x0000000000000001 -ELF-X86-64-UNWIND-NEXT: Content: '' +ELF-X86-64-UNWIND-NEXT: Content: "" RUN: not obj2yaml %t.blah 2>&1 | FileCheck --check-prefix=ENOENT %s ENOENT: Error: '{{[Nn]}}o such file or directory' Index: llvm/test/ObjectYAML/MachO/DWARF-BigEndian.yaml =================================================================== --- llvm/test/ObjectYAML/MachO/DWARF-BigEndian.yaml +++ llvm/test/ObjectYAML/MachO/DWARF-BigEndian.yaml @@ -13,7 +13,7 @@ LoadCommands: - cmd: LC_SEGMENT cmdsize: 1144 - segname: '' + segname: "" vmaddr: 0 vmsize: 1122 fileoff: 1292 @@ -258,13 +258,13 @@ n_desc: 0 n_value: 0 StringTable: - - '' + - "" - _compilerrt_abort_impl - ___absvdi2 - - '' + - "" DWARF: debug_str: - - 'clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)' + - "clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)" - ../compiler-rt/lib/builtins/absvdi2.c - /Users/cbieneman/dev/open-source/llvm-build-rel - int @@ -375,7 +375,7 @@ #CHECK: DWARF: #CHECK: debug_str: -#CHECK: - 'clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)' +#CHECK: - "clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)" #CHECK: - ../compiler-rt/lib/builtins/absvdi2.c #CHECK: - /Users/cbieneman/dev/open-source/llvm-build-rel #CHECK: - int Index: llvm/test/ObjectYAML/MachO/DWARF-LittleEndian.yaml =================================================================== --- llvm/test/ObjectYAML/MachO/DWARF-LittleEndian.yaml +++ llvm/test/ObjectYAML/MachO/DWARF-LittleEndian.yaml @@ -14,7 +14,7 @@ LoadCommands: - cmd: LC_SEGMENT_64 cmdsize: 1272 - segname: '' + segname: "" vmaddr: 0 vmsize: 1086 fileoff: 1424 @@ -247,13 +247,13 @@ n_desc: 0 n_value: 0 StringTable: - - '' + - "" - _compilerrt_abort_impl - ___absvdi2 - - '' + - "" DWARF: debug_str: - - 'clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)' + - "clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)" - ../compiler-rt/lib/builtins/absvdi2.c - /Users/cbieneman/dev/open-source/llvm-build-rel - int @@ -364,7 +364,7 @@ #CHECK: DWARF: #CHECK: debug_str: -#CHECK: - 'clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)' +#CHECK: - "clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)" #CHECK: - ../compiler-rt/lib/builtins/absvdi2.c #CHECK: - /Users/cbieneman/dev/open-source/llvm-build-rel #CHECK: - int Index: llvm/test/ObjectYAML/MachO/DWARF-debug_str.yaml =================================================================== --- llvm/test/ObjectYAML/MachO/DWARF-debug_str.yaml +++ llvm/test/ObjectYAML/MachO/DWARF-debug_str.yaml @@ -235,14 +235,14 @@ n_desc: 0 n_value: 4294971296 StringTable: - - '' - - '' + - "" + - "" - __mh_execute_header - _main DWARF: debug_str: - - '' - - 'clang version 4.0.0 (trunk 288677) (llvm/trunk 288676)' + - "" + - "clang version 4.0.0 (trunk 288677) (llvm/trunk 288676)" - hello_world.c - /Users/cbieneman/dev/open-source/llvm-build-rel - main @@ -254,8 +254,8 @@ #CHECK: DWARF: #CHECK: debug_str: -#CHECK: - '' -#CHECK: - 'clang version 4.0.0 (trunk 288677) (llvm/trunk 288676)' +#CHECK: - "" +#CHECK: - "clang version 4.0.0 (trunk 288677) (llvm/trunk 288676)" #CHECK: - hello_world.c #CHECK: - /Users/cbieneman/dev/open-source/llvm-build-rel #CHECK: - main Index: llvm/test/ObjectYAML/MachO/dylib_dylinker_command.yaml =================================================================== --- llvm/test/ObjectYAML/MachO/dylib_dylinker_command.yaml +++ llvm/test/ObjectYAML/MachO/dylib_dylinker_command.yaml @@ -23,7 +23,7 @@ timestamp: 2 current_version: 7864576 compatibility_version: 65536 - PayloadString: '/usr/lib/libc++.1.dylib' + PayloadString: "/usr/lib/libc++.1.dylib" ZeroPadBytes: 1 - cmd: LC_LOAD_DYLIB cmdsize: 56 @@ -49,7 +49,7 @@ #CHECK: timestamp: 2 #CHECK: current_version: 7864576 #CHECK: compatibility_version: 65536 -#CHECK: PayloadString: '/usr/lib/libc++.1.dylib' +#CHECK: PayloadString: "/usr/lib/libc++.1.dylib" #CHECK: ZeroPadBytes: 1 #CHECK: - cmd: LC_LOAD_DYLIB #CHECK: cmdsize: 56 Index: llvm/test/ObjectYAML/MachO/export_trie.yaml =================================================================== --- llvm/test/ObjectYAML/MachO/export_trie.yaml +++ llvm/test/ObjectYAML/MachO/export_trie.yaml @@ -119,7 +119,7 @@ timestamp: 2 current_version: 7864576 compatibility_version: 65536 - PayloadString: '/usr/lib/libc++.1.dylib' + PayloadString: "/usr/lib/libc++.1.dylib" ZeroPadBytes: 1 - cmd: LC_LOAD_DYLIB cmdsize: 56 @@ -142,11 +142,11 @@ ExportTrie: TerminalSize: 0 NodeOffset: 0 - Name: '' + Name: "" Flags: 0x0000000000000000 Address: 0x0000000000000000 Other: 0x0000000000000000 - ImportName: '' + ImportName: "" Children: - TerminalSize: 0 NodeOffset: 5 @@ -154,7 +154,7 @@ Flags: 0x0000000000000000 Address: 0x0000000000000000 Other: 0x0000000000000000 - ImportName: '' + ImportName: "" Children: - TerminalSize: 2 NodeOffset: 33 @@ -162,20 +162,20 @@ Flags: 0x0000000000000000 Address: 0x0000000000000000 Other: 0x0000000000000000 - ImportName: '' + ImportName: "" - TerminalSize: 3 NodeOffset: 37 Name: main Flags: 0x0000000000000000 Address: 0x0000000000001160 Other: 0x0000000000000000 - ImportName: '' + ImportName: "" ... #CHECK: ExportTrie: #CHECK: TerminalSize: 0 #CHECK: NodeOffset: 0 -#CHECK: Name: '' +#CHECK: Name: "" #CHECK: Children: #CHECK: - TerminalSize: 0 #CHECK: NodeOffset: 5 Index: llvm/test/ObjectYAML/MachO/null_string_entries.yaml =================================================================== --- llvm/test/ObjectYAML/MachO/null_string_entries.yaml +++ llvm/test/ObjectYAML/MachO/null_string_entries.yaml @@ -118,7 +118,7 @@ timestamp: 2 current_version: 7864576 compatibility_version: 65536 - PayloadString: '/usr/lib/libc++.1.dylib' + PayloadString: "/usr/lib/libc++.1.dylib" ZeroPadBytes: 1 - cmd: LC_LOAD_DYLIB cmdsize: 52 @@ -139,10 +139,10 @@ datasize: 0 LinkEditData: StringTable: - - '' - - '' - - '' - - '' + - "" + - "" + - "" + - "" - __mh_execute_header - __Unwind_Resume - __ZNKSt3__16locale9use_facetERNS0_2idE @@ -167,17 +167,17 @@ - _strlen - _strnlen - dyld_stub_binder - - 'radr://5614542' - - '' - - '' - - '' + - "radr://5614542" + - "" + - "" + - "" ... #CHECK: StringTable: -#CHECK: - '' -#CHECK: - '' -#CHECK: - '' -#CHECK: - '' +#CHECK: - "" +#CHECK: - "" +#CHECK: - "" +#CHECK: - "" #CHECK: - __mh_execute_header #CHECK: - __Unwind_Resume #CHECK: - __ZNKSt3__16locale9use_facetERNS0_2idE @@ -202,7 +202,7 @@ #CHECK: - _strlen #CHECK: - _strnlen #CHECK: - dyld_stub_binder -#CHECK: - 'radr://5614542' -#CHECK: - '' -#CHECK: - '' -#CHECK: - '' +#CHECK: - "radr://5614542" +#CHECK: - "" +#CHECK: - "" +#CHECK: - "" Index: llvm/test/ObjectYAML/MachO/out_of_order_linkedit.yaml =================================================================== --- llvm/test/ObjectYAML/MachO/out_of_order_linkedit.yaml +++ llvm/test/ObjectYAML/MachO/out_of_order_linkedit.yaml @@ -119,7 +119,7 @@ timestamp: 2 current_version: 7864576 compatibility_version: 65536 - PayloadString: '/usr/lib/libc++.1.dylib' + PayloadString: "/usr/lib/libc++.1.dylib" ZeroPadBytes: 1 - cmd: LC_LOAD_DYLIB cmdsize: 56 @@ -155,45 +155,45 @@ BindOpcodes: - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM Imm: 1 - Symbol: '' + Symbol: "" - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM Imm: 0 Symbol: __ZNSt3__14coutE - Opcode: BIND_OPCODE_SET_TYPE_IMM Imm: 1 - Symbol: '' + Symbol: "" - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB Imm: 2 ULEBExtraData: - 0x0000000000000000 - Symbol: '' + Symbol: "" - Opcode: BIND_OPCODE_DO_BIND Imm: 0 - Symbol: '' + Symbol: "" - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM Imm: 0 Symbol: __ZNSt3__15ctypeIcE2idE - Opcode: BIND_OPCODE_DO_BIND Imm: 0 - Symbol: '' + Symbol: "" - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM Imm: 0 Symbol: ___gxx_personality_v0 - Opcode: BIND_OPCODE_DO_BIND Imm: 0 - Symbol: '' + Symbol: "" - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM Imm: 2 - Symbol: '' + Symbol: "" - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM Imm: 0 Symbol: dyld_stub_binder - Opcode: BIND_OPCODE_DO_BIND Imm: 0 - Symbol: '' + Symbol: "" - Opcode: BIND_OPCODE_DONE Imm: 0 - Symbol: '' + Symbol: "" ... #CHECK: - cmd: LC_DYLD_INFO_ONLY @@ -225,42 +225,42 @@ #CHECK: BindOpcodes: #CHECK: - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM #CHECK: Imm: 1 -#CHECK: Symbol: '' +#CHECK: Symbol: "" #CHECK: - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM #CHECK: Imm: 0 #CHECK: Symbol: __ZNSt3__14coutE #CHECK: - Opcode: BIND_OPCODE_SET_TYPE_IMM #CHECK: Imm: 1 -#CHECK: Symbol: '' +#CHECK: Symbol: "" #CHECK: - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB #CHECK: Imm: 2 #CHECK: ULEBExtraData: #CHECK: - 0x0000000000000000 -#CHECK: Symbol: '' +#CHECK: Symbol: "" #CHECK: - Opcode: BIND_OPCODE_DO_BIND #CHECK: Imm: 0 -#CHECK: Symbol: '' +#CHECK: Symbol: "" #CHECK: - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM #CHECK: Imm: 0 #CHECK: Symbol: __ZNSt3__15ctypeIcE2idE #CHECK: - Opcode: BIND_OPCODE_DO_BIND #CHECK: Imm: 0 -#CHECK: Symbol: '' +#CHECK: Symbol: "" #CHECK: - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM #CHECK: Imm: 0 #CHECK: Symbol: ___gxx_personality_v0 #CHECK: - Opcode: BIND_OPCODE_DO_BIND #CHECK: Imm: 0 -#CHECK: Symbol: '' +#CHECK: Symbol: "" #CHECK: - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM #CHECK: Imm: 2 -#CHECK: Symbol: '' +#CHECK: Symbol: "" #CHECK: - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM #CHECK: Imm: 0 #CHECK: Symbol: dyld_stub_binder #CHECK: - Opcode: BIND_OPCODE_DO_BIND #CHECK: Imm: 0 -#CHECK: Symbol: '' +#CHECK: Symbol: "" #CHECK: - Opcode: BIND_OPCODE_DONE #CHECK: Imm: 0 -#CHECK: Symbol: '' +#CHECK: Symbol: "" Index: llvm/test/ObjectYAML/MachO/symtab.yaml =================================================================== --- llvm/test/ObjectYAML/MachO/symtab.yaml +++ llvm/test/ObjectYAML/MachO/symtab.yaml @@ -121,7 +121,7 @@ timestamp: 2 current_version: 7864576 compatibility_version: 65536 - PayloadString: '/usr/lib/libc++.1.dylib' + PayloadString: "/usr/lib/libc++.1.dylib" ZeroPadBytes: 1 - cmd: LC_LOAD_DYLIB cmdsize: 56 @@ -293,7 +293,7 @@ n_desc: 512 n_value: 0 StringTable: - - ' ' + - " " - __ZNSt3__1lsINS_11char_traitsIcEEEERNS_13basic_ostreamIcT_EES6_PKc - __ZNSt3__124__put_character_sequenceIcNS_11char_traitsIcEEEERNS_13basic_ostreamIT_T0_EES7_PKS4_m - __ZNSt3__111char_traitsIcE6lengthEPKc @@ -478,7 +478,7 @@ #CHECK: n_desc: 512 #CHECK: n_value: 0 #CHECK: StringTable: -#CHECK: - ' ' +#CHECK: - " " #CHECK: - __ZNSt3__1lsINS_11char_traitsIcEEEERNS_13basic_ostreamIcT_EES6_PKc #CHECK: - __ZNSt3__124__put_character_sequenceIcNS_11char_traitsIcEEEERNS_13basic_ostreamIT_T0_EES7_PKS4_m #CHECK: - __ZNSt3__111char_traitsIcE6lengthEPKc Index: llvm/test/ObjectYAML/wasm/data_section.yaml =================================================================== --- llvm/test/ObjectYAML/wasm/data_section.yaml +++ llvm/test/ObjectYAML/wasm/data_section.yaml @@ -12,7 +12,7 @@ Offset: Opcode: I32_CONST Value: 4 - Content: '10001000' + Content: "10001000" Relocations: - Type: R_WEBASSEMBLY_GLOBAL_ADDR_I32 Index: 0 @@ -42,5 +42,5 @@ # CHECK-NEXT: Offset: # CHECK-NEXT: Opcode: I32_CONST # CHECK-NEXT: Value: 4 -# CHECK-NEXT: Content: '10001000' +# CHECK-NEXT: Content: "10001000" # CHECK-NEXT: ... Index: llvm/test/ThinLTO/X86/diagnostic-handler-remarks-with-hotness.ll =================================================================== --- llvm/test/ThinLTO/X86/diagnostic-handler-remarks-with-hotness.ll +++ llvm/test/ThinLTO/X86/diagnostic-handler-remarks-with-hotness.ll @@ -23,7 +23,7 @@ ; YAML1-NEXT: Hotness: 50 ; YAML1-NEXT: Args: ; YAML1-NEXT: - Callee: foo -; YAML1-NEXT: - String: ' inlined into ' +; YAML1-NEXT: - String: " inlined into " ; YAML1-NEXT: - Caller: main ; YAML1-NEXT: ... @@ -36,7 +36,7 @@ ; YAML2-NEXT: Function: foo ; YAML2-NEXT: Args: ; YAML2-NEXT: - Callee: bar -; YAML2-NEXT: - String: ' inlined into ' +; YAML2-NEXT: - String: " inlined into " ; YAML2-NEXT: - Caller: foo ; YAML2-NEXT: ... Index: llvm/test/ThinLTO/X86/diagnostic-handler-remarks.ll =================================================================== --- llvm/test/ThinLTO/X86/diagnostic-handler-remarks.ll +++ llvm/test/ThinLTO/X86/diagnostic-handler-remarks.ll @@ -20,7 +20,7 @@ ; YAML1-NEXT: Function: main ; YAML1-NEXT: Args: ; YAML1-NEXT: - Callee: foo -; YAML1-NEXT: - String: ' inlined into ' +; YAML1-NEXT: - String: " inlined into " ; YAML1-NEXT: - Caller: main ; YAML1-NEXT: ... @@ -33,7 +33,7 @@ ; YAML2-NEXT: Function: foo ; YAML2-NEXT: Args: ; YAML2-NEXT: - Callee: bar -; YAML2-NEXT: - String: ' inlined into ' +; YAML2-NEXT: - String: " inlined into " ; YAML2-NEXT: - Caller: foo ; YAML2-NEXT: ... Index: llvm/test/Transforms/GVN/opt-remarks.ll =================================================================== --- llvm/test/Transforms/GVN/opt-remarks.ll +++ llvm/test/Transforms/GVN/opt-remarks.ll @@ -12,10 +12,10 @@ ; YAML-NEXT: Name: LoadElim ; YAML-NEXT: Function: arg ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'load of type ' +; YAML-NEXT: - String: "load of type " ; YAML-NEXT: - Type: i32 -; YAML-NEXT: - String: ' eliminated' -; YAML-NEXT: - String: ' in favor of ' +; YAML-NEXT: - String: " eliminated" +; YAML-NEXT: - String: " in favor of " ; YAML-NEXT: - InfavorOfValue: i ; YAML-NEXT: ... ; YAML-NEXT: --- !Passed @@ -23,21 +23,21 @@ ; YAML-NEXT: Name: LoadElim ; YAML-NEXT: Function: const ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'load of type ' +; YAML-NEXT: - String: "load of type " ; YAML-NEXT: - Type: i32 -; YAML-NEXT: - String: ' eliminated' -; YAML-NEXT: - String: ' in favor of ' -; YAML-NEXT: - InfavorOfValue: '4' +; YAML-NEXT: - String: " eliminated" +; YAML-NEXT: - String: " in favor of " +; YAML-NEXT: - InfavorOfValue: "4" ; YAML-NEXT: ... ; YAML-NEXT: --- !Passed ; YAML-NEXT: Pass: gvn ; YAML-NEXT: Name: LoadElim ; YAML-NEXT: Function: inst ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'load of type ' +; YAML-NEXT: - String: "load of type " ; YAML-NEXT: - Type: i32 -; YAML-NEXT: - String: ' eliminated' -; YAML-NEXT: - String: ' in favor of ' +; YAML-NEXT: - String: " eliminated" +; YAML-NEXT: - String: " in favor of " ; YAML-NEXT: - InfavorOfValue: load ; YAML-NEXT: ... ; YAML-NEXT: --- !Missed @@ -46,13 +46,13 @@ ; YAML-NEXT: DebugLoc: { File: /tmp/s.c, Line: 3, Column: 3 } ; YAML-NEXT: Function: may_alias ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'load of type ' +; YAML-NEXT: - String: "load of type " ; YAML-NEXT: - Type: i32 -; YAML-NEXT: - String: ' not eliminated' -; YAML-NEXT: - String: ' in favor of ' +; YAML-NEXT: - String: " not eliminated" +; YAML-NEXT: - String: " in favor of " ; YAML-NEXT: - OtherAccess: load ; YAML-NEXT: DebugLoc: { File: /tmp/s.c, Line: 1, Column: 13 } -; YAML-NEXT: - String: ' because it is clobbered by ' +; YAML-NEXT: - String: " because it is clobbered by " ; YAML-NEXT: - ClobberedBy: store ; YAML-NEXT: DebugLoc: { File: /tmp/s.c, Line: 2, Column: 10 } ; YAML-NEXT: ... Index: llvm/test/Transforms/Inline/optimization-remarks-passed-yaml.ll =================================================================== --- llvm/test/Transforms/Inline/optimization-remarks-passed-yaml.ll +++ llvm/test/Transforms/Inline/optimization-remarks-passed-yaml.ll @@ -24,14 +24,14 @@ ; YAML-NEXT: Args: ; YAML-NEXT: - Callee: foo ; YAML-NEXT: DebugLoc: { File: /tmp/s.c, Line: 1, Column: 0 } -; YAML-NEXT: - String: ' can be inlined into ' +; YAML-NEXT: - String: " can be inlined into " ; YAML-NEXT: - Caller: bar ; YAML-NEXT: DebugLoc: { File: /tmp/s.c, Line: 3, Column: 0 } -; YAML-NEXT: - String: ' with cost=' -; YAML-NEXT: - Cost: '{{[0-9\-]+}}' -; YAML-NEXT: - String: ' (threshold=' -; YAML-NEXT: - Threshold: '{{[0-9]+}}' -; YAML-NEXT: - String: ')' +; YAML-NEXT: - String: " with cost=" +; YAML-NEXT: - Cost: "{{[0-9\-]+}}" +; YAML-NEXT: - String: " (threshold=" +; YAML-NEXT: - Threshold: "{{[0-9]+}}" +; YAML-NEXT: - String: ")" ; YAML-NEXT: ... ; YAML-NEXT: --- !Passed ; YAML-NEXT: Pass: inline @@ -42,12 +42,12 @@ ; YAML-NEXT: Args: ; YAML-NEXT: - Callee: foo ; YAML-NEXT: DebugLoc: { File: /tmp/s.c, Line: 1, Column: 0 } -; YAML-NEXT: - String: ' inlined into ' +; YAML-NEXT: - String: " inlined into " ; YAML-NEXT: - Caller: bar ; YAML-NEXT: DebugLoc: { File: /tmp/s.c, Line: 3, Column: 0 } ; YAML-NEXT: ... -; ModuleID = '/tmp/s.c' +; ModuleID = "/tmp/s.c" source_filename = "/tmp/s.c" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.11.0" Index: llvm/test/Transforms/Inline/optimization-remarks-yaml.ll =================================================================== --- llvm/test/Transforms/Inline/optimization-remarks-yaml.ll +++ llvm/test/Transforms/Inline/optimization-remarks-yaml.ll @@ -24,10 +24,10 @@ ; YAML-NEXT: Hotness: 30 ; YAML-NEXT: Args: ; YAML-NEXT: - Callee: foo -; YAML-NEXT: - String: ' will not be inlined into ' +; YAML-NEXT: - String: " will not be inlined into " ; YAML-NEXT: - Caller: baz ; YAML-NEXT: DebugLoc: { File: /tmp/s.c, Line: 4, Column: 0 } -; YAML-NEXT: - String: ' because its definition is unavailable' +; YAML-NEXT: - String: " because its definition is unavailable" ; YAML-NEXT: ... ; YAML-NEXT: --- !Missed ; YAML-NEXT: Pass: inline @@ -37,13 +37,13 @@ ; YAML-NEXT: Hotness: 30 ; YAML-NEXT: Args: ; YAML-NEXT: - Callee: bar -; YAML-NEXT: - String: ' will not be inlined into ' +; YAML-NEXT: - String: " will not be inlined into " ; YAML-NEXT: - Caller: baz ; YAML-NEXT: DebugLoc: { File: /tmp/s.c, Line: 4, Column: 0 } -; YAML-NEXT: - String: ' because its definition is unavailable' +; YAML-NEXT: - String: " because its definition is unavailable" ; YAML-NEXT: ... -; ModuleID = '/tmp/s.c' +; ModuleID = "/tmp/s.c" source_filename = "/tmp/s.c" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.11.0" Index: llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll =================================================================== --- llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll +++ llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -loop-vectorize -S -pass-remarks-missed='loop-vectorize' -pass-remarks-analysis='loop-vectorize' 2>&1 | FileCheck %s +; RUN: opt < %s -loop-vectorize -S -pass-remarks-missed="loop-vectorize" -pass-remarks-analysis="loop-vectorize" 2>&1 | FileCheck %s ; RUN: opt < %s -loop-vectorize -o /dev/null -pass-remarks-output=%t.yaml ; RUN: cat %t.yaml | FileCheck -check-prefix=YAML %s @@ -50,7 +50,7 @@ ; YAML-NEXT: DebugLoc: { File: source.cpp, Line: 4, Column: 5 } ; YAML-NEXT: Function: _Z4testPii ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'loop not vectorized: ' +; YAML-NEXT: - String: "loop not vectorized: " ; YAML-NEXT: - String: could not determine number of loop iterations ; YAML-NEXT: ... ; YAML-NEXT: --- !Missed @@ -67,15 +67,15 @@ ; YAML-NEXT: DebugLoc: { File: source.cpp, Line: 13, Column: 5 } ; YAML-NEXT: Function: _Z13test_disabledPii ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'loop not vectorized: vectorization and interleaving are explicitly disabled, or vectorize width and interleave count are both set to 1' +; YAML-NEXT: - String: "loop not vectorized: vectorization and interleaving are explicitly disabled, or vectorize width and interleave count are both set to 1" ; YAML-NEXT: ... ; YAML-NEXT: --- !Analysis -; YAML-NEXT: Pass: '' +; YAML-NEXT: Pass: "" ; YAML-NEXT: Name: CantIdentifyArrayBounds ; YAML-NEXT: DebugLoc: { File: source.cpp, Line: 19, Column: 5 } ; YAML-NEXT: Function: _Z17test_array_boundsPiS_i ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'loop not vectorized: ' +; YAML-NEXT: - String: "loop not vectorized: " ; YAML-NEXT: - String: cannot identify array bounds ; YAML-NEXT: ... ; YAML-NEXT: --- !Missed @@ -85,9 +85,9 @@ ; YAML-NEXT: Function: _Z17test_array_boundsPiS_i ; YAML-NEXT: Args: ; YAML-NEXT: - String: loop not vectorized -; YAML-NEXT: - String: ' (Force=' -; YAML-NEXT: - Force: 'true' -; YAML-NEXT: - String: ')' +; YAML-NEXT: - String: " (Force=" +; YAML-NEXT: - Force: "true" +; YAML-NEXT: - String: ")" ; YAML-NEXT: ... ; YAML-NEXT: --- !Failure ; YAML-NEXT: Pass: loop-vectorize @@ -95,7 +95,7 @@ ; YAML-NEXT: DebugLoc: { File: source.cpp, Line: 19, Column: 5 } ; YAML-NEXT: Function: _Z17test_array_boundsPiS_i ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'loop not vectorized: ' +; YAML-NEXT: - String: "loop not vectorized: " ; YAML-NEXT: - String: failed explicitly specified loop vectorization ; YAML-NEXT: ... ; YAML-NEXT: --- !Analysis @@ -104,7 +104,7 @@ ; YAML-NEXT: DebugLoc: { File: source.cpp, Line: 29, Column: 7 } ; YAML-NEXT: Function: test_multiple_failures ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'loop not vectorized: ' +; YAML-NEXT: - String: "loop not vectorized: " ; YAML-NEXT: - String: control flow cannot be substituted for a select ; YAML-NEXT: ... ; YAML-NEXT: --- !Analysis @@ -113,7 +113,7 @@ ; YAML-NEXT: DebugLoc: { File: source.cpp, Line: 27, Column: 3 } ; YAML-NEXT: Function: test_multiple_failures ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'loop not vectorized: ' +; YAML-NEXT: - String: "loop not vectorized: " ; YAML-NEXT: - String: value that could not be identified as reduction is used outside the loop ; YAML-NEXT: ... ; YAML-NEXT: --- !Analysis @@ -122,7 +122,7 @@ ; YAML-NEXT: DebugLoc: { File: source.cpp, Line: 27, Column: 3 } ; YAML-NEXT: Function: test_multiple_failures ; YAML-NEXT: Args: -; YAML-NEXT: - String: 'loop not vectorized: ' +; YAML-NEXT: - String: "loop not vectorized: " ; YAML-NEXT: - String: could not determine number of loop iterations ; YAML-NEXT: ... ; YAML-NEXT: --- !Missed Index: llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll =================================================================== --- llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll +++ llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll @@ -36,7 +36,7 @@ ; SUMMARY-NEXT: WPDRes: ; SUMMARY-NEXT: 0: ; SUMMARY-NEXT: Kind: SingleImpl -; SUMMARY-NEXT: SingleImplName: 'vf4$merged' +; SUMMARY-NEXT: SingleImplName: "vf4$merged" ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: WithGlobalValueDeadStripping: false ; SUMMARY-NEXT: ... Index: llvm/test/Transforms/WholeProgramDevirt/export-uniform-ret-val.ll =================================================================== --- llvm/test/Transforms/WholeProgramDevirt/export-uniform-ret-val.ll +++ llvm/test/Transforms/WholeProgramDevirt/export-uniform-ret-val.ll @@ -11,7 +11,7 @@ ; SUMMARY-NEXT: WPDRes: ; SUMMARY-NEXT: 0: ; SUMMARY-NEXT: Kind: Indir -; SUMMARY-NEXT: SingleImplName: '' +; SUMMARY-NEXT: SingleImplName: "" ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: 24,12: ; SUMMARY-NEXT: Kind: UniformRetVal Index: llvm/test/Transforms/WholeProgramDevirt/export-unique-ret-val.ll =================================================================== --- llvm/test/Transforms/WholeProgramDevirt/export-unique-ret-val.ll +++ llvm/test/Transforms/WholeProgramDevirt/export-unique-ret-val.ll @@ -11,7 +11,7 @@ ; SUMMARY-NEXT: WPDRes: ; SUMMARY-NEXT: 0: ; SUMMARY-NEXT: Kind: Indir -; SUMMARY-NEXT: SingleImplName: '' +; SUMMARY-NEXT: SingleImplName: "" ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: 12,24: ; SUMMARY-NEXT: Kind: UniqueRetVal @@ -23,7 +23,7 @@ ; SUMMARY-NEXT: WPDRes: ; SUMMARY-NEXT: 0: ; SUMMARY-NEXT: Kind: Indir -; SUMMARY-NEXT: SingleImplName: '' +; SUMMARY-NEXT: SingleImplName: "" ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: 24,12: ; SUMMARY-NEXT: Kind: UniqueRetVal Index: llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll =================================================================== --- llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll +++ llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll @@ -12,7 +12,7 @@ ; SUMMARY-NEXT: WPDRes: ; SUMMARY-NEXT: 0: ; SUMMARY-NEXT: Kind: Indir -; SUMMARY-NEXT: SingleImplName: '' +; SUMMARY-NEXT: SingleImplName: "" ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: 12,24: ; SUMMARY-NEXT: Kind: VirtualConstProp @@ -24,7 +24,7 @@ ; SUMMARY-NEXT: WPDRes: ; SUMMARY-NEXT: 0: ; SUMMARY-NEXT: Kind: Indir -; SUMMARY-NEXT: SingleImplName: '' +; SUMMARY-NEXT: SingleImplName: "" ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: 24,12: ; SUMMARY-NEXT: Kind: VirtualConstProp Index: llvm/test/Transforms/WholeProgramDevirt/import-indir.ll =================================================================== --- llvm/test/Transforms/WholeProgramDevirt/import-indir.ll +++ llvm/test/Transforms/WholeProgramDevirt/import-indir.ll @@ -35,11 +35,11 @@ ; SUMMARY-NEXT: WPDRes: ; SUMMARY-NEXT: 0: ; SUMMARY-NEXT: Kind: Indir -; SUMMARY-NEXT: SingleImplName: '' +; SUMMARY-NEXT: SingleImplName: "" ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: 4: ; SUMMARY-NEXT: Kind: Indir -; SUMMARY-NEXT: SingleImplName: '' +; SUMMARY-NEXT: SingleImplName: "" ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: : ; SUMMARY-NEXT: Kind: UniformRetVal Index: llvm/test/tools/dsymutil/arch-option.test =================================================================== --- llvm/test/tools/dsymutil/arch-option.test +++ llvm/test/tools/dsymutil/arch-option.test @@ -3,7 +3,7 @@ RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib | FileCheck %s -check-prefix=ARM64 -check-prefix=ARMV7S -check-prefix=ARMV7 -check-prefix=CHECK RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch all | FileCheck %s -check-prefix=ARM64 -check-prefix=ARMV7S -check-prefix=ARMV7 -check-prefix=CHECK -RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch='*' | FileCheck %s -check-prefix=ARM64 -check-prefix=ARMV7S -check-prefix=ARMV7 -check-prefix=CHECK +RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch="*" | FileCheck %s -check-prefix=ARM64 -check-prefix=ARMV7S -check-prefix=ARMV7 -check-prefix=CHECK RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch arm64 | FileCheck %s -check-prefix=ARM64 -check-prefix=CHECK RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch arm | FileCheck %s -check-prefix=ARMV7S -check-prefix=ARMV7 -check-prefix=CHECK RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch armv7 | FileCheck %s -check-prefix=ARMV7 -check-prefix=CHECK @@ -14,21 +14,21 @@ ARMV7: --- ARMV7-NOT: ... -ARMV7: triple: 'armv7-apple-darwin' +ARMV7: triple: "armv7-apple-darwin" ARMV7-NOT: ... ARMV7: sym: _armv7_var ARMV7-NOT: --- ARMV7S: --- ARMV7S-NOT: ... -ARMV7S: triple: 'armv7s-apple-darwin' +ARMV7S: triple: "armv7s-apple-darwin" ARMV7S-NOT: ... ARMV7S: sym: _armv7s_var ARMV7S-NOT: --- ARM64: --- ARM64-NOT: ... -ARM64: triple: 'arm64-apple-darwin' +ARM64: triple: "arm64-apple-darwin" ARM64-NOT: ... ARM64: sym: _arm64_var ARM64-NOT: --- Index: llvm/test/tools/dsymutil/debug-map-parsing.test =================================================================== --- llvm/test/tools/dsymutil/debug-map-parsing.test +++ llvm/test/tools/dsymutil/debug-map-parsing.test @@ -9,7 +9,7 @@ CHECK-NOT: error CHECK: --- -CHECK: triple: 'x86_64-apple-darwin' +CHECK: triple: "x86_64-apple-darwin" CHECK: binary-path:{{.*}}/Inputs/basic.macho.x86_64 CHECK: filename:{{.*}}/Inputs/basic1.macho.x86_64.o CHECK-DAG: sym: _main, objAddr: 0x0000000000000000, binAddr: 0x0000000100000EA0, size: 0x00000024 @@ -29,7 +29,7 @@ CHECK-LTO-NOT: error CHECK-LTO: --- -CHECK-LTO: triple: 'x86_64-apple-darwin' +CHECK-LTO: triple: "x86_64-apple-darwin" CHECK-LTO: binary-path:{{.*}}/Inputs/basic-lto.macho.x86_64 CHECK-LTO: /Inputs/basic-lto.macho.x86_64.o CHECK-LTO-DAG: sym: _bar, objAddr: 0x0000000000000050, binAddr: 0x0000000100000F90, size: 0x00000024 @@ -53,7 +53,7 @@ CHECK-ARCHIVE-NEXT: trying to open {{.*}}/libbasic.a(basic3.macho.x86_64.o)' CHECK-ARCHIVE-NEXT: found member in current archive. CHECK-ARCHIVE: --- -CHECK-ARCHIVE: triple: 'x86_64-apple-darwin' +CHECK-ARCHIVE: triple: "x86_64-apple-darwin" CHECK-ARCHIVE: binary-path:{{.*}}/Inputs/basic-archive.macho.x86_64 CHECK-ARCHIVE: /Inputs/basic1.macho.x86_64.o CHECK-ARCHIVE-DAG: sym: _main, objAddr: 0x0000000000000000, binAddr: 0x0000000100000EA0, size: 0x00000024 @@ -75,7 +75,7 @@ NOT-FOUND: cannot open{{.*}}"/Inputs/basic2.macho.x86_64.o": {{[Nn]o}} such file NOT-FOUND: cannot open{{.*}}"/Inputs/basic3.macho.x86_64.o": {{[Nn]o}} such file NOT-FOUND: --- -NOT-FOUND-NEXT: triple: 'x86_64-apple-darwin' +NOT-FOUND-NEXT: triple: "x86_64-apple-darwin" NOT-FOUND-NEXT: binary-path:{{.*}}/Inputs/basic.macho.x86_64 NOT-FOUND-NEXT: ... Index: llvm/test/tools/dsymutil/fat-binary-output.test =================================================================== --- llvm/test/tools/dsymutil/fat-binary-output.test +++ llvm/test/tools/dsymutil/fat-binary-output.test @@ -1,6 +1,6 @@ RUN: llvm-dsymutil -f -verbose -no-output %p/Inputs/fat-test.dylib -oso-prepend-path %p | FileCheck %s -This test doesn't produce any filesytstem output, we just look at the verbose +This test doesn"t produce any filesytstem output, we just look at the verbose log output. For each arch in the binary, check that we emit the right triple with the right @@ -10,16 +10,16 @@ After the link of each architecture, check that lipo is correctly invoked to generate the fat output binary. -CHECK: triple: 'x86_64-apple-darwin' -CHECK: - filename: {{'?}}[[INPUTS_PATH:.*]]fat-test.o +CHECK: triple: "x86_64-apple-darwin" +CHECK: - filename: {{"?}}[[INPUTS_PATH:.*]]fat-test.o CHECK: DW_AT_name{{.*}} "x86_64_var" -CHECK: triple: 'i386-apple-darwin' -CHECK: - filename: {{'?}}[[INPUTS_PATH]]fat-test.o +CHECK: triple: "i386-apple-darwin" +CHECK: - filename: {{"?}}[[INPUTS_PATH]]fat-test.o CHECK: DW_AT_name{{.*}} "i386_var" -CHECK: triple: 'x86_64h-apple-darwin' -CHECK: - filename: {{'?}}[[INPUTS_PATH]]fat-test.o +CHECK: triple: "x86_64h-apple-darwin" +CHECK: - filename: {{"?}}[[INPUTS_PATH]]fat-test.o CHECK: DW_AT_name{{.*}} "x86_64h_var" CHECK: Running lipo Index: llvm/test/tools/dsymutil/yaml-object-address-rewrite.test =================================================================== --- llvm/test/tools/dsymutil/yaml-object-address-rewrite.test +++ llvm/test/tools/dsymutil/yaml-object-address-rewrite.test @@ -5,14 +5,14 @@ # rewrite these addresses to the right values. # # CHECK: --- -# CHECK-NEXT: triple:{{.*}}'x86_64-apple-darwin' -# CHECK-NEXT: binary-path:{{.*}}'' +# CHECK-NEXT: triple:{{.*}}"x86_64-apple-darwin" +# CHECK-NEXT: binary-path:{{.*}}"" # CHECK-NEXT: objects: # CHECK-NEXT: filename:{{.*}}/Inputs/basic1.macho.x86_64.o # CHECK-NEXT: timestamp: 0 # CHECK-NEXT: symbols: # CHECK-NEXT: sym: _main, objAddr: 0x0000000000000000, binAddr: 0x0000000100000EA0, size: 0x00000024 -# CHECK-NEXT: filename:{{.*}}/Inputs/./libbasic.a(basic2.macho.x86_64.o)' +# CHECK-NEXT: filename:{{.*}}/Inputs/./libbasic.a(basic2.macho.x86_64.o)" # CHECK-NEXT: timestamp: 0 # CHECK-NEXT: symbols: # CHECK-DAG: sym: _foo, objAddr: 0x0000000000000020, binAddr: 0x0000000100000ED0, size: 0x00000050 @@ -20,7 +20,7 @@ # CHECK-DAG: sym: _inc, objAddr: 0x0000000000000070, binAddr: 0x0000000100000F20, size: 0x00000017 # CHECK-DAG: sym: _baz, objAddr: 0x0000000000000310, binAddr: 0x0000000100001000, size: 0x00000000 # CHECK-NOT: { sym: -# CHECK-NEXT: filename:{{.*}}/Inputs/./libbasic.a(basic3.macho.x86_64.o)' +# CHECK-NEXT: filename:{{.*}}/Inputs/./libbasic.a(basic3.macho.x86_64.o)" # CHECK-NEXT: timestamp: 0 # CHECK-NEXT: symbols: # CHECK-DAG: sym: _val, binAddr: 0x0000000100001008, size: 0x00000000 @@ -29,7 +29,7 @@ # CHECK-NOT: { sym: # CHECK-NEXT: ... --- -triple: 'x86_64-apple-darwin' +triple: "x86_64-apple-darwin" objects: - filename: /Inputs/basic1.macho.x86_64.o symbols: Index: llvm/test/tools/llvm-xray/X86/convert-fdr-to-yaml.txt =================================================================== --- llvm/test/tools/llvm-xray/X86/convert-fdr-to-yaml.txt +++ llvm/test/tools/llvm-xray/X86/convert-fdr-to-yaml.txt @@ -8,17 +8,17 @@ ; CHECK-NEXT: nonstop-tsc: true ; CHECK-NEXT: cycle-frequency: 5678 ; CHECK-NEXT: records: -; CHECK-NEXT: - { type: 0, func-id: 1, function: '1', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407340 } -; CHECK-NEXT: - { type: 0, func-id: 1, function: '1', cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407346 } -; CHECK-NEXT: - { type: 0, func-id: 2, function: '2', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407347 } -; CHECK-NEXT: - { type: 0, func-id: 3, function: '3', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407387 } -; CHECK-NEXT: - { type: 0, func-id: 3, function: '3', cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407437 } -; CHECK-NEXT: - { type: 0, func-id: 2, function: '2', cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407467 } -; CHECK-NEXT: - { type: 0, func-id: 4, function: '4', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407492 } -; CHECK-NEXT: - { type: 0, func-id: 5, function: '5', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407517 } -; CHECK-NEXT: - { type: 0, func-id: 5, function: '5', cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407542 } -; CHECK-NEXT: - { type: 0, func-id: 268435455, function: '268435455', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407552 } -; CHECK-NEXT: - { type: 0, func-id: 268435455, function: '268435455', cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407562 } -; CHECK-NEXT: - { type: 0, func-id: 6, function: '6', cpu: 6, thread: 5, kind: function-enter, tsc: 7238225556407682 } -; CHECK-NEXT: - { type: 0, func-id: 6, function: '6', cpu: 6, thread: 5, kind: function-exit, tsc: 7238225556407755 } +; CHECK-NEXT: - { type: 0, func-id: 1, function: "1", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407340 } +; CHECK-NEXT: - { type: 0, func-id: 1, function: "1", cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407346 } +; CHECK-NEXT: - { type: 0, func-id: 2, function: "2", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407347 } +; CHECK-NEXT: - { type: 0, func-id: 3, function: "3", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407387 } +; CHECK-NEXT: - { type: 0, func-id: 3, function: "3", cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407437 } +; CHECK-NEXT: - { type: 0, func-id: 2, function: "2", cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407467 } +; CHECK-NEXT: - { type: 0, func-id: 4, function: "4", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407492 } +; CHECK-NEXT: - { type: 0, func-id: 5, function: "5", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407517 } +; CHECK-NEXT: - { type: 0, func-id: 5, function: "5", cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407542 } +; CHECK-NEXT: - { type: 0, func-id: 268435455, function: "268435455", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407552 } +; CHECK-NEXT: - { type: 0, func-id: 268435455, function: "268435455", cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407562 } +; CHECK-NEXT: - { type: 0, func-id: 6, function: "6", cpu: 6, thread: 5, kind: function-enter, tsc: 7238225556407682 } +; CHECK-NEXT: - { type: 0, func-id: 6, function: "6", cpu: 6, thread: 5, kind: function-exit, tsc: 7238225556407755 } ; CHECK-NEXT: ... Index: llvm/test/tools/llvm-xray/X86/convert-roundtrip.yaml =================================================================== --- llvm/test/tools/llvm-xray/X86/convert-roundtrip.yaml +++ llvm/test/tools/llvm-xray/X86/convert-roundtrip.yaml @@ -19,6 +19,6 @@ #CHECK-NEXT: nonstop-tsc: true #CHECK-NEXT: cycle-frequency: 2601000000 #CHECK-NEXT: records: -#CHECK-NEXT: - { type: 0, func-id: 1, function: '1', cpu: 1, thread: 111, kind: function-enter, tsc: 10001 } -#CHECK-NEXT: - { type: 0, func-id: 1, function: '1', cpu: 1, thread: 111, kind: function-exit, tsc: 10100 } +#CHECK-NEXT: - { type: 0, func-id: 1, function: "1", cpu: 1, thread: 111, kind: function-enter, tsc: 10001 } +#CHECK-NEXT: - { type: 0, func-id: 1, function: "1", cpu: 1, thread: 111, kind: function-exit, tsc: 10100 } #CHECK-NEXT: ... Index: llvm/test/tools/llvm-xray/X86/convert-to-yaml.txt =================================================================== --- llvm/test/tools/llvm-xray/X86/convert-to-yaml.txt +++ llvm/test/tools/llvm-xray/X86/convert-to-yaml.txt @@ -8,10 +8,10 @@ ; CHECK-NEXT: nonstop-tsc: true ; CHECK-NEXT: cycle-frequency: 2601000000 ; CHECK-NEXT: records: -; CHECK-NEXT: - { type: 0, func-id: 3, function: '3', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 } -; CHECK-NEXT: - { type: 0, func-id: 2, function: '2', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 } -; CHECK-NEXT: - { type: 0, func-id: 2, function: '2', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 } -; CHECK-NEXT: - { type: 0, func-id: 1, function: '1', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 } -; CHECK-NEXT: - { type: 0, func-id: 1, function: '1', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 } -; CHECK-NEXT: - { type: 0, func-id: 3, function: '3', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 } +; CHECK-NEXT: - { type: 0, func-id: 3, function: "3", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 } +; CHECK-NEXT: - { type: 0, func-id: 2, function: "2", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 } +; CHECK-NEXT: - { type: 0, func-id: 2, function: "2", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 } +; CHECK-NEXT: - { type: 0, func-id: 1, function: "1", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 } +; CHECK-NEXT: - { type: 0, func-id: 1, function: "1", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 } +; CHECK-NEXT: - { type: 0, func-id: 3, function: "3", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 } ; CHECK-NEXT: ... Index: llvm/test/tools/llvm-xray/X86/convert-with-standalone-instrmap.txt =================================================================== --- llvm/test/tools/llvm-xray/X86/convert-with-standalone-instrmap.txt +++ llvm/test/tools/llvm-xray/X86/convert-with-standalone-instrmap.txt @@ -8,10 +8,10 @@ ; CHECK-NEXT: nonstop-tsc: true ; CHECK-NEXT: cycle-frequency: 2601000000 ; CHECK-NEXT: records: -; CHECK-NEXT: - { type: 0, func-id: 3, function: '@(41caa0)', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 } -; CHECK-NEXT: - { type: 0, func-id: 2, function: '@(41ca70)', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 } -; CHECK-NEXT: - { type: 0, func-id: 2, function: '@(41ca70)', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 } -; CHECK-NEXT: - { type: 0, func-id: 1, function: '@(41ca40)', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 } -; CHECK-NEXT: - { type: 0, func-id: 1, function: '@(41ca40)', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 } -; CHECK-NEXT: - { type: 0, func-id: 3, function: '@(41caa0)', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 } +; CHECK-NEXT: - { type: 0, func-id: 3, function: "@(41caa0)", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 } +; CHECK-NEXT: - { type: 0, func-id: 2, function: "@(41ca70)", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 } +; CHECK-NEXT: - { type: 0, func-id: 2, function: "@(41ca70)", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 } +; CHECK-NEXT: - { type: 0, func-id: 1, function: "@(41ca40)", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 } +; CHECK-NEXT: - { type: 0, func-id: 1, function: "@(41ca40)", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 } +; CHECK-NEXT: - { type: 0, func-id: 3, function: "@(41caa0)", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 } ; CHECK-NEXT: ... Index: llvm/test/tools/llvm-xray/X86/convert-with-yaml-instrmap.txt =================================================================== --- llvm/test/tools/llvm-xray/X86/convert-with-yaml-instrmap.txt +++ llvm/test/tools/llvm-xray/X86/convert-with-yaml-instrmap.txt @@ -8,10 +8,10 @@ ; CHECK-NEXT: nonstop-tsc: true ; CHECK-NEXT: cycle-frequency: 2601000000 ; CHECK-NEXT: records: -; CHECK-NEXT: - { type: 0, func-id: 3, function: '3', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 } -; CHECK-NEXT: - { type: 0, func-id: 2, function: '2', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 } -; CHECK-NEXT: - { type: 0, func-id: 2, function: '2', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 } -; CHECK-NEXT: - { type: 0, func-id: 1, function: '1', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 } -; CHECK-NEXT: - { type: 0, func-id: 1, function: '1', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 } -; CHECK-NEXT: - { type: 0, func-id: 3, function: '3', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 } +; CHECK-NEXT: - { type: 0, func-id: 3, function: "3", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 } +; CHECK-NEXT: - { type: 0, func-id: 2, function: "2", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 } +; CHECK-NEXT: - { type: 0, func-id: 2, function: "2", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 } +; CHECK-NEXT: - { type: 0, func-id: 1, function: "1", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 } +; CHECK-NEXT: - { type: 0, func-id: 1, function: "1", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 } +; CHECK-NEXT: - { type: 0, func-id: 3, function: "3", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 } ; CHECK-NEXT: ... Index: llvm/unittests/ObjectYAML/YAMLTest.cpp =================================================================== --- llvm/unittests/ObjectYAML/YAMLTest.cpp +++ llvm/unittests/ObjectYAML/YAMLTest.cpp @@ -34,5 +34,5 @@ llvm::raw_svector_ostream OS(Buf); yaml::Output YOut(OS); YOut << BH; - EXPECT_NE(OS.str().find("''"), StringRef::npos); + EXPECT_NE(OS.str().find("\"\""), StringRef::npos); } Index: llvm/unittests/Support/YAMLIOTest.cpp =================================================================== --- llvm/unittests/Support/YAMLIOTest.cpp +++ llvm/unittests/Support/YAMLIOTest.cpp @@ -505,6 +505,8 @@ llvm::StringRef str9; llvm::StringRef str10; llvm::StringRef str11; + llvm::StringRef str12; + llvm::StringRef str13; std::string stdstr1; std::string stdstr2; std::string stdstr3; @@ -516,6 +518,8 @@ std::string stdstr9; std::string stdstr10; std::string stdstr11; + std::string stdstr12; + std::string stdstr13; }; namespace llvm { @@ -534,6 +538,8 @@ io.mapRequired("str9", st.str9); io.mapRequired("str10", st.str10); io.mapRequired("str11", st.str11); + io.mapRequired("str12", st.str12); + io.mapRequired("str13", st.str13); io.mapRequired("stdstr1", st.stdstr1); io.mapRequired("stdstr2", st.stdstr2); io.mapRequired("stdstr3", st.stdstr3); @@ -545,12 +551,21 @@ io.mapRequired("stdstr9", st.stdstr9); io.mapRequired("stdstr10", st.stdstr10); io.mapRequired("stdstr11", st.stdstr11); + io.mapRequired("stdstr12", st.stdstr12); + io.mapRequired("stdstr13", st.stdstr13); } }; } } TEST(YAMLIO, TestReadWriteStringTypes) { + static const char quoted[34] = + "\001\002\003\004\005\006\007\010\011\012\013\014\015\016\017" + "\020\021\022\023\024\025\026\027\030\031\032\033\034\035\036" + "\037\000\177"; + static const char unquoted[] = + "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ" + "0123456789_-/^.,"; std::string intermediate; { StringTypes map; @@ -565,6 +580,8 @@ map.str9 = "~"; map.str10 = "0.2e20"; map.str11 = "0x30"; + map.str12 = unquoted; + map.str13 = llvm::StringRef(quoted, 33); map.stdstr1 = "'eee"; map.stdstr2 = "\"fff"; map.stdstr3 = "`ggg"; @@ -576,6 +593,8 @@ map.stdstr9 = "~"; map.stdstr10 = "0.2e20"; map.stdstr11 = "0x30"; + map.stdstr12 = unquoted; + map.stdstr13 = std::string(quoted, 33); llvm::raw_string_ostream ostr(intermediate); Output yout(ostr); @@ -583,23 +602,33 @@ } llvm::StringRef flowOut(intermediate); - EXPECT_NE(llvm::StringRef::npos, flowOut.find("'''aaa")); - EXPECT_NE(llvm::StringRef::npos, flowOut.find("'\"bbb'")); - EXPECT_NE(llvm::StringRef::npos, flowOut.find("'`ccc'")); - EXPECT_NE(llvm::StringRef::npos, flowOut.find("'@ddd'")); - EXPECT_NE(llvm::StringRef::npos, flowOut.find("''\n")); - EXPECT_NE(llvm::StringRef::npos, flowOut.find("'0000000004000000'\n")); - EXPECT_NE(llvm::StringRef::npos, flowOut.find("'true'\n")); - EXPECT_NE(llvm::StringRef::npos, flowOut.find("'FALSE'\n")); - EXPECT_NE(llvm::StringRef::npos, flowOut.find("'~'\n")); - EXPECT_NE(llvm::StringRef::npos, flowOut.find("'0.2e20'\n")); - EXPECT_NE(llvm::StringRef::npos, flowOut.find("'0x30'\n")); - EXPECT_NE(std::string::npos, flowOut.find("'''eee")); - EXPECT_NE(std::string::npos, flowOut.find("'\"fff'")); - EXPECT_NE(std::string::npos, flowOut.find("'`ggg'")); - EXPECT_NE(std::string::npos, flowOut.find("'@hhh'")); - EXPECT_NE(std::string::npos, flowOut.find("''\n")); - EXPECT_NE(std::string::npos, flowOut.find("'0000000004000000'\n")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"'aaa\"")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"\\\"bbb\"")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"`ccc\"")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"@ddd\"")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"\"\n")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"0000000004000000\"\n")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"true\"\n")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"FALSE\"\n")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"~\"\n")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"0.2e20\"\n")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"0x30\"\n")); + EXPECT_NE(llvm::StringRef::npos, flowOut.find(unquoted)); + EXPECT_NE(llvm::StringRef::npos, flowOut.find( + "\"\\x01\\x02\\x03\\x04\\x05\\x06\\x07\\x08\\x09\\x0A\\x0B\\x0C\\x0D\\x0E" + "\\x0F\\x10\\x11\\x12\\x13\\x14\\x15\\x16\\x17\\x18\\x19\\x1A\\x1B\\x1C" + "\\x1D\\x1E\\x1F\\x00\\x7F\"")); + EXPECT_NE(std::string::npos, flowOut.find("\"'eee\"")); + EXPECT_NE(std::string::npos, flowOut.find("\"\\\"fff\"")); + EXPECT_NE(std::string::npos, flowOut.find("\"`ggg\"")); + EXPECT_NE(std::string::npos, flowOut.find("\"@hhh\"")); + EXPECT_NE(std::string::npos, flowOut.find("\"\"\n")); + EXPECT_NE(std::string::npos, flowOut.find("\"0000000004000000\"\n")); + EXPECT_NE(std::string::npos, flowOut.find(unquoted)); + EXPECT_NE(llvm::StringRef::npos, flowOut.find( + "\"\\x01\\x02\\x03\\x04\\x05\\x06\\x07\\x08\\x09\\x0A\\x0B\\x0C\\x0D\\x0E" + "\\x0F\\x10\\x11\\x12\\x13\\x14\\x15\\x16\\x17\\x18\\x19\\x1A\\x1B\\x1C" + "\\x1D\\x1E\\x1F\\x00\\x7F\"")); { Input yin(intermediate); @@ -613,12 +642,16 @@ EXPECT_TRUE(map.str4.equals("@ddd")); EXPECT_TRUE(map.str5.equals("")); EXPECT_TRUE(map.str6.equals("0000000004000000")); + EXPECT_TRUE(map.str12.equals(unquoted)); + EXPECT_TRUE(map.str13.equals(llvm::StringRef(quoted, 33))); EXPECT_TRUE(map.stdstr1 == "'eee"); EXPECT_TRUE(map.stdstr2 == "\"fff"); EXPECT_TRUE(map.stdstr3 == "`ggg"); EXPECT_TRUE(map.stdstr4 == "@hhh"); EXPECT_TRUE(map.stdstr5 == ""); EXPECT_TRUE(map.stdstr6 == "0000000004000000"); + EXPECT_TRUE(map.stdstr12 == unquoted); + EXPECT_TRUE(map.stdstr13 == std::string(quoted, 33)); } }