Index: llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -730,7 +730,8 @@
     // Make sure sources are identical.
     const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
     const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
-    if (!Src0->isReg() || Src0->getSubReg() != Src1->getSubReg() ||
+    if (!Src0->isReg() || !Src1->isReg() ||
+        Src0->getSubReg() != Src1->getSubReg() ||
         Src0->getSubReg() != AMDGPU::NoSubRegister)
       return nullptr;
 
Index: llvm/trunk/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
@@ -24,6 +24,10 @@
     ret void
   }
 
+  define amdgpu_ps void @v_max_reg_imm_f32() #0 {
+    ret void
+  }
+
   attributes #0 = { nounwind "no-signed-zeros-fp-math"="false" }
 
 ...
@@ -422,3 +426,19 @@
     S_ENDPGM
 
 ...
+---
+
+# Pass used to crash with immediate second operand of max
+name:            v_max_reg_imm_f32
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32 }
+  - { id: 1, class: vgpr_32 }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: %vgpr0
+
+    %0 = COPY %vgpr0
+    %1 = V_MAX_F32_e64 0, killed %0, 0, 1056964608, 1, 0, implicit %exec
+
+...