Index: lib/Target/AArch64/AArch64.td
===================================================================
--- lib/Target/AArch64/AArch64.td
+++ lib/Target/AArch64/AArch64.td
@@ -362,6 +362,7 @@
 
 def : ProcessorModel<"generic", NoSchedModel, [
                      FeatureFPARMv8,
+                     FeatureFuseAES,
                      FeatureNEON,
                      FeaturePerfMon,
                      FeaturePostRAScheduler
Index: test/CodeGen/AArch64/misched-fusion-aes.ll
===================================================================
--- test/CodeGen/AArch64/misched-fusion-aes.ll
+++ test/CodeGen/AArch64/misched-fusion-aes.ll
@@ -1,7 +1,8 @@
-; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX
-; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX
-; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX
-; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=generic -mattr=+crypto | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEAES
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEAES
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEAES
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEAES
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEAES
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m1  | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKM1
 
 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %d, <16 x i8> %k)
@@ -74,22 +75,22 @@
   ret void
 
 ; CHECK-LABEL: aesea:
-; CHECKCORTEX: aese [[VA:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VA]]
-; CHECKCORTEX: aese [[VB:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VB]]
-; CHECKCORTEX: aese [[VC:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VC]]
-; CHECKCORTEX: aese [[VD:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VD]]
-; CHECKCORTEX: aese [[VE:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VE]]
-; CHECKCORTEX: aese [[VF:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VF]]
-; CHECKCORTEX: aese [[VG:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VG]]
-; CHECKCORTEX: aese [[VH:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VH]]
+; CHECKFUSEAES: aese [[VA:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesmc {{v[0-7].16b}}, [[VA]]
+; CHECKFUSEAES: aese [[VB:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesmc {{v[0-7].16b}}, [[VB]]
+; CHECKFUSEAES: aese [[VC:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesmc {{v[0-7].16b}}, [[VC]]
+; CHECKFUSEAES: aese [[VD:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesmc {{v[0-7].16b}}, [[VD]]
+; CHECKFUSEAES: aese [[VE:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesmc {{v[0-7].16b}}, [[VE]]
+; CHECKFUSEAES: aese [[VF:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesmc {{v[0-7].16b}}, [[VF]]
+; CHECKFUSEAES: aese [[VG:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesmc {{v[0-7].16b}}, [[VG]]
+; CHECKFUSEAES: aese [[VH:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesmc {{v[0-7].16b}}, [[VH]]
 
 ; CHECKM1: aese [[VA:v[0-7].16b]], {{v[0-7].16b}}
 ; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VA]]
@@ -175,22 +176,22 @@
   ret void
 
 ; CHECK-LABEL: aesda:
-; CHECKCORTEX: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VA]]
-; CHECKCORTEX: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VB]]
-; CHECKCORTEX: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VC]]
-; CHECKCORTEX: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VD]]
-; CHECKCORTEX: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VE]]
-; CHECKCORTEX: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VF]]
-; CHECKCORTEX: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VG]]
-; CHECKCORTEX: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}}
-; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VH]]
+; CHECKFUSEAES: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesimc {{v[0-7].16b}}, [[VA]]
+; CHECKFUSEAES: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesimc {{v[0-7].16b}}, [[VB]]
+; CHECKFUSEAES: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesimc {{v[0-7].16b}}, [[VC]]
+; CHECKFUSEAES: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesimc {{v[0-7].16b}}, [[VD]]
+; CHECKFUSEAES: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesimc {{v[0-7].16b}}, [[VE]]
+; CHECKFUSEAES: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesimc {{v[0-7].16b}}, [[VF]]
+; CHECKFUSEAES: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesimc {{v[0-7].16b}}, [[VG]]
+; CHECKFUSEAES: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}}
+; CHECKFUSEAES-NEXT: aesimc {{v[0-7].16b}}, [[VH]]
 
 ; CHECKM1: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}}
 ; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VA]]