Index: llvm/trunk/include/llvm/Target/TargetMachine.h
===================================================================
--- llvm/trunk/include/llvm/Target/TargetMachine.h
+++ llvm/trunk/include/llvm/Target/TargetMachine.h
@@ -299,6 +299,12 @@
   bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
                          raw_pwrite_stream &OS,
                          bool DisableVerify = true) override;
+
+  /// Returns true if the target is expected to pass all machine verifier
+  /// checks. This is a stopgap measure to fix targets one by one. We will
+  /// remove this at some point and always enable the verifier when
+  /// EXPENSIVE_CHECKS is enabled.
+  virtual bool isMachineVerifierClean() const { return true; }
 };
 
 } // end namespace llvm
Index: llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
+++ llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
@@ -430,7 +430,12 @@
 }
 
 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
-  if (VerifyMachineCode)
+  bool Verify = VerifyMachineCode;
+#ifdef EXPENSIVE_CHECKS
+  if (VerifyMachineCode == cl::BOU_UNSET)
+    Verify = TM->isMachineVerifierClean();
+#endif
+  if (Verify)
     PM->add(createMachineVerifierPass(Banner));
 }
 
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -69,7 +69,6 @@
       return -1;
     return 0;
   }
-
 };
 
 //===----------------------------------------------------------------------===//
@@ -89,6 +88,10 @@
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   const R600Subtarget *getSubtargetImpl(const Function &) const override;
+
+  bool isMachineVerifierClean() const override {
+    return false;
+  }
 };
 
 //===----------------------------------------------------------------------===//
Index: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
@@ -60,6 +60,10 @@
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
+
+  bool isMachineVerifierClean() const override {
+    return false;
+  }
 };
 
 /// ARM/Thumb little endian target machine.
Index: llvm/trunk/lib/Target/AVR/AVRTargetMachine.h
===================================================================
--- llvm/trunk/lib/Target/AVR/AVRTargetMachine.h
+++ llvm/trunk/lib/Target/AVR/AVRTargetMachine.h
@@ -41,6 +41,10 @@
 
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
+  bool isMachineVerifierClean() const override {
+    return false;
+  }
+
 private:
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   AVRSubtarget SubTarget;
Index: llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.h
===================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.h
+++ llvm/trunk/lib/Target/Lanai/LanaiTargetMachine.h
@@ -49,6 +49,10 @@
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
+
+  bool isMachineVerifierClean() const override {
+    return false;
+  }
 };
 } // namespace llvm
 
Index: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
@@ -66,6 +66,10 @@
 
   bool isLittleEndian() const { return isLittle; }
   const MipsABIInfo &getABI() const { return ABI; }
+
+  bool isMachineVerifierClean() const override {
+    return false;
+  }
 };
 
 /// Mips32/64 big endian target machine.
Index: llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h
===================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h
+++ llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h
@@ -65,6 +65,9 @@
 
   TargetIRAnalysis getTargetIRAnalysis() override;
 
+  bool isMachineVerifierClean() const override {
+    return false;
+  }
 }; // NVPTXTargetMachine.
 
 class NVPTXTargetMachine32 : public NVPTXTargetMachine {
Index: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
@@ -55,6 +55,10 @@
     const Triple &TT = getTargetTriple();
     return (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
   };
+
+  bool isMachineVerifierClean() const override {
+    return false;
+  }
 };
 
 /// PowerPC 32-bit target machine.
Index: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
===================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
@@ -40,6 +40,10 @@
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
+
+  bool isMachineVerifierClean() const override {
+    return false;
+  }
 };
 
 /// Sparc 32-bit target machine
Index: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h
===================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h
+++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -51,6 +51,8 @@
   }
 
   bool targetSchedulesPostRAScheduling() const override { return true; };
+
+  bool isMachineVerifierClean() const override { return false; }
 };
 
 } // end namespace llvm
Index: llvm/trunk/lib/Target/X86/X86TargetMachine.h
===================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.h
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.h
@@ -49,6 +49,10 @@
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
+
+  bool isMachineVerifierClean() const override {
+    return false;
+  }
 };
 
 } // end namespace llvm
Index: llvm/trunk/test/CodeGen/MIR/Generic/multiRunPass.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/Generic/multiRunPass.mir
+++ llvm/trunk/test/CodeGen/MIR/Generic/multiRunPass.mir
@@ -7,8 +7,8 @@
 # This test ensures that the command line accepts
 # several run passes on the same command line and
 # actually create the proper pipeline for it.
-# PSEUDO_PEEPHOLE: -expand-isel-pseudos -peephole-opt
-# PEEPHOLE_PSEUDO: -peephole-opt -expand-isel-pseudos
+# PSEUDO_PEEPHOLE: -expand-isel-pseudos {{(-machineverifier )?}}-peephole-opt
+# PEEPHOLE_PSEUDO: -peephole-opt {{(-machineverifier )?}}-expand-isel-pseudos
 
 # Make sure there are no other passes happening after what we asked.
 # CHECK-NEXT: --- |