Index: lib/Target/X86/X86InstructionSelector.cpp =================================================================== --- lib/Target/X86/X86InstructionSelector.cpp +++ lib/Target/X86/X86InstructionSelector.cpp @@ -72,9 +72,28 @@ MachineFunction &MF) const; bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const; - bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const; + bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI, + MachineFunction &MF) const; + bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI, + MachineFunction &MF) const; + bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI, + MachineFunction &MF) const; + bool selectExtract(MachineInstr &I, MachineRegisterInfo &MRI, + MachineFunction &MF) const; + bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const; + + // emit insert subreg instruction and insert it before MachineInstr &I + bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, + MachineRegisterInfo &MRI, MachineFunction &MF) const; + // emit extract subreg instruction and insert it before MachineInstr &I + bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, + MachineRegisterInfo &MRI, MachineFunction &MF) const; + + const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const; + const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg, + MachineRegisterInfo &MRI) const; const X86TargetMachine &TM; const X86Subtarget &STI; @@ -113,8 +132,8 @@ // FIXME: This should be target-independent, inferred from the types declared // for each class in the bank. -static const TargetRegisterClass * -getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) { +const TargetRegisterClass * +X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { if (RB.getID() == X86::GPRRegBankID) { if (Ty.getSizeInBits() <= 8) return &X86::GR8RegClass; @@ -127,13 +146,13 @@ } if (RB.getID() == X86::VECRRegBankID) { if (Ty.getSizeInBits() == 32) - return &X86::FR32XRegClass; + return STI.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass; if (Ty.getSizeInBits() == 64) - return &X86::FR64XRegClass; + return STI.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass; if (Ty.getSizeInBits() == 128) - return &X86::VR128XRegClass; + return STI.hasAVX512() ? &X86::VR128XRegClass : &X86::VR128RegClass; if (Ty.getSizeInBits() == 256) - return &X86::VR256XRegClass; + return STI.hasAVX512() ? &X86::VR256XRegClass : &X86::VR256RegClass; if (Ty.getSizeInBits() == 512) return &X86::VR512RegClass; } @@ -141,10 +160,16 @@ llvm_unreachable("Unknown RegBank!"); } +const TargetRegisterClass * +X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, + MachineRegisterInfo &MRI) const { + const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); + return getRegClass(Ty, RegBank); +} + // Set X86 Opcode and constrain DestReg. -static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, - MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, - const RegisterBankInfo &RBI) { +bool X86InstructionSelector::selectCopy(MachineInstr &I, + MachineRegisterInfo &MRI) const { unsigned DstReg = I.getOperand(0).getReg(); if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { @@ -171,7 +196,7 @@ switch (RegBank.getID()) { case X86::GPRRegBankID: assert((DstSize <= 64) && "GPRs cannot get more than 64-bit width values."); - RC = getRegClassForTypeOnBank(MRI.getType(DstReg), RegBank); + RC = getRegClass(MRI.getType(DstReg), RegBank); // Change the physical register if (SrcSize > DstSize && TargetRegisterInfo::isPhysicalRegister(SrcReg)) { @@ -186,7 +211,7 @@ } break; case X86::VECRRegBankID: - RC = getRegClassForTypeOnBank(MRI.getType(DstReg), RegBank); + RC = getRegClass(MRI.getType(DstReg), RegBank); break; default: llvm_unreachable("Unknown RegBank!"); @@ -220,7 +245,7 @@ // Certain non-generic instructions also need some special handling. if (I.isCopy()) - return selectCopy(I, TII, MRI, TRI, RBI); + return selectCopy(I, MRI); // TODO: handle more cases - LOAD_STACK_GUARD, PHI return true; @@ -249,6 +274,14 @@ return true; if (selectUadde(I, MRI, MF)) return true; + if (selectUnmergeValues(I, MRI, MF)) + return true; + if (selectMergeValues(I, MRI, MF)) + return true; + if (selectExtract(I, MRI, MF)) + return true; + if (selectInsert(I, MRI, MF)) + return true; return false; } @@ -461,11 +494,11 @@ if (DstRB.getID() != X86::GPRRegBankID) return false; - const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); + const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); if (!DstRC) return false; - const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(SrcTy, SrcRB); + const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); if (!SrcRC) return false; @@ -520,8 +553,7 @@ return false; const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); - unsigned DefReg = - MRI.createVirtualRegister(getRegClassForTypeOnBank(DstTy, RegBank)); + unsigned DefReg = MRI.createVirtualRegister(getRegClass(DstTy, RegBank)); BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::SUBREG_TO_REG), DefReg) @@ -656,6 +688,266 @@ return true; } +bool X86InstructionSelector::selectExtract(MachineInstr &I, + MachineRegisterInfo &MRI, + MachineFunction &MF) const { + + if (I.getOpcode() != TargetOpcode::G_EXTRACT) + return false; + + const unsigned DstReg = I.getOperand(0).getReg(); + const unsigned SrcReg = I.getOperand(1).getReg(); + int64_t Index = I.getOperand(2).getImm(); + + const LLT DstTy = MRI.getType(DstReg); + const LLT SrcTy = MRI.getType(SrcReg); + + // Meanwile handle vector type only. + if (!DstTy.isVector()) + return false; + + if (Index % DstTy.getSizeInBits() != 0) + return false; // Not extract subvector. + + if (Index == 0) { + // Replace by extract subreg copy. + if (!emitExtractSubreg(DstReg, SrcReg, I, MRI, MF)) + return false; + + I.eraseFromParent(); + return true; + } + + bool HasAVX = STI.hasAVX(); + bool HasAVX512 = STI.hasAVX512(); + bool HasVLX = STI.hasVLX(); + + if (SrcTy.getSizeInBits() == 256 && DstTy.getSizeInBits() == 128) { + if (HasVLX) + I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr)); + else if (HasAVX) + I.setDesc(TII.get(X86::VEXTRACTF128rr)); + else + return false; + } else if (SrcTy.getSizeInBits() == 512 && HasAVX512) { + if (DstTy.getSizeInBits() == 128) + I.setDesc(TII.get(X86::VEXTRACTF32x4Zrr)); + else if (DstTy.getSizeInBits() == 256) + I.setDesc(TII.get(X86::VEXTRACTF64x4Zrr)); + else + return false; + } else + return false; + + // Convert to X86 VEXTRACT immediate. + Index = Index / DstTy.getSizeInBits(); + I.getOperand(2).setImm(Index); + + return constrainSelectedInstRegOperands(I, TII, TRI, RBI); +} + +bool X86InstructionSelector::emitExtractSubreg(unsigned DstReg, unsigned SrcReg, + MachineInstr &I, + MachineRegisterInfo &MRI, + MachineFunction &MF) const { + + const LLT DstTy = MRI.getType(DstReg); + const LLT SrcTy = MRI.getType(SrcReg); + + unsigned SubIdx = X86::NoSubRegister; + if (DstTy.getSizeInBits() == 128) + SubIdx = X86::sub_xmm; + else if (DstTy.getSizeInBits() == 256) + SubIdx = X86::sub_ymm; + else + return false; + + const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); + const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI); + + SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx); + + if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || + !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { + DEBUG(dbgs() << "Failed to constrain G_TRUNC\n"); + return false; + } + + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg) + .addReg(SrcReg, 0, SubIdx); + + return true; +} + +bool X86InstructionSelector::emitInsertSubreg(unsigned DstReg, unsigned SrcReg, + MachineInstr &I, + MachineRegisterInfo &MRI, + MachineFunction &MF) const { + + const LLT DstTy = MRI.getType(DstReg); + const LLT SrcTy = MRI.getType(SrcReg); + + unsigned SubIdx = X86::NoSubRegister; + if (SrcTy.getSizeInBits() == 128) + SubIdx = X86::sub_xmm; + else if (SrcTy.getSizeInBits() == 256) + SubIdx = X86::sub_ymm; + else + return false; + + const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI); + const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); + + if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || + !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { + DEBUG(dbgs() << "Failed to constrain INSERT_SUBREG\n"); + return false; + } + + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY)) + .addReg(DstReg, RegState::DefineNoRead, SubIdx) + .addReg(SrcReg); + + return true; +} + +bool X86InstructionSelector::selectInsert(MachineInstr &I, + MachineRegisterInfo &MRI, + MachineFunction &MF) const { + + if (I.getOpcode() != TargetOpcode::G_INSERT) + return false; + + const unsigned DstReg = I.getOperand(0).getReg(); + const unsigned SrcReg = I.getOperand(1).getReg(); + const unsigned InsertReg = I.getOperand(2).getReg(); + int64_t Index = I.getOperand(3).getImm(); + + const LLT DstTy = MRI.getType(DstReg); + const LLT InsertRegTy = MRI.getType(InsertReg); + + // Meanwile handle vector type only. + if (!DstTy.isVector()) + return false; + + if (Index % InsertRegTy.getSizeInBits() != 0) + return false; // Not insert subvector. + + if (Index == 0 && MRI.getVRegDef(SrcReg)->isImplicitDef()) { + // Replace by subreg copy. + if (!emitInsertSubreg(DstReg, InsertReg, I, MRI, MF)) + return false; + + I.eraseFromParent(); + return true; + } + + bool HasAVX = STI.hasAVX(); + bool HasAVX512 = STI.hasAVX512(); + bool HasVLX = STI.hasVLX(); + + if (DstTy.getSizeInBits() == 256 && InsertRegTy.getSizeInBits() == 128) { + if (HasVLX) + I.setDesc(TII.get(X86::VINSERTF32x4Z256rr)); + else if (HasAVX) + I.setDesc(TII.get(X86::VINSERTF128rr)); + else + return false; + } else if (DstTy.getSizeInBits() == 512 && HasAVX512) { + if (InsertRegTy.getSizeInBits() == 128) + I.setDesc(TII.get(X86::VINSERTF32x4Zrr)); + else if (InsertRegTy.getSizeInBits() == 256) + I.setDesc(TII.get(X86::VINSERTF64x4Zrr)); + else + return false; + } else + return false; + + // Convert to X86 VINSERT immediate. + Index = Index / InsertRegTy.getSizeInBits(); + + I.getOperand(3).setImm(Index); + + return constrainSelectedInstRegOperands(I, TII, TRI, RBI); +} + +bool X86InstructionSelector::selectUnmergeValues(MachineInstr &I, + MachineRegisterInfo &MRI, + MachineFunction &MF) const { + if (I.getOpcode() != TargetOpcode::G_UNMERGE_VALUES) + return false; + + // Split to extracts. + unsigned NumDefs = I.getNumOperands() - 1; + unsigned SrcReg = I.getOperand(NumDefs).getReg(); + unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); + + for (unsigned Idx = 0; Idx < NumDefs; ++Idx) { + + MachineInstr &ExtrInst = + *BuildMI(*I.getParent(), I, I.getDebugLoc(), + TII.get(TargetOpcode::G_EXTRACT), I.getOperand(Idx).getReg()) + .addReg(SrcReg) + .addImm(Idx * DefSize); + + if (!select(ExtrInst)) + return false; + } + + I.eraseFromParent(); + return true; +} + +bool X86InstructionSelector::selectMergeValues(MachineInstr &I, + MachineRegisterInfo &MRI, + MachineFunction &MF) const { + if (I.getOpcode() != TargetOpcode::G_MERGE_VALUES) + return false; + + // Split to inserts. + unsigned DstReg = I.getOperand(0).getReg(); + unsigned SrcReg0 = I.getOperand(1).getReg(); + + const LLT DstTy = MRI.getType(DstReg); + const LLT SrcTy = MRI.getType(SrcReg0); + unsigned SrcSize = SrcTy.getSizeInBits(); + + const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); + + // For the first src use insertSubReg. + unsigned DefReg = MRI.createGenericVirtualRegister(DstTy); + MRI.setRegBank(DefReg, RegBank); + if (!emitInsertSubreg(DefReg, I.getOperand(1).getReg(), I, MRI, MF)) + return false; + + for (unsigned Idx = 2; Idx < I.getNumOperands(); ++Idx) { + + unsigned Tmp = MRI.createGenericVirtualRegister(DstTy); + MRI.setRegBank(Tmp, RegBank); + + MachineInstr &InsertInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(), + TII.get(TargetOpcode::G_INSERT), Tmp) + .addReg(DefReg) + .addReg(I.getOperand(Idx).getReg()) + .addImm((Idx - 1) * SrcSize); + + DefReg = Tmp; + + if (!select(InsertInst)) + return false; + } + + MachineInstr &CopyInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(), + TII.get(TargetOpcode::COPY), DstReg) + .addReg(DefReg); + + if (!select(CopyInst)) + return false; + + I.eraseFromParent(); + return true; +} + InstructionSelector * llvm::createX86InstructionSelector(const X86TargetMachine &TM, X86Subtarget &Subtarget, Index: lib/Target/X86/X86LegalizerInfo.cpp =================================================================== --- lib/Target/X86/X86LegalizerInfo.cpp +++ lib/Target/X86/X86LegalizerInfo.cpp @@ -214,12 +214,24 @@ if (!Subtarget.hasAVX()) return; + const LLT v16s8 = LLT::vector(16, 8); + const LLT v8s16 = LLT::vector(8, 16); + const LLT v4s32 = LLT::vector(4, 32); + const LLT v2s64 = LLT::vector(2, 64); + + const LLT v32s8 = LLT::vector(32, 8); + const LLT v16s16 = LLT::vector(16, 16); const LLT v8s32 = LLT::vector(8, 32); const LLT v4s64 = LLT::vector(4, 64); for (unsigned MemOp : {G_LOAD, G_STORE}) for (auto Ty : {v8s32, v4s64}) setAction({MemOp, Ty}, Legal); + + for (auto Ty : {v32s8, v16s16, v8s32, v4s64}) + setAction({G_INSERT, Ty}, Legal); + for (auto Ty : {v16s8, v8s16, v4s32, v2s64}) + setAction({G_INSERT, 1, Ty}, Legal); } void X86LegalizerInfo::setLegalizerInfoAVX2() { @@ -243,6 +255,18 @@ if (!Subtarget.hasAVX512()) return; + const LLT v16s8 = LLT::vector(16, 8); + const LLT v8s16 = LLT::vector(8, 16); + const LLT v4s32 = LLT::vector(4, 32); + const LLT v2s64 = LLT::vector(2, 64); + + const LLT v32s8 = LLT::vector(32, 8); + const LLT v16s16 = LLT::vector(16, 16); + const LLT v8s32 = LLT::vector(8, 32); + const LLT v4s64 = LLT::vector(4, 64); + + const LLT v64s8 = LLT::vector(64, 8); + const LLT v32s16 = LLT::vector(32, 16); const LLT v16s32 = LLT::vector(16, 32); const LLT v8s64 = LLT::vector(8, 64); @@ -256,13 +280,15 @@ for (auto Ty : {v16s32, v8s64}) setAction({MemOp, Ty}, Legal); + for (auto Ty : {v64s8, v32s16, v16s32, v8s64}) + setAction({G_INSERT, Ty}, Legal); + for (auto Ty : {v32s8, v16s16, v8s32, v4s64, v16s8, v8s16, v4s32, v2s64}) + setAction({G_INSERT, 1, Ty}, Legal); + /************ VLX *******************/ if (!Subtarget.hasVLX()) return; - const LLT v4s32 = LLT::vector(4, 32); - const LLT v8s32 = LLT::vector(8, 32); - for (auto Ty : {v4s32, v8s32}) setAction({G_MUL, Ty}, Legal); } Index: test/CodeGen/X86/GlobalISel/add-vec.ll =================================================================== --- test/CodeGen/X86/GlobalISel/add-vec.ll +++ test/CodeGen/X86/GlobalISel/add-vec.ll @@ -1,38 +1,41 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=SKX +; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SKX +; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=core-avx2 -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2 +; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=corei7-avx -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX1 + define <16 x i8> @test_add_v16i8(<16 x i8> %arg1, <16 x i8> %arg2) { -; SKX-LABEL: test_add_v16i8: -; SKX: # BB#0: -; SKX-NEXT: vpaddb %xmm1, %xmm0, %xmm0 -; SKX-NEXT: retq +; ALL-LABEL: test_add_v16i8: +; ALL: # BB#0: +; ALL-NEXT: vpaddb %xmm1, %xmm0, %xmm0 +; ALL-NEXT: retq %ret = add <16 x i8> %arg1, %arg2 ret <16 x i8> %ret } define <8 x i16> @test_add_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) { -; SKX-LABEL: test_add_v8i16: -; SKX: # BB#0: -; SKX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 -; SKX-NEXT: retq +; ALL-LABEL: test_add_v8i16: +; ALL: # BB#0: +; ALL-NEXT: vpaddw %xmm1, %xmm0, %xmm0 +; ALL-NEXT: retq %ret = add <8 x i16> %arg1, %arg2 ret <8 x i16> %ret } define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) { -; SKX-LABEL: test_add_v4i32: -; SKX: # BB#0: -; SKX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; SKX-NEXT: retq +; ALL-LABEL: test_add_v4i32: +; ALL: # BB#0: +; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; ALL-NEXT: retq %ret = add <4 x i32> %arg1, %arg2 ret <4 x i32> %ret } define <2 x i64> @test_add_v2i64(<2 x i64> %arg1, <2 x i64> %arg2) { -; SKX-LABEL: test_add_v2i64: -; SKX: # BB#0: -; SKX-NEXT: vpaddq %xmm1, %xmm0, %xmm0 -; SKX-NEXT: retq +; ALL-LABEL: test_add_v2i64: +; ALL: # BB#0: +; ALL-NEXT: vpaddq %xmm1, %xmm0, %xmm0 +; ALL-NEXT: retq %ret = add <2 x i64> %arg1, %arg2 ret <2 x i64> %ret } @@ -42,6 +45,20 @@ ; SKX: # BB#0: ; SKX-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; SKX-NEXT: retq +; +; AVX2-LABEL: test_add_v32i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq +; +; AVX1-LABEL: test_add_v32i8: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpaddb %xmm3, %xmm2, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq %ret = add <32 x i8> %arg1, %arg2 ret <32 x i8> %ret } @@ -51,6 +68,20 @@ ; SKX: # BB#0: ; SKX-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; SKX-NEXT: retq +; +; AVX2-LABEL: test_add_v16i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq +; +; AVX1-LABEL: test_add_v16i16: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpaddw %xmm3, %xmm2, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq %ret = add <16 x i16> %arg1, %arg2 ret <16 x i16> %ret } @@ -60,6 +91,20 @@ ; SKX: # BB#0: ; SKX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; SKX-NEXT: retq +; +; AVX2-LABEL: test_add_v8i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq +; +; AVX1-LABEL: test_add_v8i32: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpaddd %xmm3, %xmm2, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq %ret = add <8 x i32> %arg1, %arg2 ret <8 x i32> %ret } @@ -69,6 +114,20 @@ ; SKX: # BB#0: ; SKX-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; SKX-NEXT: retq +; +; AVX2-LABEL: test_add_v4i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq +; +; AVX1-LABEL: test_add_v4i64: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpaddq %xmm3, %xmm2, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq %ret = add <4 x i64> %arg1, %arg2 ret <4 x i64> %ret } @@ -78,6 +137,26 @@ ; SKX: # BB#0: ; SKX-NEXT: vpaddb %zmm1, %zmm0, %zmm0 ; SKX-NEXT: retq +; +; AVX2-LABEL: test_add_v64i8: +; AVX2: # BB#0: +; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1 +; AVX2-NEXT: retq +; +; AVX1-LABEL: test_add_v64i8: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6 +; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm7 +; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpaddb %xmm6, %xmm4, %xmm2 +; AVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpaddb %xmm7, %xmm5, %xmm3 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 +; AVX1-NEXT: retq %ret = add <64 x i8> %arg1, %arg2 ret <64 x i8> %ret } @@ -87,6 +166,26 @@ ; SKX: # BB#0: ; SKX-NEXT: vpaddw %zmm1, %zmm0, %zmm0 ; SKX-NEXT: retq +; +; AVX2-LABEL: test_add_v32i16: +; AVX2: # BB#0: +; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1 +; AVX2-NEXT: retq +; +; AVX1-LABEL: test_add_v32i16: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6 +; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm7 +; AVX1-NEXT: vpaddw %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpaddw %xmm6, %xmm4, %xmm2 +; AVX1-NEXT: vpaddw %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpaddw %xmm7, %xmm5, %xmm3 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 +; AVX1-NEXT: retq %ret = add <32 x i16> %arg1, %arg2 ret <32 x i16> %ret } @@ -96,6 +195,26 @@ ; SKX: # BB#0: ; SKX-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; SKX-NEXT: retq +; +; AVX2-LABEL: test_add_v16i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1 +; AVX2-NEXT: retq +; +; AVX1-LABEL: test_add_v16i32: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6 +; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm7 +; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpaddd %xmm6, %xmm4, %xmm2 +; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpaddd %xmm7, %xmm5, %xmm3 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 +; AVX1-NEXT: retq %ret = add <16 x i32> %arg1, %arg2 ret <16 x i32> %ret } @@ -105,6 +224,26 @@ ; SKX: # BB#0: ; SKX-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; SKX-NEXT: retq +; +; AVX2-LABEL: test_add_v8i64: +; AVX2: # BB#0: +; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1 +; AVX2-NEXT: retq +; +; AVX1-LABEL: test_add_v8i64: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6 +; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm7 +; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpaddq %xmm6, %xmm4, %xmm2 +; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpaddq %xmm7, %xmm5, %xmm3 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 +; AVX1-NEXT: retq %ret = add <8 x i64> %arg1, %arg2 ret <8 x i64> %ret } Index: test/CodeGen/X86/GlobalISel/select-extract-vec256.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/select-extract-vec256.mir @@ -0,0 +1,80 @@ +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL + +--- | + define void @test_extract_128_idx0() { + ret void + } + + define void @test_extract_128_idx1() { + ret void + } + +... +--- +name: test_extract_128_idx0 +# ALL-LABEL: name: test_extract_128_idx0 +alignment: 4 +legalized: true +regBankSelected: true +# AVX: registers: +# AVX-NEXT: - { id: 0, class: vr256 } +# AVX-NEXT: - { id: 1, class: vr128 } +# +# AVX512VL: registers: +# AVX512VL-NEXT: - { id: 0, class: vr256x } +# AVX512VL-NEXT: - { id: 1, class: vr128x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } +# ALL: %0 = COPY %ymm1 +# ALL-NEXT: %1 = COPY %0.sub_xmm +# ALL-NEXT: %xmm0 = COPY %1 +# ALL-NEXT: RET 0, implicit %xmm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm1 + + %0(<8 x s32>) = COPY %ymm1 + %1(<4 x s32>) = G_EXTRACT %0(<8 x s32>), 0 + %xmm0 = COPY %1(<4 x s32>) + RET 0, implicit %xmm0 + +... +--- +name: test_extract_128_idx1 +# ALL-LABEL: name: test_extract_128_idx1 +alignment: 4 +legalized: true +regBankSelected: true +# AVX: registers: +# AVX-NEXT: - { id: 0, class: vr256 } +# AVX-NEXT: - { id: 1, class: vr128 } +# +# AVX512VL: registers: +# AVX512VL-NEXT: - { id: 0, class: vr256x } +# AVX512VL-NEXT: - { id: 1, class: vr128x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } +# AVX: %0 = COPY %ymm1 +# AVX-NEXT: %1 = VEXTRACTF128rr %0, 1 +# AVX-NEXT: %xmm0 = COPY %1 +# AVX-NEXT: RET 0, implicit %xmm0 +# +# AVX512VL: %0 = COPY %ymm1 +# AVX512VL-NEXT: %1 = VEXTRACTF32x4Z256rr %0, 1 +# AVX512VL-NEXT: %xmm0 = COPY %1 +# AVX512VL-NEXT: RET 0, implicit %xmm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm1 + + %0(<8 x s32>) = COPY %ymm1 + %1(<4 x s32>) = G_EXTRACT %0(<8 x s32>), 128 + %xmm0 = COPY %1(<4 x s32>) + RET 0, implicit %xmm0 + +... + + Index: test/CodeGen/X86/GlobalISel/select-extract-vec512.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/select-extract-vec512.mir @@ -0,0 +1,127 @@ +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL + +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL + +--- | + define void @test_extract_128_idx0() { + ret void + } + + define void @test_extract_128_idx1() { + ret void + } + + define void @test_extract_256_idx0() { + ret void + } + + define void @test_extract_256_idx1() { + ret void + } + +... +--- +name: test_extract_128_idx0 +# ALL-LABEL: name: test_extract_128_idx0 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr128x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } +# ALL: %0 = COPY %zmm1 +# ALL-NEXT: %1 = COPY %0.sub_xmm +# ALL-NEXT: %xmm0 = COPY %1 +# ALL-NEXT: RET 0, implicit %xmm0 +body: | + bb.1 (%ir-block.0): + liveins: %zmm1 + + %0(<16 x s32>) = COPY %zmm1 + %1(<4 x s32>) = G_EXTRACT %0(<16 x s32>), 0 + %xmm0 = COPY %1(<4 x s32>) + RET 0, implicit %xmm0 + +... +--- +name: test_extract_128_idx1 +# ALL-LABEL: name: test_extract_128_idx1 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr128x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } +# ALL: %0 = COPY %zmm1 +# ALL-NEXT: %1 = VEXTRACTF32x4Zrr %0, 1 +# ALL-NEXT: %xmm0 = COPY %1 +# ALL-NEXT: RET 0, implicit %xmm0 +body: | + bb.1 (%ir-block.0): + liveins: %zmm1 + + %0(<16 x s32>) = COPY %zmm1 + %1(<4 x s32>) = G_EXTRACT %0(<16 x s32>), 128 + %xmm0 = COPY %1(<4 x s32>) + RET 0, implicit %xmm0 + +... +--- +name: test_extract_256_idx0 +# ALL-LABEL: name: test_extract_256_idx0 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr256x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } +# ALL: %0 = COPY %zmm1 +# ALL-NEXT: %1 = COPY %0.sub_ymm +# ALL-NEXT: %ymm0 = COPY %1 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %zmm1 + + %0(<16 x s32>) = COPY %zmm1 + %1(<8 x s32>) = G_EXTRACT %0(<16 x s32>), 0 + %ymm0 = COPY %1(<8 x s32>) + RET 0, implicit %ymm0 + +... +--- +name: test_extract_256_idx1 +# ALL-LABEL: name: test_extract_256_idx1 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr256x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } +# ALL: %0 = COPY %zmm1 +# ALL-NEXT: %1 = VEXTRACTF64x4Zrr %0, 1 +# ALL-NEXT: %ymm0 = COPY %1 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %zmm1 + + %0(<16 x s32>) = COPY %zmm1 + %1(<8 x s32>) = G_EXTRACT %0(<16 x s32>), 256 + %ymm0 = COPY %1(<8 x s32>) + RET 0, implicit %ymm0 + +... + Index: test/CodeGen/X86/GlobalISel/select-insert-vec256.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/select-insert-vec256.mir @@ -0,0 +1,176 @@ +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL +--- | + define void @test_insert_128_idx0() { + ret void + } + + define void @test_insert_128_idx0_undef() { + ret void + } + + define void @test_insert_128_idx1() { + ret void + } + + define void @test_insert_128_idx1_undef() { + ret void + } + +... +--- +name: test_insert_128_idx0 +# ALL-LABEL: name: test_insert_128_idx0 +alignment: 4 +legalized: true +regBankSelected: true +# AVX: registers: +# AVX-NEXT: - { id: 0, class: vr256 } +# AVX-NEXT: - { id: 1, class: vr128 } +# AVX-NEXT: - { id: 2, class: vr256 } +# +# AVX512VL: registers: +# AVX512VL-NEXT: - { id: 0, class: vr256x } +# AVX512VL-NEXT: - { id: 1, class: vr128x } +# AVX512VL-NEXT: - { id: 2, class: vr256x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# AVX: %0 = COPY %ymm0 +# AVX-NEXT: %1 = COPY %xmm1 +# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 0 +# AVX-NEXT: %ymm0 = COPY %2 +# AVX-NEXT: RET 0, implicit %ymm0 +# +# AVX512VL: %0 = COPY %ymm0 +# AVX512VL-NEXT: %1 = COPY %xmm1 +# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 0 +# AVX512VL-NEXT: %ymm0 = COPY %2 +# AVX512VL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm0, %ymm1 + + %0(<8 x s32>) = COPY %ymm0 + %1(<4 x s32>) = COPY %xmm1 + %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0 + %ymm0 = COPY %2(<8 x s32>) + RET 0, implicit %ymm0 + +... +--- +name: test_insert_128_idx0_undef +# ALL-LABEL: name: test_insert_128_idx0_undef +alignment: 4 +legalized: true +regBankSelected: true +# AVX: registers: +# AVX-NEXT: - { id: 0, class: vecr } +# AVX-NEXT: - { id: 1, class: vr128 } +# AVX-NEXT: - { id: 2, class: vr256 } +# +# AVX512VL: registers: +# AVX512VL-NEXT: - { id: 0, class: vecr } +# AVX512VL-NEXT: - { id: 1, class: vr128x } +# AVX512VL-NEXT: - { id: 2, class: vr256x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# ALL: %1 = COPY %xmm1 +# ALL-NEXT: undef %2.sub_xmm = COPY %1 +# ALL-NEXT: %ymm0 = COPY %2 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm0, %ymm1 + + %0(<8 x s32>) = IMPLICIT_DEF + %1(<4 x s32>) = COPY %xmm1 + %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0 + %ymm0 = COPY %2(<8 x s32>) + RET 0, implicit %ymm0 + +... +--- +name: test_insert_128_idx1 +# ALL-LABEL: name: test_insert_128_idx1 +alignment: 4 +legalized: true +regBankSelected: true +# AVX: registers: +# AVX-NEXT: - { id: 0, class: vr256 } +# AVX-NEXT: - { id: 1, class: vr128 } +# AVX-NEXT: - { id: 2, class: vr256 } +# +# AVX512VL: registers: +# AVX512VL-NEXT: - { id: 0, class: vr256x } +# AVX512VL-NEXT: - { id: 1, class: vr128x } +# AVX512VL-NEXT: - { id: 2, class: vr256x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# AVX: %0 = COPY %ymm0 +# AVX-NEXT: %1 = COPY %xmm1 +# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 1 +# AVX-NEXT: %ymm0 = COPY %2 +# AVX-NEXT: RET 0, implicit %ymm0 +# +# AVX512VL: %0 = COPY %ymm0 +# AVX512VL-NEXT: %1 = COPY %xmm1 +# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 1 +# AVX512VL-NEXT: %ymm0 = COPY %2 +# AVX512VL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm0, %ymm1 + + %0(<8 x s32>) = COPY %ymm0 + %1(<4 x s32>) = COPY %xmm1 + %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128 + %ymm0 = COPY %2(<8 x s32>) + RET 0, implicit %ymm0 +... +--- +name: test_insert_128_idx1_undef +# ALL-LABEL: name: test_insert_128_idx1_undef +alignment: 4 +legalized: true +regBankSelected: true +# AVX: registers: +# AVX-NEXT: - { id: 0, class: vr256 } +# AVX-NEXT: - { id: 1, class: vr128 } +# AVX-NEXT: - { id: 2, class: vr256 } +# +# AVX512VL: registers: +# AVX512VL-NEXT: - { id: 0, class: vr256x } +# AVX512VL-NEXT: - { id: 1, class: vr128x } +# AVX512VL-NEXT: - { id: 2, class: vr256x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# AVX: %0 = IMPLICIT_DEF +# AVX-NEXT: %1 = COPY %xmm1 +# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 1 +# AVX-NEXT: %ymm0 = COPY %2 +# AVX-NEXT: RET 0, implicit %ymm0 +# +# AVX512VL: %0 = IMPLICIT_DEF +# AVX512VL-NEXT: %1 = COPY %xmm1 +# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 1 +# AVX512VL-NEXT: %ymm0 = COPY %2 +# AVX512VL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm0, %ymm1 + + %0(<8 x s32>) = IMPLICIT_DEF + %1(<4 x s32>) = COPY %xmm1 + %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128 + %ymm0 = COPY %2(<8 x s32>) + RET 0, implicit %ymm0 +... + Index: test/CodeGen/X86/GlobalISel/select-insert-vec512.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/select-insert-vec512.mir @@ -0,0 +1,271 @@ +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL + +--- | + define void @test_insert_128_idx0() { + ret void + } + + define void @test_insert_128_idx0_undef() { + ret void + } + + define void @test_insert_128_idx1() { + ret void + } + + define void @test_insert_128_idx1_undef() { + ret void + } + + define void @test_insert_256_idx0() { + ret void + } + + define void @test_insert_256_idx0_undef() { + ret void + } + + define void @test_insert_256_idx1() { + ret void + } + + define void @test_insert_256_idx1_undef() { + ret void + } + +... +--- +name: test_insert_128_idx0 +# ALL-LABEL: name: test_insert_128_idx0 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr128x } +# ALL-NEXT: - { id: 2, class: vr512 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# ALL: %0 = COPY %zmm0 +# ALL-NEXT: %1 = COPY %xmm1 +# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 0 +# ALL-NEXT: %ymm0 = COPY %2 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %zmm0, %ymm1 + + %0(<16 x s32>) = COPY %zmm0 + %1(<4 x s32>) = COPY %xmm1 + %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0 + %ymm0 = COPY %2(<16 x s32>) + RET 0, implicit %ymm0 + +... +--- +name: test_insert_128_idx0_undef +# ALL-LABEL: name: test_insert_128_idx0_undef +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vecr } +# ALL-NEXT: - { id: 1, class: vr128x } +# ALL-NEXT: - { id: 2, class: vr512 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# ALL: %1 = COPY %xmm1 +# ALL-NEXT: undef %2.sub_xmm = COPY %1 +# ALL-NEXT: %ymm0 = COPY %2 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm0, %ymm1 + + %0(<16 x s32>) = IMPLICIT_DEF + %1(<4 x s32>) = COPY %xmm1 + %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0 + %ymm0 = COPY %2(<16 x s32>) + RET 0, implicit %ymm0 + +... +--- +name: test_insert_128_idx1 +# ALL-LABEL: name: test_insert_128_idx1 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr128x } +# ALL-NEXT: - { id: 2, class: vr512 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# ALL: %0 = COPY %zmm0 +# ALL-NEXT: %1 = COPY %xmm1 +# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 1 +# ALL-NEXT: %ymm0 = COPY %2 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm0, %ymm1 + + %0(<16 x s32>) = COPY %zmm0 + %1(<4 x s32>) = COPY %xmm1 + %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128 + %ymm0 = COPY %2(<16 x s32>) + RET 0, implicit %ymm0 +... +--- +name: test_insert_128_idx1_undef +# ALL-LABEL: name: test_insert_128_idx1_undef +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr128x } +# ALL-NEXT: - { id: 2, class: vr512 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# ALL: %0 = IMPLICIT_DEF +# ALL-NEXT: %1 = COPY %xmm1 +# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 1 +# ALL-NEXT: %ymm0 = COPY %2 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm0, %ymm1 + + %0(<16 x s32>) = IMPLICIT_DEF + %1(<4 x s32>) = COPY %xmm1 + %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128 + %ymm0 = COPY %2(<16 x s32>) + RET 0, implicit %ymm0 +... +--- +name: test_insert_256_idx0 +# ALL-LABEL: name: test_insert_256_idx0 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr256x } +# ALL-NEXT: - { id: 2, class: vr512 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# ALL: %0 = COPY %zmm0 +# ALL-NEXT: %1 = COPY %ymm1 +# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 0 +# ALL-NEXT: %ymm0 = COPY %2 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %zmm0, %ymm1 + + %0(<16 x s32>) = COPY %zmm0 + %1(<8 x s32>) = COPY %ymm1 + %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0 + %ymm0 = COPY %2(<16 x s32>) + RET 0, implicit %ymm0 + +... +--- +name: test_insert_256_idx0_undef +# ALL-LABEL: name: test_insert_256_idx0_undef +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vecr } +# ALL-NEXT: - { id: 1, class: vr256x } +# ALL-NEXT: - { id: 2, class: vr512 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# ALL: %1 = COPY %ymm1 +# ALL-NEXT: undef %2.sub_ymm = COPY %1 +# ALL-NEXT: %ymm0 = COPY %2 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm0, %ymm1 + + %0(<16 x s32>) = IMPLICIT_DEF + %1(<8 x s32>) = COPY %ymm1 + %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0 + %ymm0 = COPY %2(<16 x s32>) + RET 0, implicit %ymm0 + +... +--- +name: test_insert_256_idx1 +# ALL-LABEL: name: test_insert_256_idx1 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr256x } +# ALL-NEXT: - { id: 2, class: vr512 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# ALL: %0 = COPY %zmm0 +# ALL-NEXT: %1 = COPY %ymm1 +# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 1 +# ALL-NEXT: %ymm0 = COPY %2 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm0, %ymm1 + + %0(<16 x s32>) = COPY %zmm0 + %1(<8 x s32>) = COPY %ymm1 + %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256 + %ymm0 = COPY %2(<16 x s32>) + RET 0, implicit %ymm0 +... +--- +name: test_insert_256_idx1_undef +# ALL-LABEL: name: test_insert_256_idx1_undef +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr256x } +# ALL-NEXT: - { id: 2, class: vr512 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# ALL: %0 = IMPLICIT_DEF +# ALL-NEXT: %1 = COPY %ymm1 +# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 1 +# ALL-NEXT: %ymm0 = COPY %2 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %ymm0, %ymm1 + + %0(<16 x s32>) = IMPLICIT_DEF + %1(<8 x s32>) = COPY %ymm1 + %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256 + %ymm0 = COPY %2(<16 x s32>) + RET 0, implicit %ymm0 +... + Index: test/CodeGen/X86/GlobalISel/select-memop-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-memop-scalar.mir +++ test/CodeGen/X86/GlobalISel/select-memop-scalar.mir @@ -340,10 +340,16 @@ alignment: 4 legalized: true regBankSelected: true +# NO_AVX512F: registers: +# NO_AVX512F-NEXT: - { id: 0, class: fr32 } +# NO_AVX512F-NEXT: - { id: 1, class: gr64 } +# NO_AVX512F-NEXT: - { id: 2, class: gr32 } +# +# AVX512ALL: registers: +# AVX512ALL-NEXT: - { id: 0, class: fr32x } +# AVX512ALL-NEXT: - { id: 1, class: gr64 } +# AVX512ALL-NEXT: - { id: 2, class: gr32 } registers: -# ALL: - { id: 0, class: fr32x } -# ALL: - { id: 1, class: gr64 } -# ALL: - { id: 2, class: gr32 } - { id: 0, class: vecr } - { id: 1, class: gpr } - { id: 2, class: gpr } @@ -399,10 +405,16 @@ alignment: 4 legalized: true regBankSelected: true +# NO_AVX512F: registers: +# NO_AVX512F-NEXT: - { id: 0, class: fr64 } +# NO_AVX512F-NEXT: - { id: 1, class: gr64 } +# NO_AVX512F-NEXT: - { id: 2, class: gr64 } +# +# AVX512ALL: registers: +# AVX512ALL-NEXT: - { id: 0, class: fr64x } +# AVX512ALL-NEXT: - { id: 1, class: gr64 } +# AVX512ALL-NEXT: - { id: 2, class: gr64 } registers: -# ALL: - { id: 0, class: fr64x } -# ALL: - { id: 1, class: gr64 } -# ALL: - { id: 2, class: gr64 } - { id: 0, class: vecr } - { id: 1, class: gpr } - { id: 2, class: gpr } Index: test/CodeGen/X86/GlobalISel/select-merge-vec256.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/select-merge-vec256.mir @@ -0,0 +1,101 @@ +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512VL +--- | + define void @test_merge() { + ret void + } + + define void @test_unmerge() { + ret void + } + +... +--- +name: test_merge +# AVX-LABEL: name: test_merge +# +# AVX512VL-LABEL: name: test_merge +alignment: 4 +legalized: true +regBankSelected: true +# AVX: registers: +# AVX-NEXT: - { id: 0, class: vr128 } +# AVX-NEXT: - { id: 1, class: vr256 } +# AVX-NEXT: - { id: 2, class: vr256 } +# AVX-NEXT: - { id: 3, class: vr256 } +# +# AVX512VL: registers: +# AVX512VL-NEXT: - { id: 0, class: vr128x } +# AVX512VL-NEXT: - { id: 1, class: vr256x } +# AVX512VL-NEXT: - { id: 2, class: vr256x } +# AVX512VL-NEXT: - { id: 3, class: vr256x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } +# AVX: %0 = IMPLICIT_DEF +# AVX-NEXT: undef %2.sub_xmm = COPY %0 +# AVX-NEXT: %3 = VINSERTF128rr %2, %0, 1 +# AVX-NEXT: %1 = COPY %3 +# AVX-NEXT: %ymm0 = COPY %1 +# AVX-NEXT: RET 0, implicit %ymm0 +# +# AVX512VL: %0 = IMPLICIT_DEF +# AVX512VL-NEXT: undef %2.sub_xmm = COPY %0 +# AVX512VL-NEXT: %3 = VINSERTF32x4Z256rr %2, %0, 1 +# AVX512VL-NEXT: %1 = COPY %3 +# AVX512VL-NEXT: %ymm0 = COPY %1 +# AVX512VL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + + %0(<4 x s32>) = IMPLICIT_DEF + %1(<8 x s32>) = G_MERGE_VALUES %0(<4 x s32>), %0(<4 x s32>) + %ymm0 = COPY %1(<8 x s32>) + RET 0, implicit %ymm0 + +... +--- +name: test_unmerge +# AVX-LABEL: name: test_unmerge +# +# AVX512VL-LABEL: name: test_unmerge +alignment: 4 +legalized: true +regBankSelected: true +# AVX: registers: +# AVX-NEXT: - { id: 0, class: vr256 } +# AVX-NEXT: - { id: 1, class: vr128 } +# AVX-NEXT: - { id: 2, class: vr128 } +# +# AVX512VL: registers: +# AVX512VL-NEXT: - { id: 0, class: vr256x } +# AVX512VL-NEXT: - { id: 1, class: vr128x } +# AVX512VL-NEXT: - { id: 2, class: vr128x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# AVX: %0 = IMPLICIT_DEF +# AVX-NEXT: %1 = COPY %0.sub_xmm +# AVX-NEXT: %2 = VEXTRACTF128rr %0, 1 +# AVX-NEXT: %xmm0 = COPY %1 +# AVX-NEXT: %xmm1 = COPY %2 +# AVX-NEXT: RET 0, implicit %xmm0, implicit %xmm1 +# +# AVX512VL: %0 = IMPLICIT_DEF +# AVX512VL-NEXT: %1 = COPY %0.sub_xmm +# AVX512VL-NEXT: %2 = VEXTRACTF32x4Z256rr %0, 1 +# AVX512VL-NEXT: %xmm0 = COPY %1 +# AVX512VL-NEXT: %xmm1 = COPY %2 +# AVX512VL-NEXT: RET 0, implicit %xmm0, implicit %xmm1 +body: | + bb.1 (%ir-block.0): + + %0(<8 x s32>) = IMPLICIT_DEF + %1(<4 x s32>), %2(<4 x s32>) = G_UNMERGE_VALUES %0(<8 x s32>) + %xmm0 = COPY %1(<4 x s32>) + %xmm1 = COPY %2(<4 x s32>) + RET 0, implicit %xmm0, implicit %xmm1 + +... + Index: test/CodeGen/X86/GlobalISel/select-merge-vec512.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/select-merge-vec512.mir @@ -0,0 +1,144 @@ +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL +--- | + define void @test_merge_v128() { + ret void + } + + define void @test_merge_v256() { + ret void + } + + define void @test_unmerge_v128() { + ret void + } + + define void @test_unmerge_v256() { + ret void + } + +... +--- +name: test_merge_v128 +# ALL-LABEL: name: test_merge_v128 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr128x } +# ALL-NEXT: - { id: 1, class: vr512 } +# ALL-NEXT: - { id: 2, class: vr512 } +# ALL-NEXT: - { id: 3, class: vr512 } +# ALL-NEXT: - { id: 4, class: vr512 } +# ALL-NEXT: - { id: 5, class: vr512 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } +# ALL: %0 = IMPLICIT_DEF +# ALL-NEXT: undef %2.sub_xmm = COPY %0 +# ALL-NEXT: %3 = VINSERTF32x4Zrr %2, %0, 1 +# ALL-NEXT: %4 = VINSERTF32x4Zrr %3, %0, 2 +# ALL-NEXT: %5 = VINSERTF32x4Zrr %4, %0, 3 +# ALL-NEXT: %1 = COPY %5 +# ALL-NEXT: %zmm0 = COPY %1 +# ALL-NEXT: RET 0, implicit %zmm0 +body: | + bb.1 (%ir-block.0): + + %0(<4 x s32>) = IMPLICIT_DEF + %1(<16 x s32>) = G_MERGE_VALUES %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>) + %zmm0 = COPY %1(<16 x s32>) + RET 0, implicit %zmm0 + +... +--- +name: test_merge_v256 +# ALL-LABEL: name: test_merge_v256 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr256x } +# ALL-NEXT: - { id: 1, class: vr512 } +# ALL-NEXT: - { id: 2, class: vr512 } +# ALL-NEXT: - { id: 3, class: vr512 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } +# ALL: %0 = IMPLICIT_DEF +# ALL-NEXT: undef %2.sub_ymm = COPY %0 +# ALL-NEXT: %3 = VINSERTF64x4Zrr %2, %0, 1 +# ALL-NEXT: %1 = COPY %3 +# ALL-NEXT: %zmm0 = COPY %1 +# ALL-NEXT: RET 0, implicit %zmm0 +body: | + bb.1 (%ir-block.0): + + %0(<8 x s32>) = IMPLICIT_DEF + %1(<16 x s32>) = G_MERGE_VALUES %0(<8 x s32>), %0(<8 x s32>) + %zmm0 = COPY %1(<16 x s32>) + RET 0, implicit %zmm0 + +... +--- +name: test_unmerge_v128 +# ALL-LABEL: name: test_unmerge_v128 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr128x } +# ALL-NEXT: - { id: 2, class: vr128x } +# ALL-NEXT: - { id: 3, class: vr128x } +# ALL-NEXT: - { id: 4, class: vr128x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } + - { id: 3, class: vecr } + - { id: 4, class: vecr } +# ALL: %0 = IMPLICIT_DEF +# ALL-NEXT: %1 = COPY %0.sub_xmm +# ALL-NEXT: %2 = VEXTRACTF32x4Zrr %0, 1 +# ALL-NEXT: %3 = VEXTRACTF32x4Zrr %0, 2 +# ALL-NEXT: %4 = VEXTRACTF32x4Zrr %0, 3 +# ALL-NEXT: %xmm0 = COPY %1 +# ALL-NEXT: RET 0, implicit %xmm0 +body: | + bb.1 (%ir-block.0): + + %0(<16 x s32>) = IMPLICIT_DEF + %1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>), %4(<4 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>) + %xmm0 = COPY %1(<4 x s32>) + RET 0, implicit %xmm0 + +... +--- +name: test_unmerge_v256 +# ALL-LABEL: name: test_unmerge_v256 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: vr512 } +# ALL-NEXT: - { id: 1, class: vr256x } +# ALL-NEXT: - { id: 2, class: vr256x } +registers: + - { id: 0, class: vecr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +# ALL: %0 = IMPLICIT_DEF +# ALL-NEXT: %1 = COPY %0.sub_ymm +# ALL-NEXT: %2 = VEXTRACTF64x4Zrr %0, 1 +# ALL-NEXT: %xmm0 = COPY %1 +# ALL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + + %0(<16 x s32>) = IMPLICIT_DEF + %1(<8 x s32>), %2(<8 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>) + %xmm0 = COPY %1(<8 x s32>) + RET 0, implicit %ymm0 + +... +