Index: include/llvm/CodeGen/GlobalISel/InstructionSelector.h =================================================================== --- include/llvm/CodeGen/GlobalISel/InstructionSelector.h +++ include/llvm/CodeGen/GlobalISel/InstructionSelector.h @@ -29,6 +29,7 @@ class MachineRegisterInfo; class RegisterBankInfo; class TargetInstrInfo; +class TargetRegisterClass; class TargetRegisterInfo; /// Container class for CodeGen predicate results. @@ -79,6 +80,12 @@ InstructionSelector(); + bool constrainOperandRegToRegClass(MachineInstr &I, unsigned OpIdx, + const TargetRegisterClass *RC, + const TargetInstrInfo &TII, + const TargetRegisterInfo &TRI, + const RegisterBankInfo &RBI) const; + /// Mutate the newly-selected instruction \p I to constrain its (possibly /// generic) virtual register operands to the instruction's register class. /// This could involve inserting COPYs before (for uses) or after (for defs). Index: include/llvm/CodeGen/GlobalISel/Utils.h =================================================================== --- include/llvm/CodeGen/GlobalISel/Utils.h +++ include/llvm/CodeGen/GlobalISel/Utils.h @@ -29,9 +29,16 @@ class TargetInstrInfo; class TargetPassConfig; class TargetRegisterInfo; +class TargetRegisterClass; class Twine; class ConstantFP; +unsigned constrainRegToClass(MachineRegisterInfo &MRI, + const TargetInstrInfo &TII, + const RegisterBankInfo &RBI, + MachineInstr &InsertPt, unsigned Reg, + const TargetRegisterClass *RegClass); + /// Try to constrain Reg so that it is usable by argument OpIdx of the /// provided MCInstrDesc \p II. If this fails, create a new virtual /// register in the correct class and insert a COPY before \p InsertPt. Index: lib/CodeGen/GlobalISel/InstructionSelector.cpp =================================================================== --- lib/CodeGen/GlobalISel/InstructionSelector.cpp +++ lib/CodeGen/GlobalISel/InstructionSelector.cpp @@ -25,6 +25,18 @@ InstructionSelector::InstructionSelector() {} +bool InstructionSelector::constrainOperandRegToRegClass( + MachineInstr &I, unsigned OpIdx, const TargetRegisterClass *RC, + const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, + const RegisterBankInfo &RBI) const { + MachineBasicBlock &MBB = *I.getParent(); + MachineFunction &MF = *MBB.getParent(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + + return llvm::constrainRegToClass(MRI, TII, RBI, I, + I.getOperand(OpIdx).getReg(), RC); +} + bool InstructionSelector::constrainSelectedInstRegOperands( MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const { Index: lib/CodeGen/GlobalISel/Utils.cpp =================================================================== --- lib/CodeGen/GlobalISel/Utils.cpp +++ lib/CodeGen/GlobalISel/Utils.cpp @@ -26,6 +26,23 @@ using namespace llvm; +unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI, + const TargetInstrInfo &TII, + const RegisterBankInfo &RBI, + MachineInstr &InsertPt, unsigned Reg, + const TargetRegisterClass *RegClass) { + if (!RBI.constrainGenericRegister(Reg, *RegClass, MRI)) { + unsigned NewReg = MRI.createVirtualRegister(RegClass); + BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(), + TII.get(TargetOpcode::COPY), NewReg) + .addReg(Reg); + return NewReg; + } + + return Reg; +} + + unsigned llvm::constrainOperandRegClass( const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, @@ -36,16 +53,7 @@ "PhysReg not implemented"); const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); - - if (!RBI.constrainGenericRegister(Reg, *RegClass, MRI)) { - unsigned NewReg = MRI.createVirtualRegister(RegClass); - BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(), - TII.get(TargetOpcode::COPY), NewReg) - .addReg(Reg); - return NewReg; - } - - return Reg; + return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, RegClass); } bool llvm::isTriviallyDead(const MachineInstr &MI, Index: lib/Target/AArch64/AArch64InstructionSelector.cpp =================================================================== --- lib/Target/AArch64/AArch64InstructionSelector.cpp +++ lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -940,6 +940,9 @@ const LLT DstTy = MRI.getType(I.getOperand(0).getReg()); const LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); + if (DstTy == LLT::scalar(32) && SrcTy == LLT::scalar(64)) + llvm_unreachable("Tablegen code can import this"); + const unsigned DstReg = I.getOperand(0).getReg(); const unsigned SrcReg = I.getOperand(1).getReg(); Index: test/CodeGen/AArch64/GlobalISel/select-bitcast.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-bitcast.mir +++ test/CodeGen/AArch64/GlobalISel/select-bitcast.mir @@ -95,7 +95,7 @@ # CHECK: registers: # CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32all } +# CHECK-NEXT: - { id: 1, class: gpr32 } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } @@ -194,7 +194,7 @@ # CHECK: registers: # CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64all } +# CHECK-NEXT: - { id: 1, class: gpr64 } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } Index: test/CodeGen/AArch64/GlobalISel/select-trunc.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-trunc.mir +++ test/CodeGen/AArch64/GlobalISel/select-trunc.mir @@ -15,8 +15,8 @@ regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr32 } +# CHECK-NEXT: - { id: 0, class: gpr64all } +# CHECK-NEXT: - { id: 1, class: gpr32sp } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } Index: test/TableGen/GlobalISelEmitter.td =================================================================== --- test/TableGen/GlobalISelEmitter.td +++ test/TableGen/GlobalISelEmitter.td @@ -10,6 +10,8 @@ def R0 : Register<"r0"> { let Namespace = "MyTarget"; } def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>; def GPR32Op : RegisterOperand; +def F0 : Register<"f0"> { let Namespace = "MyTarget"; } +def FPR32 : RegisterClass<"MyTarget", [f32], 32, (add F0)>; class I Pat> : Instruction { @@ -462,6 +464,31 @@ def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>; def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>; +//===- Test a COPY_TO_REGCLASS --------------------------------------------===// +// + +// CHECK-LABEL: if ([&]() { +// CHECK-NEXT: MachineInstr &MI0 = I; +// CHECK-NEXT: if (MI0.getNumOperands() < 2) +// CHECK-NEXT: return false; +// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_BITCAST) && +// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) && +// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) && +// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) && +// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::FPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI)))))) +// CHECK-NEXT: // (bitconvert:i32 FPR32:f32:$src1) => (COPY_TO_REGCLASS:i32 FPR32:f32:$src1, GPR32:i32) +// CHECK-NEXT: I.setDesc(TII.get(TargetOpcode::COPY)); +// CHECK-NEXT: MachineInstr &NewI = I; +// CHECK-NEXT: constrainOperandRegToRegClass(NewI, 0, &MyTarget::GPR32RegClass, TII, TRI, RBI); +// CHECK-NEXT: return true; +// CHECK-NEXT: } +// CHECK-NEXT: return false; +// CHECK-NEXT: }()) { return true; } + +// The -6 is just to distinguish it from the other 'not' cases. +def : Pat<(i32 (bitconvert FPR32:$src1)), + (COPY_TO_REGCLASS FPR32:$src1, GPR32)>; + //===- Test a pattern with an MBB operand. --------------------------------===// // CHECK-LABEL: if ([&]() { Index: utils/TableGen/CodeGenRegisters.h =================================================================== --- utils/TableGen/CodeGenRegisters.h +++ utils/TableGen/CodeGenRegisters.h @@ -329,6 +329,9 @@ const std::string &getName() const { return Name; } std::string getQualifiedName() const; ArrayRef getValueTypes() const {return VTs;} + bool hasValueType(MVT::SimpleValueType VT) const { + return std::find(VTs.begin(), VTs.end(), VT) != VTs.end(); + } unsigned getNumValueTypes() const { return VTs.size(); } MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const { @@ -360,6 +363,16 @@ return SubClassWithSubReg.lookup(SubIdx); } + /// Find largest subclass where all registers have SubIdx subregisters in + /// SubRegClass and the largest subregister class that contains those + /// subregisters without (as far as possible) also containing additional registers. + /// + /// This can be used to find a suitable pair of classes for subregister copies. + CodeGenRegisterClass * + getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank, + const CodeGenSubRegIndex *SubIdx, + CodeGenRegisterClass **SubRegClass) const; + void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, CodeGenRegisterClass *SubRC) { SubClassWithSubReg[SubIdx] = SubRC; @@ -370,7 +383,7 @@ void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, BitVector &Out) const; - // addSuperRegClass - Add a class containing only SudIdx super-registers. + // addSuperRegClass - Add a class containing only SubIdx super-registers. void addSuperRegClass(CodeGenSubRegIndex *SubIdx, CodeGenRegisterClass *SuperRC) { SuperRegClasses[SubIdx].insert(SuperRC); Index: utils/TableGen/CodeGenRegisters.cpp =================================================================== --- utils/TableGen/CodeGenRegisters.cpp +++ utils/TableGen/CodeGenRegisters.cpp @@ -920,6 +920,83 @@ RC.inheritProperties(RegBank); } +CodeGenRegisterClass *CodeGenRegisterClass::getMatchingSubClassWithSubRegs( + CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx, + CodeGenRegisterClass **SubRegRC) const { + auto SizeOrder = [](const CodeGenRegisterClass *A, + const CodeGenRegisterClass *B) { + return A->getMembers().size() >= B->getMembers().size(); + }; + + auto &RegClasses = RegBank.getRegClasses(); + + // Find all the subclasses of this one that fully support the sub-register + // index and order them by size. BiggestSuperRC should always be first. + CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx); + if (!BiggestSuperRegRC) + return nullptr; + BitVector SuperRegRCsBV = BiggestSuperRegRC->getSubClasses(); + std::vector SuperRegRCs; + for (auto &RC : RegClasses) + if (SuperRegRCsBV[RC.EnumValue]) + SuperRegRCs.emplace_back(&RC); + std::sort(SuperRegRCs.begin(), SuperRegRCs.end(), SizeOrder); + assert(SuperRegRCs.front() == BiggestSuperRegRC && "Biggest class wasn't first"); + + // Find all the subreg classes and order them by size too. + std::vector> SuperRegClasses; + for (auto &RC: RegClasses) { + BitVector SuperRegClassesBV(RegClasses.size()); + RC.getSuperRegClasses(SubIdx, SuperRegClassesBV); + if (SuperRegClassesBV.any()) + SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV)); + } + std::sort(SuperRegClasses.begin(), SuperRegClasses.end(), + [&](const std::pair &A, + const std::pair &B) { + return SizeOrder(A.first, B.first); + }); + + // Find the biggest subclass and subreg class such that R:subidx is in the + // subreg class for all R in subclass. + // + // For example: + // All registers in X86's GR64 have a sub_32bit subregister but no class + // exists that contains all the 32-bit subregisters because GR64 contains RIP + // but GR32 does not contain EIP. Instead, we constrain SuperRegRC to + // GR32_with_sub_8bit (which is identical to GR32_with_sub_32bit) and then, + // having excluded RIP, we are able to find a SubRegRC (GR32). + CodeGenRegisterClass *ChosenSuperRegClass = nullptr; + for (auto *SuperRegRC : SuperRegRCs) { + for (const auto &SuperRegClassPair : SuperRegClasses) { + const BitVector &SuperRegClassBV = SuperRegClassPair.second; + if (SuperRegClassBV[SuperRegRC->EnumValue]) { + *SubRegRC = SuperRegClassPair.first; + ChosenSuperRegClass = SuperRegRC; + + // If SubRegRC is bigger than SuperRegRC then there are members of + // SubRegRC that don't have super registers via SubIdx. Keep looking to + // find a better fit and fall back on this one if there isn't one. + // + // This is intended to prevent X86 from making odd choices such as + // picking LOW32_ADDR_ACCESS_RBP instead of GR32 in the example above. + // LOW32_ADDR_ACCESS_RBP is a valid choice but contains registers that + // aren't subregisters of SuperRegRC whereas GR32 has a direct 1:1 + // mapping. + if (SuperRegRC->getMembers().size() >= (*SubRegRC)->getMembers().size()) + return ChosenSuperRegClass; + } + } + + // If we found a fit but it wasn't quite ideal because SubRegRC had excess + // registers, then we're done. + if (ChosenSuperRegClass) + return ChosenSuperRegClass; + } + + return nullptr; +} + void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, BitVector &Out) const { auto FindI = SuperRegClasses.find(SubIdx); Index: utils/TableGen/GlobalISelEmitter.cpp =================================================================== --- utils/TableGen/GlobalISelEmitter.cpp +++ utils/TableGen/GlobalISelEmitter.cpp @@ -155,6 +155,16 @@ return failedImport(Explanation); } +static Record *getInitValueAsRegClass(Init *V) { + if (DefInit *VDefInit = dyn_cast(V)) { + if (VDefInit->getDef()->isSubClassOf("RegisterOperand")) + return VDefInit->getDef()->getValueAsDef("RegClass"); + if (VDefInit->getDef()->isSubClassOf("RegisterClass")) + return VDefInit->getDef(); + } + return nullptr; +} + //===- Matchers -----------------------------------------------------------===// class OperandMatcher; @@ -796,7 +806,13 @@ //===- Actions ------------------------------------------------------------===// class OperandRenderer { public: - enum RendererKind { OR_Copy, OR_Imm, OR_Register, OR_ComplexPattern }; + enum RendererKind { + OR_Copy, + OR_CopySubReg, + OR_Imm, + OR_Register, + OR_ComplexPattern + }; protected: RendererKind Kind; @@ -841,6 +857,42 @@ } }; +/// A CopySubRegRenderer emits code to copy a single register operand from an +/// existing instruction to the one being built and indicate that only a +/// subregister should be copied. +class CopySubRegRenderer : public OperandRenderer { +protected: + /// The matcher for the instruction that this operand is copied from. + /// This provides the facility for looking up an a operand by it's name so + /// that it can be used as a source for the instruction being built. + const InstructionMatcher &Matched; + /// The name of the operand. + const StringRef SymbolicName; + // The subregister to extract. + const CodeGenSubRegIndex *SubReg; + +public: + CopySubRegRenderer(const InstructionMatcher &Matched, StringRef SymbolicName, + const CodeGenSubRegIndex *SubReg) + : OperandRenderer(OR_CopySubReg), Matched(Matched), + SymbolicName(SymbolicName), SubReg(SubReg) {} + + static bool classof(const OperandRenderer *R) { + return R->getKind() == OR_CopySubReg; + } + + const StringRef getSymbolicName() const { return SymbolicName; } + + void emitCxxRenderStmts(raw_ostream &OS, RuleMatcher &Rule) const override { + const OperandMatcher &Operand = Matched.getOperand(SymbolicName); + StringRef InsnVarName = + Rule.getInsnVarName(Operand.getInstructionMatcher()); + std::string OperandExpr = Operand.getOperandExpr(InsnVarName); + OS << " MIB.addReg(" << OperandExpr << ".getReg() /*" << SymbolicName + << "*/, 0, " << SubReg->EnumValue << ");\n"; + } +}; + /// Adds a specific physical register to the instruction being built. /// This is typically useful for WZR/XZR on AArch64. class AddRegisterRenderer : public OperandRenderer { @@ -947,6 +999,7 @@ /// into the desired instruction when this is possible. class BuildMIAction : public MatchAction { private: + std::string Name; const CodeGenInstruction *I; const InstructionMatcher &Matched; std::vector> OperandRenderers; @@ -970,8 +1023,9 @@ } public: - BuildMIAction(const CodeGenInstruction *I, const InstructionMatcher &Matched) - : I(I), Matched(Matched) {} + BuildMIAction(const StringRef Name, const CodeGenInstruction *I, + const InstructionMatcher &Matched) + : Name(Name), I(I), Matched(Matched) {} template Kind &addRenderer(Args&&... args) { @@ -1006,7 +1060,7 @@ } } - OS << " MachineInstr &NewI = " << RecycleVarName << ";\n"; + OS << " MachineInstr &" << Name << " = " << RecycleVarName << ";\n"; return; } @@ -1024,7 +1078,38 @@ OS << " for (const auto &MMO : FromMI->memoperands())\n"; OS << " MIB.addMemOperand(MMO);\n"; OS << " " << RecycleVarName << ".eraseFromParent();\n"; - OS << " MachineInstr &NewI = *MIB;\n"; + OS << " MachineInstr &" << Name << " = *MIB;\n"; + } +}; + +class ConstrainOperandsToDefinitionAction : public MatchAction { +private: + std::string Name; + +public: + ConstrainOperandsToDefinitionAction(const StringRef Name) : Name(Name) {} + + void emitCxxActionStmts(raw_ostream &OS, RuleMatcher &Rule, + StringRef RecycleVarName) const override { + OS << " constrainSelectedInstRegOperands(" << Name << ", TII, TRI, RBI);\n"; + } +}; + +class ConstrainOperandToRegClassAction : public MatchAction { +private: + std::string Name; + unsigned OpIdx; + const CodeGenRegisterClass &RC; + +public: + ConstrainOperandToRegClassAction(const StringRef Name, unsigned OpIdx, + const CodeGenRegisterClass &RC) + : Name(Name), OpIdx(OpIdx), RC(RC) {} + + void emitCxxActionStmts(raw_ostream &OS, RuleMatcher &Rule, + StringRef RecycleVarName) const override { + OS << " constrainOperandRegToRegClass(" << Name << ", " << OpIdx + << ", &" << RC.getQualifiedName() << "RegClass, TII, TRI, RBI);\n"; } }; @@ -1172,7 +1257,6 @@ MA->emitCxxActionStmts(OS, *this, "I"); } - OS << " constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);\n"; OS << " return true;\n"; OS << " }\n"; OS << " return false;\n"; @@ -1215,6 +1299,7 @@ const RecordKeeper &RK; const CodeGenDAGPatterns CGP; const CodeGenTarget &Target; + CodeGenRegBank CGRegs; /// Keep track of the equivalence between SDNodes and Instruction. /// This is defined using 'GINodeEquiv' in the target description. @@ -1238,9 +1323,9 @@ Error importChildMatcher(InstructionMatcher &InsnMatcher, TreePatternNode *SrcChild, unsigned OpIdx, unsigned &TempOpIdx) const; - Expected createAndImportInstructionRenderer( - RuleMatcher &M, const TreePatternNode *Dst, - const InstructionMatcher &InsnMatcher) const; + Expected + createAndImportInstructionRenderer(RuleMatcher &M, const TreePatternNode *Dst, + const InstructionMatcher &InsnMatcher); Error importExplicitUseRenderer(BuildMIAction &DstMIBuilder, TreePatternNode *DstChild, const InstructionMatcher &InsnMatcher) const; @@ -1277,7 +1362,7 @@ } GlobalISelEmitter::GlobalISelEmitter(RecordKeeper &RK) - : RK(RK), CGP(RK), Target(CGP.getTargetInfo()) {} + : RK(RK), CGP(RK), Target(CGP.getTargetInfo()), CGRegs(RK) {} //===- Emitter ------------------------------------------------------------===// @@ -1388,15 +1473,10 @@ auto *ChildRec = ChildDefInit->getDef(); // Check for register classes. - if (ChildRec->isSubClassOf("RegisterClass")) { - OM.addPredicate( - Target.getRegisterClass(ChildRec)); - return Error::success(); - } - - if (ChildRec->isSubClassOf("RegisterOperand")) { + if (ChildRec->isSubClassOf("RegisterClass") || + ChildRec->isSubClassOf("RegisterOperand")) { OM.addPredicate( - Target.getRegisterClass(ChildRec->getValueAsDef("RegClass"))); + Target.getRegisterClass(getInitValueAsRegClass(ChildDefInit))); return Error::success(); } @@ -1495,7 +1575,7 @@ Expected GlobalISelEmitter::createAndImportInstructionRenderer( RuleMatcher &M, const TreePatternNode *Dst, - const InstructionMatcher &InsnMatcher) const { + const InstructionMatcher &InsnMatcher) { Record *DstOp = Dst->getOperator(); if (!DstOp->isSubClassOf("Instruction")) { if (DstOp->isSubClassOf("ValueType")) @@ -1503,22 +1583,61 @@ "Pattern operator isn't an instruction (it's a ValueType)"); return failedImport("Pattern operator isn't an instruction"); } - auto &DstI = Target.getInstruction(DstOp); + auto *DstI = &Target.getInstruction(DstOp); - auto &DstMIBuilder = M.addAction(&DstI, InsnMatcher); + unsigned DstINumUses = DstI->Operands.size() - DstI->Operands.NumDefs; + unsigned ExpectedDstINumUses = Dst->getNumChildren(); + bool IsExtractSubReg = false; + + // COPY_TO_REGCLASS is just a copy with a ConstrainOperandToRegClassAction + // attached. Similarly for EXTRACT_SUBREG except that's a subregister copy. + if (DstI->TheDef->getName() == "COPY_TO_REGCLASS") { + DstI = &Target.getInstruction(RK.getDef("COPY")); + DstINumUses--; // Ignore the class constraint. + ExpectedDstINumUses--; + } else if (DstI->TheDef->getName() == "EXTRACT_SUBREG") { + DstI = &Target.getInstruction(RK.getDef("COPY")); + IsExtractSubReg = true; + } + + auto &DstMIBuilder = M.addAction("NewI", DstI, InsnMatcher); // Render the explicit defs. - for (unsigned I = 0; I < DstI.Operands.NumDefs; ++I) { - const auto &DstIOperand = DstI.Operands[I]; + for (unsigned I = 0; I < DstI->Operands.NumDefs; ++I) { + const auto &DstIOperand = DstI->Operands[I]; DstMIBuilder.addRenderer(InsnMatcher, DstIOperand.Name); } + // EXTRACT_SUBREG needs to use a subregister COPY. + if (IsExtractSubReg) { + if (!Dst->getChild(0)->isLeaf()) + return failedImport("EXTRACT_SUBREG child #1 is not a leaf"); + + if (DefInit *SubRegInit = dyn_cast(Dst->getChild(1)->getLeafValue())) { + CodeGenRegisterClass *RC = CGRegs.getRegClass( + getInitValueAsRegClass(Dst->getChild(0)->getLeafValue())); + CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); + + CodeGenRegisterClass *DstRC = nullptr; + CodeGenRegisterClass *SrcRC = + RC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx, &DstRC); + assert(DstRC && "Couldn't find a matching subclass"); + if (SrcRC != RC) + return failedImport("EXTRACT_SUBREG requires an additional COPY"); + + DstMIBuilder.addRenderer( + InsnMatcher, Dst->getChild(0)->getName(), SubIdx); + return DstMIBuilder; + } + + return failedImport("EXTRACT_SUBREG child #1 is not a subreg index"); + } + // Render the explicit uses. unsigned Child = 0; - unsigned DstINumUses = DstI.Operands.size() - DstI.Operands.NumDefs; unsigned NumDefaultOps = 0; for (unsigned I = 0; I != DstINumUses; ++I) { - const auto &DstIOperand = DstI.Operands[DstI.Operands.NumDefs + I]; + const auto &DstIOperand = DstI->Operands[DstI->Operands.NumDefs + I]; // If the operand has default values, introduce them now. // FIXME: Until we have a decent test case that dictates we should do @@ -1539,10 +1658,10 @@ ++Child; } - if (NumDefaultOps + Dst->getNumChildren() != DstINumUses) + if (NumDefaultOps + ExpectedDstINumUses != DstINumUses) return failedImport("Expected " + llvm::to_string(DstINumUses) + " used operands but found " + - llvm::to_string(Dst->getNumChildren()) + + llvm::to_string(ExpectedDstINumUses) + " explicit ones and " + llvm::to_string(NumDefaultOps) + " default ones"); @@ -1630,10 +1749,26 @@ const auto &DstIOperand = DstI.Operands[OpIdx]; Record *DstIOpRec = DstIOperand.Rec; - if (DstIOpRec->isSubClassOf("RegisterOperand")) + if (DstI.TheDef->getName() == "COPY_TO_REGCLASS") { + DstIOpRec = getInitValueAsRegClass(Dst->getChild(1)->getLeafValue()); + + if (DstIOpRec == nullptr) + return failedImport( + "COPY_TO_REGCLASS operand #1 isn't a register class"); + } else if (DstI.TheDef->getName() == "EXTRACT_SUBREG") { + if (!Dst->getChild(0)->isLeaf()) + return failedImport("EXTRACT_SUBREG operand #0 isn't a leaf"); + + // We can assume that a subregister is in the same bank as it's super register. + DstIOpRec = getInitValueAsRegClass(Dst->getChild(0)->getLeafValue()); + + if (DstIOpRec == nullptr) + return failedImport( + "EXTRACT_SUBREG operand #0 isn't a register class"); + } else if (DstIOpRec->isSubClassOf("RegisterOperand")) DstIOpRec = DstIOpRec->getValueAsDef("RegClass"); - if (!DstIOpRec->isSubClassOf("RegisterClass")) - return failedImport("Dst MI def isn't a register class"); + else if (!DstIOpRec->isSubClassOf("RegisterClass")) + return failedImport("Dst MI def isn't a register class" + to_string(*Dst)); OperandMatcher &OM = InsnMatcher.getOperand(OpIdx); OM.setSymbolicName(DstIOperand.Name); @@ -1653,6 +1788,61 @@ if (auto Error = importImplicitDefRenderers(DstMIBuilder, P.getDstRegs())) return std::move(Error); + // Constrain the registers to classes. This is normally derived from the + // emitted instruction but a few instructions require special handling. + if (DstI.TheDef->getName() == "COPY_TO_REGCLASS") { + // COPY_TO_REGCLASS does not provide operand constraints itself but the + // result is constrained to the class given by the second child. + Record *DstIOpRec = + getInitValueAsRegClass(Dst->getChild(1)->getLeafValue()); + + if (DstIOpRec == nullptr) + return failedImport("COPY_TO_REGCLASS operand #1 isn't a register class"); + + M.addAction( + "NewI", 0, Target.getRegisterClass(DstIOpRec)); + } else if (DstI.TheDef->getName() == "EXTRACT_SUBREG") { + // EXTRACT_SUBREG selects into a subregister COPY but unlike most + // instructions, the result register class is controlled by the + // subregisters of the operand. As a result, we must constrain the result + // class rather than check that it's already the right one. + if (!Dst->getChild(0)->isLeaf()) + return failedImport("EXTRACT_SUBREG child #1 is not a leaf"); + + if (DefInit *SubRegInit = + dyn_cast(Dst->getChild(1)->getLeafValue())) { + // Constrain the result to the same register bank as the operand. + Record *DstIOpRec = + getInitValueAsRegClass(Dst->getChild(0)->getLeafValue()); + + if (DstIOpRec == nullptr) + return failedImport( + "COPY_TO_REGCLASS operand #1 isn't a register class"); + + CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef()); + CodeGenRegisterClass *SrcRC = CGRegs.getRegClass( + getInitValueAsRegClass(Dst->getChild(0)->getLeafValue())); + + // It would be nice to leave this constraint implicit but we're required + // to pick a register class so constrain the result to a register class + // that can hold the correct MVT. + // + // FIXME: This may introduce an extra copy if the chosen class doesn't + // actually contain the subregisters. + assert(Src->getExtTypes().size() == 1); + + CodeGenRegisterClass *DstRC = nullptr; + SrcRC = SrcRC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx, &DstRC); + assert(DstRC && "Couldn't find a matching subclass"); + M.addAction("NewI", 0, *DstRC); + + return M; + } + + return failedImport("EXTRACT_SUBREG child #1 is not a subreg index"); + } else + M.addAction("NewI"); + // We're done with this pattern! It's eligible for GISel emission; return it. ++NumPatternImported; return std::move(M);