Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8297,6 +8297,10 @@
   switch (cast<ConstantSDNode>(Op.getOperand(ArgStart))->getZExtValue()) {
   case Intrinsic::ppc_cfence: {
     assert(ArgStart == 1);
+    // If the operand is a constant (e.g. load from a constant pool being
+    // constant folded), there is no need to form a fence.
+    if (isa<ConstantSDNode>(Op.getOperand(ArgStart + 1)))
+      return Op.getOperand(0);
     assert(Subtarget.isPPC64() && "Only 64-bit is supported for now.");
     return SDValue(DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other,
                                       DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64,
Index: llvm/test/CodeGen/PowerPC/atomics-constant.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/atomics-constant.ll
+++ llvm/test/CodeGen/PowerPC/atomics-constant.ll
@@ -9,12 +9,8 @@
 ; CHECK-LABEL: foo:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
-; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
-; CHECK-NEXT:    cmpw 7, 4, 4
 ; CHECK-NEXT:    ld 3, 0(3)
-; CHECK-NEXT:    bne- 7, .+4
-; CHECK-NEXT:    isync
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
 entry: