Index: cmake/builtin-config-ix.cmake
===================================================================
--- cmake/builtin-config-ix.cmake
+++ cmake/builtin-config-ix.cmake
@@ -24,7 +24,7 @@
 
 
 set(ARM64 aarch64)
-set(ARM32 arm armhf armv6m)
+set(ARM32 arm armhf armv6m armv7m armv7em armv7 armv7s armv7k)
 set(X86 i386 i686)
 set(X86_64 x86_64)
 set(MIPS32 mips mipsel)
Index: lib/builtins/arm/aeabi_cdcmp.S
===================================================================
--- lib/builtins/arm/aeabi_cdcmp.S
+++ lib/builtins/arm/aeabi_cdcmp.S
@@ -48,7 +48,12 @@
         // NaN has been ruled out, so __aeabi_cdcmple can't trap
         bne __aeabi_cdcmple
 
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+        mov ip, #APSR_C
+        msr APSR_nzcvq, ip
+#else
         msr CPSR_f, #APSR_C
+#endif
         JMP(lr)
 #endif
 END_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
@@ -95,17 +100,23 @@
         lsls r0, r0, #31
         pop {r0-r3, pc}
 #else
+        ITT(eq)
         moveq ip, #0
         beq 1f
 
         ldm sp, {r0-r3}
         bl __aeabi_dcmpeq
         cmp r0, #1
+        ITE(eq)
         moveq ip, #(APSR_C | APSR_Z)
         movne ip, #(APSR_C)
 
 1:
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+        msr APSR_nzcvq, ip
+#else
         msr CPSR_f, ip
+#endif
         pop {r0-r3}
         POP_PC()
 #endif
Index: lib/builtins/arm/aeabi_cfcmp.S
===================================================================
--- lib/builtins/arm/aeabi_cfcmp.S
+++ lib/builtins/arm/aeabi_cfcmp.S
@@ -48,7 +48,12 @@
         // NaN has been ruled out, so __aeabi_cfcmple can't trap
         bne __aeabi_cfcmple
 
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+        mov ip, #APSR_C
+        msr APSR_nzcvq, ip
+#else
         msr CPSR_f, #APSR_C
+#endif
         JMP(lr)
 #endif
 END_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
@@ -95,17 +100,23 @@
         lsls r0, r0, #31
         pop {r0-r3, pc}
 #else
+        ITT(eq)
         moveq ip, #0
         beq 1f
 
         ldm sp, {r0-r3}
         bl __aeabi_fcmpeq
         cmp r0, #1
+        ITE(eq)
         moveq ip, #(APSR_C | APSR_Z)
         movne ip, #(APSR_C)
 
 1:
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+        msr APSR_nzcvq, ip
+#else
         msr CPSR_f, ip
+#endif
         pop {r0-r3}
         POP_PC()
 #endif
Index: lib/builtins/arm/eqdf2vfp.S
===================================================================
--- lib/builtins/arm/eqdf2vfp.S
+++ lib/builtins/arm/eqdf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f64 d6, d7		
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(eq)
 	moveq	r0, #1		// set result register to 1 if equal
 	movne	r0, #0
 	bx	lr
Index: lib/builtins/arm/eqsf2vfp.S
===================================================================
--- lib/builtins/arm/eqsf2vfp.S
+++ lib/builtins/arm/eqsf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f32 s14, s15
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(eq)
 	moveq	r0, #1      // set result register to 1 if equal
 	movne	r0, #0
 	bx	lr
Index: lib/builtins/arm/gedf2vfp.S
===================================================================
--- lib/builtins/arm/gedf2vfp.S
+++ lib/builtins/arm/gedf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f64 d6, d7
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(ge)
 	movge	r0, #1      // set result register to 1 if greater than or equal
 	movlt	r0, #0
 	bx	lr
Index: lib/builtins/arm/gesf2vfp.S
===================================================================
--- lib/builtins/arm/gesf2vfp.S
+++ lib/builtins/arm/gesf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f32 s14, s15
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(ge)
 	movge	r0, #1      // set result register to 1 if greater than or equal
 	movlt	r0, #0
 	bx	lr
Index: lib/builtins/arm/gtdf2vfp.S
===================================================================
--- lib/builtins/arm/gtdf2vfp.S
+++ lib/builtins/arm/gtdf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f64 d6, d7
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(gt)
 	movgt	r0, #1		// set result register to 1 if equal
 	movle	r0, #0
 	bx	lr
Index: lib/builtins/arm/gtsf2vfp.S
===================================================================
--- lib/builtins/arm/gtsf2vfp.S
+++ lib/builtins/arm/gtsf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f32 s14, s15
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(gt)
 	movgt	r0, #1		// set result register to 1 if equal
 	movle	r0, #0
 	bx	lr
Index: lib/builtins/arm/ledf2vfp.S
===================================================================
--- lib/builtins/arm/ledf2vfp.S
+++ lib/builtins/arm/ledf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f64 d6, d7
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(ls)
 	movls	r0, #1		// set result register to 1 if equal
 	movhi	r0, #0
 	bx	lr
Index: lib/builtins/arm/lesf2vfp.S
===================================================================
--- lib/builtins/arm/lesf2vfp.S
+++ lib/builtins/arm/lesf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f32 s14, s15
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(ls)
 	movls	r0, #1      // set result register to 1 if equal
 	movhi	r0, #0
 	bx	lr
Index: lib/builtins/arm/ltdf2vfp.S
===================================================================
--- lib/builtins/arm/ltdf2vfp.S
+++ lib/builtins/arm/ltdf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f64 d6, d7
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(mi)
 	movmi	r0, #1		// set result register to 1 if equal
 	movpl	r0, #0
 	bx	lr
Index: lib/builtins/arm/ltsf2vfp.S
===================================================================
--- lib/builtins/arm/ltsf2vfp.S
+++ lib/builtins/arm/ltsf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f32 s14, s15
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(mi)
 	movmi	r0, #1      // set result register to 1 if equal
 	movpl	r0, #0
 	bx	lr
Index: lib/builtins/arm/nedf2vfp.S
===================================================================
--- lib/builtins/arm/nedf2vfp.S
+++ lib/builtins/arm/nedf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f64 d6, d7		
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(ne)
 	movne	r0, #1		// set result register to 0 if unequal
 	moveq	r0, #0
 	bx	lr
Index: lib/builtins/arm/nesf2vfp.S
===================================================================
--- lib/builtins/arm/nesf2vfp.S
+++ lib/builtins/arm/nesf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f32 s14, s15
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(ne)
 	movne	r0, #1      // set result register to 1 if unequal
 	moveq	r0, #0
 	bx	lr
Index: lib/builtins/arm/unorddf2vfp.S
===================================================================
--- lib/builtins/arm/unorddf2vfp.S
+++ lib/builtins/arm/unorddf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f64 d6, d7
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(vs)
 	movvs	r0, #1      // set result register to 1 if "overflow" (any NaNs)
 	movvc	r0, #0
 	bx	lr
Index: lib/builtins/arm/unordsf2vfp.S
===================================================================
--- lib/builtins/arm/unordsf2vfp.S
+++ lib/builtins/arm/unordsf2vfp.S
@@ -27,6 +27,7 @@
 	vcmp.f32 s14, s15
 #endif
 	vmrs	apsr_nzcv, fpscr
+	ITE(vs)
 	movvs	r0, #1      // set result register to 1 if "overflow" (any NaNs)
 	movvc	r0, #0
 	bx	lr
Index: lib/builtins/assembly.h
===================================================================
--- lib/builtins/assembly.h
+++ lib/builtins/assembly.h
@@ -96,9 +96,11 @@
 #if __ARM_ARCH_ISA_THUMB == 2
 #define IT(cond)  it cond
 #define ITT(cond) itt cond
+#define ITE(cond) ite cond
 #else
 #define IT(cond)
 #define ITT(cond)
+#define ITE(cond)
 #endif
 
 #if __ARM_ARCH_ISA_THUMB == 2