Index: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -36,6 +36,8 @@
   setAction({G_CONSTANT, S32}, Legal);
   setAction({G_CONSTANT, S64}, Legal);
 
+  setAction({G_FCONSTANT, S32}, Legal);
+
   setAction({G_GEP, P1}, Legal);
   setAction({G_GEP, P2}, Legal);
   setAction({G_GEP, 1, S64}, Legal);
Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2331,6 +2331,10 @@
 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
                                     StringRef &ErrInfo) const {
   uint16_t Opcode = MI.getOpcode();
+
+  if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
+    return true;
+
   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
   int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
Index: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
@@ -5,6 +5,11 @@
   entry:
     ret void
   }
+
+  define void @test_fconstant() {
+  entry:
+    ret void
+  }
 ...
 
 ---
@@ -18,3 +23,18 @@
 
     %0(s32) = G_CONSTANT i32 5
 ...
+
+---
+name:            test_fconstant
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_fconstant
+    ; CHECK: %0(s32) = G_FCONSTANT  float 1.000000e+00
+    ; CHECK: %1(s32) = G_FCONSTANT  float 7.5
+
+    %0(s32) = G_FCONSTANT float 1.0
+    %1(s32) = G_FCONSTANT float 7.5
+...