Index: lib/Target/NVPTX/NVPTXISelLowering.cpp
===================================================================
--- lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -1549,7 +1549,7 @@
           Chain = DAG.getMemIntrinsicNode(
               Op, dl, DAG.getVTList(MVT::Other, MVT::Glue), StoreOperands,
               TheStoreType, MachinePointerInfo(), EltAlign,
-              /* Volatile */ false, /* ReadMem */ true,
+              /* Volatile */ false, /* ReadMem */ false,
               /* WriteMem */ true, /* Size */ 0);
           InFlag = Chain.getValue(1);
 
@@ -1611,7 +1611,7 @@
       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
                                       CopyParamOps, elemtype,
                                       MachinePointerInfo(), /* Align */ 0,
-                                      /* Volatile */ false, /* ReadMem */ true,
+                                      /* Volatile */ false, /* ReadMem */ false,
                                       /* WriteMem */ true, /* Size */ 0);
 
       InFlag = Chain.getValue(1);
@@ -1799,7 +1799,7 @@
         SDValue RetVal = DAG.getMemIntrinsicNode(
             Op, dl, DAG.getVTList(LoadVTs), LoadOperands, TheLoadType,
             MachinePointerInfo(), EltAlign, /* Volatile */ false,
-            /* ReadMem */ true, /* WriteMem */ true, /* Size */ 0);
+            /* ReadMem */ true, /* WriteMem */ false, /* Size */ 0);
 
         for (unsigned j = 0; j < NumElts; ++j) {
           SDValue Ret = RetVal.getValue(j);
Index: test/CodeGen/NVPTX/bug17709.ll
===================================================================
--- test/CodeGen/NVPTX/bug17709.ll
+++ test/CodeGen/NVPTX/bug17709.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 
 ; ModuleID = '__kernelgen_main_module'
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Index: test/CodeGen/NVPTX/f16-instructions.ll
===================================================================
--- test/CodeGen/NVPTX/f16-instructions.ll
+++ test/CodeGen/NVPTX/f16-instructions.ll
@@ -1,14 +1,15 @@
 ; ## Full FP16 support enabled by default.
 ; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \
-; RUN:          -O0 -disable-post-ra -disable-fp-elim \
+; RUN:          -O0 -disable-post-ra -disable-fp-elim -verify-machineinstrs \
 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-F16 %s
 ; ## FP16 support explicitly disabled.
 ; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \
 ; RUN:          -O0 -disable-post-ra -disable-fp-elim --nvptx-no-f16-math \
+; RUN:           -verify-machineinstrs \
 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOF16 %s
 ; ## FP16 is not supported by hardware.
 ; RUN: llc < %s -O0 -mtriple=nvptx64-nvidia-cuda -mcpu=sm_52 -asm-verbose=false \
-; RUN:          -disable-post-ra -disable-fp-elim \
+; RUN:          -disable-post-ra -disable-fp-elim -verify-machineinstrs \
 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOF16 %s
 
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
Index: test/CodeGen/NVPTX/f16x2-instructions.ll
===================================================================
--- test/CodeGen/NVPTX/f16x2-instructions.ll
+++ test/CodeGen/NVPTX/f16x2-instructions.ll
@@ -1,14 +1,15 @@
 ; ## Full FP16 support enabled by default.
 ; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \
-; RUN:          -O0 -disable-post-ra -disable-fp-elim \
+; RUN:          -O0 -disable-post-ra -disable-fp-elim -verify-machineinstrs \
 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-F16 %s
 ; ## FP16 support explicitly disabled.
 ; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \
 ; RUN:          -O0 -disable-post-ra -disable-fp-elim --nvptx-no-f16-math \
+; RUN:           -verify-machineinstrs \
 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOF16 %s
 ; ## FP16 is not supported by hardware.
 ; RUN: llc < %s -O0 -mtriple=nvptx64-nvidia-cuda -mcpu=sm_52 -asm-verbose=false \
-; RUN:          -disable-post-ra -disable-fp-elim \
+; RUN:          -disable-post-ra -disable-fp-elim -verify-machineinstrs \
 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOF16 %s
 
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
Index: test/CodeGen/NVPTX/fma.ll
===================================================================
--- test/CodeGen/NVPTX/fma.ll
+++ test/CodeGen/NVPTX/fma.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -fp-contract=fast -verify-machineinstrs | FileCheck %s
 
 declare float @dummy_f32(float, float) #0
 declare double @dummy_f64(double, double) #0
Index: test/CodeGen/NVPTX/i8-param.ll
===================================================================
--- test/CodeGen/NVPTX/i8-param.ll
+++ test/CodeGen/NVPTX/i8-param.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
 
Index: test/CodeGen/NVPTX/param-load-store.ll
===================================================================
--- test/CodeGen/NVPTX/param-load-store.ll
+++ test/CodeGen/NVPTX/param-load-store.ll
@@ -1,5 +1,5 @@
 ; Verifies correctness of load/store of parameters and return values.
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 -O0 | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 -O0 -verify-machineinstrs | FileCheck %s
 
 %s_i1 = type { i1 }
 %s_i8 = type { i8 }
Index: test/CodeGen/NVPTX/simple-call.ll
===================================================================
--- test/CodeGen/NVPTX/simple-call.ll
+++ test/CodeGen/NVPTX/simple-call.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 
 
 
Index: test/CodeGen/NVPTX/vector-call.ll
===================================================================
--- test/CodeGen/NVPTX/vector-call.ll
+++ test/CodeGen/NVPTX/vector-call.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 
 target triple = "nvptx-unknown-cuda"
 
Index: test/CodeGen/NVPTX/zeroext-32bit.ll
===================================================================
--- test/CodeGen/NVPTX/zeroext-32bit.ll
+++ test/CodeGen/NVPTX/zeroext-32bit.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_30 | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_30 -verify-machineinstrs | FileCheck %s
 
 ; The zeroext attribute below should be silently ignored because
 ; we can pass a 32-bit integer across a function call without