PR18921, vmov part

[dyatkovskiy]

Summary

Purpose of patch is to add byte replicate recognition for "vmov" and "vmvn" instructions. It is kind of compatibility fix for GCC. Since GCC generates .s files with illegal vmov and vmvn byte-replicator instructions (e. g. vmov.i32 d0, #abababab).
Current version introduces new AsmOperand classes for vmov.i16, vmov.i32, vmvn.i16 and vmvn.i32 instructions, that detects bytes replication and encodes them with proper way (actually it converts them into vmov.i8).
Thanks for reviews!

[rengolin]

Hi Stepan,

Apart from the comments, looks good to me.

Thanks,
--renato

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

2294

Typos: compatibility, "even if they are illegal", gcc-as -> gnu-as.

[dyatkovskiy]

Thanks, Renato! I'll try to find way to do it from TableGen in Monday. If there is no way in TableGen, we could accept this fix for a while then.
Straight after :vararg directive, I could start work on improving tablegen if needed.
-Cheers!

[dyatkovskiy]

Hi Renato,
Please take a look at this version of fix.
Previous version could potentially give us wrong encoding. Since we change opcode in place where nobody expects.
New one fits existing style. And guarantees proper encoding.
Thanks!

[t.p.northover]

I'm not convinced about this one. I don't think 0xffffffff is such a special case. If we're going to do this compatibility alias (*sigh*), we've probably got to handle things like "vmov.i32 dD, 0xabababab" as well (and goodness knows what else).

Cheers.

Tim.

[dyatkovskiy]

Tim, actually you right )
I have just checked. "vmov.i32 d0, 0xabababab" is legal for GAS. And "vmvn.i32 d0, 0xabababab" as well...
(*sigh*).
Though recognition algorithm looks simple to me: "all bytes are equal".
I could fix it...

[rengolin]

Are you sure that this is the only special case? It seems to me that gas
accepts almost anything and try to be super smart.

Cheers,
Renato

[dyatkovskiy]

Hello Renato. We did do our small research with Tim.
GAS behaves like he reads instruction bit width (i16 or i32). And then checks whether these bits contains repeated bytes.
So, for example: "vmov.i16 d0, 0xabab" is legal. "vmob.i16 d0, 0xabcd) - not.

[dyatkovskiy]

This logic could fit pretty nice in "isNEONi32splatOnes" and friends. Of course it should be renamed to somewhat "isNEONi32splatSameBytes"

[rengolin]

Right, I was afraid gas would recognise garbage and create a string of
instructions. Seems not to be the case. Thanks for checking.

Renato

[dyatkovskiy]

Please, review updated fix.

1. It implements byte replication for VMVN and VMOV.

So "vmov.i16 d0, #0xabab" - becomes legal.
As result MC fullfills d0 with #0xab bytes.
Zero byte #0 is exception. It passed "as-is".

2. It forbids byte replication for VORR and VBIC. We can enable it. But, interesting fact, it forbidden in GCC. + It is illegal. So, the less workarounds the better IMHO.

3. Few more reasons.

In current llvm-mc state (before fix) 16-bit cases are *legal*, but llvm-mc implicitly converts
"vmov.i16 d0, #0xabab"
into
"vmov.i16 q2, #0xab00"
That seems to be wrong.

And for i32: #0xabababab --> #0xab000000

All the same with "vorr" and "vbic": bytes zeroizing at the tail.

[rengolin]

The reasoning looks good to me, though I can't review the code right now. If Tim is ok with it, I'm good.

[dyatkovskiy]

Currently I'm working on combination AsmPseudoInst + PseudoExpand solution. It could be really horrible :-)

[dyatkovskiy]

Renato,
Thanks!

 Well... below is my little confession.

It is really not easy to decide whether we should have this workaround. And whether it should be implemented that way.
Though I'm 99% sure now, that it is only possible way.

Actually I have spent about 3-4 hours one day, and 5-6 hours another day, and all the day today, looking in TableGen internals. All just to find how to implement something like :

def : NEONInstAlias<"instrA $Vm", (InstrB DPR:$Vd, ZeroizeImm AllOnesImm:$Vm)>;

IMHO, ideal solution would be like below:

def nImmByteReplicateXForm: SDNodeXForm<imm, [{
  unsigned Value = 0xff & N->getZExtValue();
  Value |= 0xe00;
  return CurDAG->getTargetConstant(Value, MVT::i32);
}]>;
def nImmVMOVI32ByteReplicate : Operand<i32>, PatLeaf<(imm), [{
    unsigned Imm = N->getZExtValue();
    if (!Imm)
      return false; // Don't bother with zero.
    unsigned char B = Imm & 0xff;
    for (unsigned i = 1; i < NumBytes; ++i) {
      Imm >>= 8;
      if ((Imm & 0xff) != B)
        return false;
    }
    return true;
  }], ImmByteReplicateXForm> {
  let PrintMethod = "printNEONModImmOperand";
  let ParserMatchClass = nImmVMOVI32AsmOperand;
}
def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
                    (VMOVv8i8 DPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;

But no. It doesn't work :-(
Inlined C++ code fragments actually are PatFrag's predicate code, and SDNodeXForm's XFormFunction. We need to much assembler instructions with specific imm values. There are two possible ways: NEONAsmPseudo and NEONInstAlias. But these classes has nothing common with DAG patterns and SDNodeXForms.

Actually I wanted to implement whole chain:

<asm> --> <dag-transform> --> <aliasing>

just in .td files.
But there is not such support. And we had to implement new class hierarchy from fundamental TableGen classes.

Even operand classes like imm0_4095 have ARMAsmParser handlers.

Also deviation from common style isn't that good. So I've looked at rest of similar checks. Every checks like that (detection of some specific imm values, for example) are implemented as C++ code in ARMAsmParser.cpp, as set of handlers for AsmOperandClass.

So I did the same: I have just implemented ways of how to recognize immediates we accept, and then how to encode them.

So here we are. I understand circumstances, and ready to wait as long as we need.

Thanks )

[dyatkovskiy]

Simplified previous version:

• For nImmVMOVI32AsmOperandByteReplicate and friends, has been customized PredicateMethod and RenderMethod. That allowed to reduce code size in ARMAsmParser.

[• rafael]

lib/Target/ARM/ARMInstrNEON.td

5347

"assembly generator", no?

In any case, it is not really relevant in the assembly is generated or user written. Just say that we (and gas) support this extension.

The comment is also out of date since the code now supports 0xabab for example.

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1640

please clang-format the patch.

[dyatkovskiy]

Hi Rafael,
Thanks for review!
I have fixed comments and passed patch through clang format as you asked.

[dyatkovskiy]

lib/Target/ARM/ARMInstrNEON.td

5348

Yeah. I see my typo: instrustions -> instructions.

[• rafael]

You don't have a test showing an error with vmov or vmvn (vmov 0xfffffffe for example).

I think the patch is OK with the extra test, but since this is ARM I will let Tim or Renato do the final review.

[dyatkovskiy]

Added test for illegal cases.

[• rafael]

Fine by me. Renato, Tim, what do you guys think?

[rengolin]

Hi Rafael,

Looks good to me too.

cheers,
--renato

[dyatkovskiy]

r207080
Thanks for reviews!

lib/Target/ARM/ARMInstrNEON.td

   let PrintMethod = "printNEONModImmOperand";
   let ParserMatchClass = nImmSplatI32AsmOperand;
 }
 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
 def nImmVMOVI32 : Operand<i32> {
   let PrintMethod = "printNEONModImmOperand";
   let ParserMatchClass = nImmVMOVI32AsmOperand;
 }
+
+def nImmVMOVI16AsmOperandByteReplicate :
+  AsmOperandClass {
+  let Name = "NEONi16vmovByteReplicate";
+  let PredicateMethod = "isNEONi16ByteReplicate";
+  let RenderMethod = "addNEONvmovByteReplicateOperands";
+}
+def nImmVMOVI32AsmOperandByteReplicate :
+  AsmOperandClass {
+  let Name = "NEONi32vmovByteReplicate";
+  let PredicateMethod = "isNEONi32ByteReplicate";
+  let RenderMethod = "addNEONvmovByteReplicateOperands";
+}
+def nImmVMVNI16AsmOperandByteReplicate :
+  AsmOperandClass {
+  let Name = "NEONi16invByteReplicate";
+  let PredicateMethod = "isNEONi16ByteReplicate";
+  let RenderMethod = "addNEONinvByteReplicateOperands";
+}
+def nImmVMVNI32AsmOperandByteReplicate :
+  AsmOperandClass {
+  let Name = "NEONi32invByteReplicate";
+  let PredicateMethod = "isNEONi32ByteReplicate";
+  let RenderMethod = "addNEONinvByteReplicateOperands";
+}
+
+def nImmVMOVI16ByteReplicate : Operand<i32> {
+  let PrintMethod = "printNEONModImmOperand";
+  let ParserMatchClass = nImmVMOVI16AsmOperandByteReplicate;
+}
+def nImmVMOVI32ByteReplicate : Operand<i32> {
+  let PrintMethod = "printNEONModImmOperand";
+  let ParserMatchClass = nImmVMOVI32AsmOperandByteReplicate;
+}
+def nImmVMVNI16ByteReplicate : Operand<i32> {
+  let PrintMethod = "printNEONModImmOperand";
+  let ParserMatchClass = nImmVMVNI16AsmOperandByteReplicate;
+}
+def nImmVMVNI32ByteReplicate : Operand<i32> {
+  let PrintMethod = "printNEONModImmOperand";
+  let ParserMatchClass = nImmVMVNI32AsmOperandByteReplicate;
+}
+
 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
 def nImmVMOVI32Neg : Operand<i32> {
   let PrintMethod = "printNEONModImmOperand";
   let ParserMatchClass = nImmVMOVI32NegAsmOperand;
 }
 def nImmVMOVF32 : Operand<i32> {
   let PrintMethod = "printFPImmOperand";
   let ParserMatchClass = FPImmOperand;

                          "vmov", "f32", "$Vd, $SIMM", "",
                          [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
                          (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
                          "vmov", "f32", "$Vd, $SIMM", "",
                          [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
 } // isReMaterializable
 
+// Add support for bytes replication feature, so it could be GAS compatible.
+// E.g. instructions below:
+// "vmov.i32 d0, 0xffffffff"
+// "vmov.i32 d0, 0xabababab"
+// "vmov.i16 d0, 0xabab"
+// are incorrect, but we could deal with such cases.
+// For last two instructions, for example, it should emit:
+// "vmov.i8 d0, 0xab"
+def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
+                    (VMOVv8i8 DPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
+def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
+                    (VMOVv8i8 DPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
+def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
+                    (VMOVv16i8 QPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
+def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
+                    (VMOVv16i8 QPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
+
+// Also add same support for VMVN instructions. So instruction:
+// "vmvn.i32 d0, 0xabababab"
+// actually means:
+// "vmov.i8 d0, 0x54"
+def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
+                    (VMOVv8i8 DPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
+def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
+                    (VMOVv8i8 DPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
+def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
+                    (VMOVv16i8 QPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
+def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
+                    (VMOVv16i8 QPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
 
 // On some CPUs the two instructions "vmov.i32 dD, #0" and "vmov.i32 qD, #0"
 // require zero cycles to execute so they should be used wherever possible for
 // setting a register to zero.
 
 // Even without these pseudo-insts we would probably end up with the correct
 // instruction, but we could not mark the general ones with "isAsCheapAsAMove"
 // since they are sometimes rather expensive (in general).

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

     if (!isSingleSpacedVectorIndexed())
       return false;
     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
   }
 
   bool isVecListOneDWordIndexed() const {
     if (!isSingleSpacedVectorIndexed())
       return false;
     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
   }
 
   bool isVecListTwoDByteIndexed() const {
     if (!isSingleSpacedVectorIndexed())
       return false;
     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
   }
 

       return false;
     int64_t Value = CE->getValue();
     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
     // value.
     return Value >= 0 && Value < 256;
   }
 
   bool isNEONi16splat() const {
+    if (isNEONByteReplicate(2))
+      return false; // Leave that for bytes replication and forbid by default.
     if (!isImm())
       return false;
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     // Must be a constant.
     if (!CE)
       return false;
     int64_t Value = CE->getValue();
     // i16 value in the range [0,255] or [0x0100, 0xff00]
     return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
   }
 
   bool isNEONi32splat() const {
+    if (isNEONByteReplicate(4))
+      return false; // Leave that for bytes replication and forbid by default.
     if (!isImm())
       return false;
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     // Must be a constant.
     if (!CE)
       return false;
     int64_t Value = CE->getValue();
     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
     return (Value >= 0 && Value < 256) ||
            (Value >= 0x0100 && Value <= 0xff00) ||
            (Value >= 0x010000 && Value <= 0xff0000) ||
            (Value >= 0x01000000 && Value <= 0xff000000);
   }
 
+  bool isNEONByteReplicate(unsigned NumBytes) const {
+    if (!isImm())
+      return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    // Must be a constant.
+    if (!CE)
+      return false;
+    int64_t Value = CE->getValue();
+    if (!Value)
+      return false; // Don't bother with zero.
+
+    unsigned char B = Value & 0xff;
+    for (unsigned i = 1; i < NumBytes; ++i) {
+      Value >>= 8;
+      if ((Value & 0xff) != B)
+        return false;
+    }
+    return true;
+  }
+  bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
+  bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
   bool isNEONi32vmov() const {
+    if (isNEONByteReplicate(4))
+      return false; // Let it to be classified as byte-replicate case.
     if (!isImm())
       return false;
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     // Must be a constant.
     if (!CE)
       return false;
     int64_t Value = CE->getValue();
     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,

         Val = -Val;
       Val = ARM_AM::getAM3Opc(AddSub, Val);
     } else {
       // For register offset, we encode the shift type and negation flag
       // here.
       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
     }
     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     if (Kind == k_PostIndexRegister) {
       int32_t Val =
           ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);

       Value = (Value >> 8) | 0x200;
     else if (Value > 0xffff && Value <= 0xff0000)
       Value = (Value >> 16) | 0x400;
     else if (Value > 0xffffff)
       Value = (Value >> 24) | 0x600;
     Inst.addOperand(MCOperand::CreateImm(Value));
   }
 
+  void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // The immediate encodes the type of constant as well as the value.
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    unsigned Value = CE->getValue();
+    assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
+            Inst.getOpcode() == ARM::VMOVv16i8) &&
+           "All vmvn instructions that wants to replicate non-zero byte "
+           "always must be replaced with VMOVv8i8 or VMOVv16i8.");
+    unsigned B = ((~Value) & 0xff);
+    B |= 0xe00; // cmode = 0b1110
+    Inst.addOperand(MCOperand::CreateImm(B));
+  }
   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     // The immediate encodes the type of constant as well as the value.
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     unsigned Value = CE->getValue();
     if (Value >= 256 && Value <= 0xffff)
       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
     else if (Value > 0xffff && Value <= 0xffffff)
       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
     else if (Value > 0xffffff)
       Value = (Value >> 24) | 0x600;
     Inst.addOperand(MCOperand::CreateImm(Value));
   }
 
+  void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // The immediate encodes the type of constant as well as the value.
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    unsigned Value = CE->getValue();
+    assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
+            Inst.getOpcode() == ARM::VMOVv16i8) &&
+           "All instructions that wants to replicate non-zero byte "
+           "always must be replaced with VMOVv8i8 or VMOVv16i8.");
+    unsigned B = Value & 0xff;
+    B |= 0xe00; // cmode = 0b1110
+    Inst.addOperand(MCOperand::CreateImm(B));
+  }
   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     // The immediate encodes the type of constant as well as the value.
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     unsigned Value = ~CE->getValue();
     if (Value >= 256 && Value <= 0xffff)
       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
     else if (Value > 0xffff && Value <= 0xffffff)

test/MC/ARM/vmov-vmvn-byte-replicate.s

+@ PR18921, "vmov" part.
+@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
+.text
+
+@ CHECK: vmov.i8 d2, #0xff @ encoding: [0x1f,0x2e,0x87,0xf3]
+@ CHECK: vmov.i8 q2, #0xff @ encoding: [0x5f,0x4e,0x87,0xf3]
+@ CHECK: vmov.i8 d2, #0xab @ encoding: [0x1b,0x2e,0x82,0xf3]
+@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3]
+@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3]
+@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3]
+
+@ CHECK: vmov.i8 d2, #0x0  @ encoding: [0x10,0x2e,0x80,0xf2]
+@ CHECK: vmov.i8 q2, #0x0  @ encoding: [0x50,0x4e,0x80,0xf2]
+@ CHECK: vmov.i8 d2, #0x54 @ encoding: [0x14,0x2e,0x85,0xf2]
+@ CHECK: vmov.i8 q2, #0x54 @ encoding: [0x54,0x4e,0x85,0xf2]
+@ CHECK: vmov.i8 d2, #0x54 @ encoding: [0x14,0x2e,0x85,0xf2]
+@ CHECK: vmov.i8 q2, #0x54 @ encoding: [0x54,0x4e,0x85,0xf2]
+
+        vmov.i32        d2, #0xffffffff
+        vmov.i32        q2, #0xffffffff
+        vmov.i32        d2, #0xabababab
+        vmov.i32        q2, #0xabababab
+        vmov.i16        q2, #0xabab
+        vmov.i16        q2, #0xabab
+
+        vmvn.i32        d2, #0xffffffff
+        vmvn.i32        q2, #0xffffffff
+        vmvn.i32        d2, #0xabababab
+        vmvn.i32        q2, #0xabababab
+        vmvn.i16        d2, #0xabab
+        vmvn.i16        q2, #0xabab

test/MC/ARM/vmov-vmvn-illegal-cases.s

+@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
+.text
+
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vmov.i32        d2, #0xffffffab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vmov.i32        q2, #0xffffffab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vmov.i16        q2, #0xffab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vmov.i16        q2, #0xffab
+
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vmvn.i32        d2, #0xffffffab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vmvn.i32        q2, #0xffffffab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vmvn.i16        q2, #0xffab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vmvn.i16        q2, #0xffab
+
+        vmov.i32        d2, #0xffffffab
+        vmov.i32        q2, #0xffffffab
+        vmov.i16        q2, #0xffab
+        vmov.i16        q2, #0xffab
+
+        vmvn.i32        d2, #0xffffffab
+        vmvn.i32        q2, #0xffffffab
+        vmvn.i16        q2, #0xffab
+        vmvn.i16        q2, #0xffab

test/MC/ARM/vorr-vbic-illegal-cases.s

+@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
+.text
+
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vorr.i32        d2, #0xffffffff
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vorr.i32        q2, #0xffffffff
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vorr.i32        d2, #0xabababab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vorr.i32        q2, #0xabababab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vorr.i16        q2, #0xabab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vorr.i16        q2, #0xabab
+
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vbic.i32        d2, #0xffffffff
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vbic.i32        q2, #0xffffffff
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vbic.i32        d2, #0xabababab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vbic.i32        q2, #0xabababab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vbic.i16        d2, #0xabab
+@ CHECK: error: invalid operand for instruction
+@ CHECK: vbic.i16        q2, #0xabab
+
+        vorr.i32        d2, #0xffffffff
+        vorr.i32        q2, #0xffffffff
+        vorr.i32        d2, #0xabababab
+        vorr.i32        q2, #0xabababab
+        vorr.i16        q2, #0xabab
+        vorr.i16        q2, #0xabab
+
+        vbic.i32        d2, #0xffffffff
+        vbic.i32        q2, #0xffffffff
+        vbic.i32        d2, #0xabababab
+        vbic.i32        q2, #0xabababab
+        vbic.i16        d2, #0xabab
+        vbic.i16        q2, #0xabab