Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3048,6 +3048,7 @@
 SDValue DAGTypeLegalizer::WidenVSELECTAndMask(SDNode *N) {
   LLVMContext &Ctx = *DAG.getContext();
   SDValue Cond = N->getOperand(0);
+  EVT CondVT = Cond.getValueType();
 
   if (N->getOpcode() != ISD::VSELECT)
     return SDValue();
@@ -3057,7 +3058,7 @@
 
   // If this is a splitted VSELECT that was previously already handled, do
   // nothing.
-  if (Cond->getValueType(0).getScalarSizeInBits() != 1)
+  if (CondVT.getScalarSizeInBits() != 1)
     return SDValue();
 
   EVT VSelVT = N->getValueType(0);
@@ -3073,7 +3074,14 @@
   if (FinalVT.getVectorNumElements() == 1)
     return SDValue();
 
-  // If there is support for an i1 vector mask, don't touch.
+  // If the resulting i1 vector mask is a fully legal type, don't widen it.
+  EVT FinalMaskVT = EVT::getVectorVT(Ctx, CondVT.getVectorElementType(),
+                                     FinalVT.getVectorNumElements());
+  if (TLI.getTypeAction(Ctx, FinalMaskVT) == TargetLowering::TypeLegal)
+    return SDValue();
+
+  // If there is support for an i1 vector mask when coming out of a SETCC node,
+  // don't touch.
   if (Cond.getOpcode() == ISD::SETCC) {
     EVT SetCCOpVT = Cond->getOperand(0).getValueType();
     while (TLI.getTypeAction(Ctx, SetCCOpVT) != TargetLowering::TypeLegal)
Index: test/CodeGen/X86/avx512-vselect.ll
===================================================================
--- test/CodeGen/X86/avx512-vselect.ll
+++ test/CodeGen/X86/avx512-vselect.ll
@@ -28,13 +28,9 @@
 ; CHECK-SKX-NEXT:    vxorps %zmm6, %zmm6, %zmm6
 ; CHECK-SKX-NEXT:    vcmpltps %zmm0, %zmm6, %k0
 ; CHECK-SKX-NEXT:    vcmpltps %zmm6, %zmm1, %k1
-; CHECK-SKX-NEXT:    korw %k1, %k0, %k0
-; CHECK-SKX-NEXT:    kshiftrw $8, %k0, %k1
-; CHECK-SKX-NEXT:    vpmovm2q %k1, %zmm1
-; CHECK-SKX-NEXT:    vpmovm2q %k0, %zmm0
-; CHECK-SKX-NEXT:    vptestmq %zmm0, %zmm0, %k1
+; CHECK-SKX-NEXT:    korw %k1, %k0, %k1
 ; CHECK-SKX-NEXT:    vblendmpd %zmm2, %zmm4, %zmm0 {%k1}
-; CHECK-SKX-NEXT:    vptestmq %zmm1, %zmm1, %k1
+; CHECK-SKX-NEXT:    kshiftrw $8, %k1, %k1
 ; CHECK-SKX-NEXT:    vblendmpd %zmm3, %zmm5, %zmm1 {%k1}
 ; CHECK-SKX-NEXT:    retq
 ;
@@ -44,12 +40,8 @@
 ; CHECK-KNL-NEXT:    vcmpltps %zmm0, %zmm6, %k0
 ; CHECK-KNL-NEXT:    vcmpltps %zmm6, %zmm1, %k1
 ; CHECK-KNL-NEXT:    korw %k1, %k0, %k1
-; CHECK-KNL-NEXT:    kshiftrw $8, %k1, %k2
-; CHECK-KNL-NEXT:    vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k2} {z}
-; CHECK-KNL-NEXT:    vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; CHECK-KNL-NEXT:    vptestmq %zmm0, %zmm0, %k1
 ; CHECK-KNL-NEXT:    vblendmpd %zmm2, %zmm4, %zmm0 {%k1}
-; CHECK-KNL-NEXT:    vptestmq %zmm1, %zmm1, %k1
+; CHECK-KNL-NEXT:    kshiftrw $8, %k1, %k1
 ; CHECK-KNL-NEXT:    vblendmpd %zmm3, %zmm5, %zmm1 {%k1}
 ; CHECK-KNL-NEXT:    retq
 entry: