Index: lib/Target/AMDGPU/SIInsertWaitcnts.cpp
===================================================================
--- lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -1087,7 +1087,7 @@
            (CntVal[LGKM_CNT] & AMDGPU::getLgkmcntBitMask(IV)))) {
         MachineLoop *ContainingLoop = MLI->getLoopFor(MI.getParent());
         if (ContainingLoop) {
-          MachineBasicBlock *TBB = ContainingLoop->getTopBlock();
+          MachineBasicBlock *TBB = ContainingLoop->getHeader();
           BlockWaitcntBrackets *ScoreBracket =
               BlockWaitcntBracketsMap[TBB].get();
           if (!ScoreBracket) {
@@ -1097,7 +1097,7 @@
           }
           ScoreBracket->setRevisitLoop(true);
           DEBUG(dbgs() << "set-revisit: block"
-                       << ContainingLoop->getTopBlock()->getNumber() << '\n';);
+                       << ContainingLoop->getHeader()->getNumber() << '\n';);
         }
       }
 
@@ -1758,12 +1758,12 @@
     // If we are walking into the block from before the loop, then guarantee
     // at least 1 re-walk over the loop to propagate the information, even if
     // no S_WAITCNT instructions were generated.
-    if (ContainingLoop && ContainingLoop->getTopBlock() == &MBB && J < I &&
+    if (ContainingLoop && ContainingLoop->getHeader() == &MBB && J < I &&
         (BlockWaitcntProcessedSet.find(&MBB) ==
          BlockWaitcntProcessedSet.end())) {
       BlockWaitcntBracketsMap[&MBB]->setRevisitLoop(true);
       DEBUG(dbgs() << "set-revisit: block"
-                   << ContainingLoop->getTopBlock()->getNumber() << '\n';);
+                   << ContainingLoop->getHeader()->getNumber() << '\n';);
     }
 
     // Walk over the instructions.
@@ -1774,7 +1774,7 @@
 
     // See if we want to revisit the loop.
     if (ContainingLoop && loopBottom(ContainingLoop) == &MBB) {
-      MachineBasicBlock *EntryBB = ContainingLoop->getTopBlock();
+      MachineBasicBlock *EntryBB = ContainingLoop->getHeader();
       BlockWaitcntBrackets *EntrySB = BlockWaitcntBracketsMap[EntryBB].get();
       if (EntrySB && EntrySB->getRevisitLoop()) {
         EntrySB->setRevisitLoop(false);
Index: test/CodeGen/AMDGPU/waitcnt-looptest.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/waitcnt-looptest.ll
@@ -0,0 +1,168 @@
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global | FileCheck --check-prefix=GCN %s
+
+; Check that the waitcnt insertion algorithm correctly propagates wait counts
+; from before a loop to the loop header.
+
+; GCN-LABEL: {{^}}testKernel
+; GCN: BB0_1:
+; GCN: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_eq_f32_e64
+; GCN: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_eq_f32_e32
+; GCN: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cmp_eq_f32_e32
+
+@data_generic = addrspace(1) global [100 x float] [float 0.000000e+00, float 0x3FB99999A0000000, float 0x3FC99999A0000000, float 0x3FD3333340000000, float 0x3FD99999A0000000, float 5.000000e-01, float 0x3FE3333340000000, float 0x3FE6666660000000, float 0x3FE99999A0000000, float 0x3FECCCCCC0000000, float 1.000000e+00, float 0x3FF19999A0000000, float 0x3FF3333340000000, float 0x3FF4CCCCC0000000, float 0x3FF6666660000000, float 1.500000e+00, float 0x3FF99999A0000000, float 0x3FFB333340000000, float 0x3FFCCCCCC0000000, float 0x3FFE666660000000, float 2.000000e+00, float 0x4000CCCCC0000000, float 0x40019999A0000000, float 0x4002666660000000, float 0x4003333340000000, float 2.500000e+00, float 0x4004CCCCC0000000, float 0x40059999A0000000, float 0x4006666660000000, float 0x4007333340000000, float 3.000000e+00, float 0x4008CCCCC0000000, float 0x40099999A0000000, float 0x400A666660000000, float 0x400B333340000000, float 3.500000e+00, float 0x400CCCCCC0000000, float 0x400D9999A0000000, float 0x400E666660000000, float 0x400F333340000000, float 4.000000e+00, float 0x4010666660000000, float 0x4010CCCCC0000000, float 0x4011333340000000, float 0x40119999A0000000, float 4.500000e+00, float 0x4012666660000000, float 0x4012CCCCC0000000, float 0x4013333340000000, float 0x40139999A0000000, float 5.000000e+00, float 0x4014666660000000, float 0x4014CCCCC0000000, float 0x4015333340000000, float 0x40159999A0000000, float 5.500000e+00, float 0x4016666660000000, float 0x4016CCCCC0000000, float 0x4017333340000000, float 0x40179999A0000000, float 6.000000e+00, float 0x4018666660000000, float 0x4018CCCCC0000000, float 0x4019333340000000, float 0x40199999A0000000, float 6.500000e+00, float 0x401A666660000000, float 0x401ACCCCC0000000, float 0x401B333340000000, float 0x401B9999A0000000, float 7.000000e+00, float 0x401C666660000000, float 0x401CCCCCC0000000, float 0x401D333340000000, float 0x401D9999A0000000, float 7.500000e+00, float 0x401E666660000000, float 0x401ECCCCC0000000, float 0x401F333340000000, float 0x401F9999A0000000, float 8.000000e+00, float 0x4020333340000000, float 0x4020666660000000, float 0x40209999A0000000, float 0x4020CCCCC0000000, float 8.500000e+00, float 0x4021333340000000, float 0x4021666660000000, float 0x40219999A0000000, float 0x4021CCCCC0000000, float 9.000000e+00, float 0x4022333340000000, float 0x4022666660000000, float 0x40229999A0000000, float 0x4022CCCCC0000000, float 9.500000e+00, float 0x4023333340000000, float 0x4023666660000000, float 0x40239999A0000000, float 0x4023CCCCC0000000], align 4
+@data_reference = addrspace(1) global [100 x float] [float 0.000000e+00, float 0x3FB99999A0000000, float 0x3FC99999A0000000, float 0x3FD3333340000000, float 0x3FD99999A0000000, float 5.000000e-01, float 0x3FE3333340000000, float 0x3FE6666660000000, float 0x3FE99999A0000000, float 0x3FECCCCCC0000000, float 1.000000e+00, float 0x3FF19999A0000000, float 0x3FF3333340000000, float 0x3FF4CCCCC0000000, float 0x3FF6666660000000, float 1.500000e+00, float 0x3FF99999A0000000, float 0x3FFB333340000000, float 0x3FFCCCCCC0000000, float 0x3FFE666660000000, float 2.000000e+00, float 0x4000CCCCC0000000, float 0x40019999A0000000, float 0x4002666660000000, float 0x4003333340000000, float 2.500000e+00, float 0x4004CCCCC0000000, float 0x40059999A0000000, float 0x4006666660000000, float 0x4007333340000000, float 3.000000e+00, float 0x4008CCCCC0000000, float 0x40099999A0000000, float 0x400A666660000000, float 0x400B333340000000, float 3.500000e+00, float 0x400CCCCCC0000000, float 0x400D9999A0000000, float 0x400E666660000000, float 0x400F333340000000, float 4.000000e+00, float 0x4010666660000000, float 0x4010CCCCC0000000, float 0x4011333340000000, float 0x40119999A0000000, float 4.500000e+00, float 0x4012666660000000, float 0x4012CCCCC0000000, float 0x4013333340000000, float 0x40139999A0000000, float 5.000000e+00, float 0x4014666660000000, float 0x4014CCCCC0000000, float 0x4015333340000000, float 0x40159999A0000000, float 5.500000e+00, float 0x4016666660000000, float 0x4016CCCCC0000000, float 0x4017333340000000, float 0x40179999A0000000, float 6.000000e+00, float 0x4018666660000000, float 0x4018CCCCC0000000, float 0x4019333340000000, float 0x40199999A0000000, float 6.500000e+00, float 0x401A666660000000, float 0x401ACCCCC0000000, float 0x401B333340000000, float 0x401B9999A0000000, float 7.000000e+00, float 0x401C666660000000, float 0x401CCCCCC0000000, float 0x401D333340000000, float 0x401D9999A0000000, float 7.500000e+00, float 0x401E666660000000, float 0x401ECCCCC0000000, float 0x401F333340000000, float 0x401F9999A0000000, float 8.000000e+00, float 0x4020333340000000, float 0x4020666660000000, float 0x40209999A0000000, float 0x4020CCCCC0000000, float 8.500000e+00, float 0x4021333340000000, float 0x4021666660000000, float 0x40219999A0000000, float 0x4021CCCCC0000000, float 9.000000e+00, float 0x4022333340000000, float 0x4022666660000000, float 0x40229999A0000000, float 0x4022CCCCC0000000, float 9.500000e+00, float 0x4023333340000000, float 0x4023666660000000, float 0x40239999A0000000, float 0x4023CCCCC0000000], align 4
+
+; Function Attrs: nounwind
+define amdgpu_kernel void @testKernel(i32 addrspace(1)* nocapture) local_unnamed_addr #0 !kernel_arg_addr_space !2 !kernel_arg_access_qual !3 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 !kernel_arg_name !6 {
+  store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> addrspace(4)* bitcast (float addrspace(4)* getelementptr ([100 x float], [100 x float] addrspace(4)* addrspacecast ([100 x float] addrspace(1)* @data_generic to [100 x float] addrspace(4)*), i64 0, i64 4) to <2 x float> addrspace(4)*), align 4, !tbaa !7
+  store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> addrspace(4)* bitcast (float addrspace(4)* getelementptr ([100 x float], [100 x float] addrspace(4)* addrspacecast ([100 x float] addrspace(1)* @data_reference to [100 x float] addrspace(4)*), i64 0, i64 4) to <2 x float> addrspace(4)*), align 4, !tbaa !7
+  br label %20
+
+; <label>:2:                                      ; preds = %20
+  %3 = tail call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #1
+  %4 = tail call i32 @llvm.amdgcn.workitem.id.x() #1
+  %5 = tail call i32 @llvm.amdgcn.workgroup.id.x() #1
+  %6 = getelementptr inbounds i8, i8 addrspace(2)* %3, i64 4
+  %7 = bitcast i8 addrspace(2)* %6 to i16 addrspace(2)*
+  %8 = load i16, i16 addrspace(2)* %7, align 4, !tbaa !10
+  %9 = zext i16 %8 to i32
+  %10 = mul i32 %5, %9
+  %11 = add i32 %10, %4
+  %12 = tail call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #1
+  %13 = zext i32 %11 to i64
+  %14 = bitcast i8 addrspace(2)* %12 to i64 addrspace(2)*
+  %15 = load i64, i64 addrspace(2)* %14, align 8, !tbaa !17
+  %16 = add i64 %15, %13
+  %17 = zext i1 %101 to i32
+  %18 = and i64 %16, 4294967295
+  %19 = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 %18
+  store i32 %17, i32 addrspace(1)* %19, align 4, !tbaa !18
+  ret void
+
+; <label>:20:                                     ; preds = %20, %1
+  %21 = phi i64 [ 0, %1 ], [ %104, %20 ]
+  %22 = phi i32 [ 0, %1 ], [ %102, %20 ]
+  %23 = phi i1 [ true, %1 ], [ %101, %20 ]
+  %24 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i64 %21
+  %25 = load float, float addrspace(1)* %24, align 4, !tbaa !19
+  %26 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_reference, i64 0, i64 %21
+  %27 = load float, float addrspace(1)* %26, align 4, !tbaa !19
+  %28 = fcmp oeq float %25, %27
+  %29 = and i1 %23, %28
+  %30 = or i32 %22, 1
+  %31 = sext i32 %30 to i64
+  %32 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i64 %31
+  %33 = load float, float addrspace(1)* %32, align 4, !tbaa !19
+  %34 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_reference, i64 0, i64 %31
+  %35 = load float, float addrspace(1)* %34, align 4, !tbaa !19
+  %36 = fcmp oeq float %33, %35
+  %37 = and i1 %29, %36
+  %38 = add nuw nsw i32 %22, 2
+  %39 = sext i32 %38 to i64
+  %40 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i64 %39
+  %41 = load float, float addrspace(1)* %40, align 4, !tbaa !19
+  %42 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_reference, i64 0, i64 %39
+  %43 = load float, float addrspace(1)* %42, align 4, !tbaa !19
+  %44 = fcmp oeq float %41, %43
+  %45 = and i1 %37, %44
+  %46 = add nuw nsw i32 %22, 3
+  %47 = sext i32 %46 to i64
+  %48 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i64 %47
+  %49 = load float, float addrspace(1)* %48, align 4, !tbaa !19
+  %50 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_reference, i64 0, i64 %47
+  %51 = load float, float addrspace(1)* %50, align 4, !tbaa !19
+  %52 = fcmp oeq float %49, %51
+  %53 = and i1 %45, %52
+  %54 = add nuw nsw i32 %22, 4
+  %55 = sext i32 %54 to i64
+  %56 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i64 %55
+  %57 = load float, float addrspace(1)* %56, align 4, !tbaa !19
+  %58 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_reference, i64 0, i64 %55
+  %59 = load float, float addrspace(1)* %58, align 4, !tbaa !19
+  %60 = fcmp oeq float %57, %59
+  %61 = and i1 %53, %60
+  %62 = add nuw nsw i32 %22, 5
+  %63 = sext i32 %62 to i64
+  %64 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i64 %63
+  %65 = load float, float addrspace(1)* %64, align 4, !tbaa !19
+  %66 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_reference, i64 0, i64 %63
+  %67 = load float, float addrspace(1)* %66, align 4, !tbaa !19
+  %68 = fcmp oeq float %65, %67
+  %69 = and i1 %61, %68
+  %70 = add nuw nsw i32 %22, 6
+  %71 = sext i32 %70 to i64
+  %72 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i64 %71
+  %73 = load float, float addrspace(1)* %72, align 4, !tbaa !19
+  %74 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_reference, i64 0, i64 %71
+  %75 = load float, float addrspace(1)* %74, align 4, !tbaa !19
+  %76 = fcmp oeq float %73, %75
+  %77 = and i1 %69, %76
+  %78 = add nuw nsw i32 %22, 7
+  %79 = sext i32 %78 to i64
+  %80 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i64 %79
+  %81 = load float, float addrspace(1)* %80, align 4, !tbaa !19
+  %82 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_reference, i64 0, i64 %79
+  %83 = load float, float addrspace(1)* %82, align 4, !tbaa !19
+  %84 = fcmp oeq float %81, %83
+  %85 = and i1 %77, %84
+  %86 = add nuw nsw i32 %22, 8
+  %87 = sext i32 %86 to i64
+  %88 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i64 %87
+  %89 = load float, float addrspace(1)* %88, align 4, !tbaa !19
+  %90 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_reference, i64 0, i64 %87
+  %91 = load float, float addrspace(1)* %90, align 4, !tbaa !19
+  %92 = fcmp oeq float %89, %91
+  %93 = and i1 %85, %92
+  %94 = add nuw nsw i32 %22, 9
+  %95 = sext i32 %94 to i64
+  %96 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i64 %95
+  %97 = load float, float addrspace(1)* %96, align 4, !tbaa !19
+  %98 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_reference, i64 0, i64 %95
+  %99 = load float, float addrspace(1)* %98, align 4, !tbaa !19
+  %100 = fcmp oeq float %97, %99
+  %101 = and i1 %93, %100
+  %102 = add nuw nsw i32 %22, 10
+  %103 = icmp eq i32 %102, 100
+  %104 = sext i32 %102 to i64
+  br i1 %103, label %2, label %20
+}
+
+; Function Attrs: nounwind readnone
+declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #1
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.amdgcn.workitem.id.x() #1
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.amdgcn.workgroup.id.x() #1
+
+; Function Attrs: nounwind readnone
+declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #1
+
+!opencl.ocl.version = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 2, i32 0}
+!1 = !{!"clang version 4.0 "}
+!2 = !{i32 1}
+!3 = !{!"none"}
+!4 = !{!"uint*"}
+!5 = !{!""}
+!6 = !{!"results"}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"omnipotent char", !9, i64 0}
+!9 = !{!"Simple C/C++ TBAA"}
+!10 = !{!11, !12, i64 4}
+!11 = !{!"hsa_kernel_dispatch_packet_s", !12, i64 0, !12, i64 2, !12, i64 4, !12, i64 6, !12, i64 8, !12, i64 10, !13, i64 12, !13, i64 16, !13, i64 20, !13, i64 24, !13, i64 28, !14, i64 32, !15, i64 40, !14, i64 48, !16, i64 56}
+!12 = !{!"short", !8, i64 0}
+!13 = !{!"int", !8, i64 0}
+!14 = !{!"long", !8, i64 0}
+!15 = !{!"any pointer", !8, i64 0}
+!16 = !{!"hsa_signal_s", !14, i64 0}
+!17 = !{!14, !14, i64 0}
+!18 = !{!13, !13, i64 0}
+!19 = !{!20, !20, i64 0}
+!20 = !{!"float", !8, i64 0}