Index: include/llvm/IR/IntrinsicsPowerPC.td
===================================================================
--- include/llvm/IR/IntrinsicsPowerPC.td
+++ include/llvm/IR/IntrinsicsPowerPC.td
@@ -896,6 +896,18 @@
       PowerPC_VSX_Intrinsic<"xxinsertw",[llvm_v4i32_ty],
                             [llvm_v4i32_ty,llvm_v2i64_ty,llvm_i32_ty],
                             [IntrNoMem]>;
+
+// Vector Permute Doubleword Immediate
+def int_ppc_vsx_xxpermdi :
+      PowerPC_VSX_Intrinsic<"xxpermdi",[llvm_v2i64_ty],
+                            [llvm_v2i64_ty,llvm_v2i64_ty,llvm_i32_ty],
+                            [IntrNoMem]>;
+
+// Vector Shift Left Double by Word Immediate
+def int_ppc_vsx_xxsldi:
+      PowerPC_VSX_Intrinsic<"xxsldwi",[llvm_v2i64_ty],
+                            [llvm_v2i64_ty,llvm_v2i64_ty,llvm_i32_ty],
+                            [IntrNoMem]>;
 }
 
 //===----------------------------------------------------------------------===//
Index: lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- lib/Target/PowerPC/PPCInstrVSX.td
+++ lib/Target/PowerPC/PPCInstrVSX.td
@@ -2280,6 +2280,14 @@
             (v4i32 (XXINSERTW $A, $B, imm:$IMM))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxextractuw v2i64:$A, imm:$IMM)),
             (v2i64 (COPY_TO_REGCLASS (XXEXTRACTUW $A, imm:$IMM), VSRC))>;
+
+  // Extra patterns expanding to vector Permute Doubleword Immediate
+  def : Pat<(v2i64 (int_ppc_vsx_xxpermdi v2i64:$A, v2i64:$B, imm:$IMM)),
+            (v2i64 (XXPERMDI $A, $B, imm:$IMM))>;
+
+  // Extra patterns expanding to vector Shift Left Double by Word Immediate
+  def : Pat<(v2i64 (int_ppc_vsx_xxsldi v2i64:$A, v2i64:$B, imm:$IMM)),
+            (v2i64 (XXSLDWI $A, $B, imm:$IMM))>;
   } // AddedComplexity = 400, HasP9Vector
 
   //===--------------------------------------------------------------------===//
Index: test/CodeGen/PowerPC/p9-xxpermdi.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/p9-xxpermdi.ll
@@ -0,0 +1,40 @@
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+
+define <2 x i64> @intrinsicXXPERMDITest0(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: intrinsicXXPERMDITest0
+; CHECK: xxmrghd  34, 34, 35
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxpermdi(<2 x i64> %a, <2 x i64> %b, i32 0)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @intrinsicXXPERMDITest1(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: intrinsicXXPERMDITest1
+; CHECK: xxpermdi 34, 34, 35, 1
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxpermdi(<2 x i64> %a, <2 x i64> %b, i32 1)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @intrinsicXXPERMDITest2(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: intrinsicXXPERMDITest2
+; CHECK: xxpermdi 34, 34, 35, 2
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxpermdi(<2 x i64> %a, <2 x i64> %b, i32 2)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @intrinsicXXPERMDITest3(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: intrinsicXXPERMDITest3
+; CHECK: xxmrgld 34, 34, 35
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxpermdi(<2 x i64> %a, <2 x i64> %b, i32 3)
+  ret <2 x i64> %ans
+}
+
+declare <2 x i64>  @llvm.ppc.vsx.xxpermdi(<2 x i64>, <2 x i64>, i32)
Index: test/CodeGen/PowerPC/p9-xxsldi.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/p9-xxsldi.ll
@@ -0,0 +1,40 @@
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+
+define <2 x i64> @intrinsicXXSLDITest0(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: intrinsicXXSLDITest0
+; CHECK: xxsldwi 34, 34, 35, 0
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxsldi(<2 x i64> %a, <2 x i64> %b, i32 0)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @intrinsicXXSLDITest1(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: intrinsicXXSLDITest1
+; CHECK: xxsldwi 34, 34, 35, 1
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxsldi(<2 x i64> %a, <2 x i64> %b, i32 1)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @intrinsicXXSLDITest2(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: intrinsicXXSLDITest2
+; CHECK: xxsldwi 34, 34, 35, 2
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxsldi(<2 x i64> %a, <2 x i64> %b, i32 2)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @intrinsicXXSLDITest3(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: intrinsicXXSLDITest3
+; CHECK: xxsldwi 34, 34, 35, 3
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxsldi(<2 x i64> %a, <2 x i64> %b, i32 3)
+  ret <2 x i64> %ans
+}
+
+declare <2 x i64>  @llvm.ppc.vsx.xxsldi(<2 x i64>, <2 x i64>, i32)