Index: llvm/trunk/include/llvm/IR/IntrinsicsX86.td =================================================================== --- llvm/trunk/include/llvm/IR/IntrinsicsX86.td +++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td @@ -3221,6 +3221,29 @@ } //===----------------------------------------------------------------------===// +// LWP +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_llwpcb : + GCCBuiltin<"__builtin_ia32_llwpcb">, + Intrinsic<[], [llvm_ptr_ty], []>; + def int_x86_slwpcb : + GCCBuiltin<"__builtin_ia32_slwpcb">, + Intrinsic<[llvm_ptr_ty], [], []>; + def int_x86_lwpins32 : + GCCBuiltin<"__builtin_ia32_lwpins32">, + Intrinsic<[llvm_i8_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_x86_lwpins64 : + GCCBuiltin<"__builtin_ia32_lwpins64">, + Intrinsic<[llvm_i8_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_x86_lwpval32 : + GCCBuiltin<"__builtin_ia32_lwpval32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_x86_lwpval64 : + GCCBuiltin<"__builtin_ia32_lwpval64">, + Intrinsic<[], [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty], []>; +} + +//===----------------------------------------------------------------------===// // MMX // Empty MMX state op. Index: llvm/trunk/lib/Support/Host.cpp =================================================================== --- llvm/trunk/lib/Support/Host.cpp +++ llvm/trunk/lib/Support/Host.cpp @@ -1,1495 +1,1496 @@ -//===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the operating system Host concept. -// -//===----------------------------------------------------------------------===// - -#include "llvm/Support/Host.h" -#include "llvm/ADT/SmallSet.h" -#include "llvm/ADT/SmallVector.h" -#include "llvm/ADT/StringRef.h" -#include "llvm/ADT/StringSwitch.h" -#include "llvm/ADT/Triple.h" -#include "llvm/Config/config.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/FileSystem.h" -#include "llvm/Support/MemoryBuffer.h" -#include "llvm/Support/raw_ostream.h" -#include -#include - -// Include the platform-specific parts of this class. -#ifdef LLVM_ON_UNIX -#include "Unix/Host.inc" -#endif -#ifdef LLVM_ON_WIN32 -#include "Windows/Host.inc" -#endif -#ifdef _MSC_VER -#include -#endif -#if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) -#include -#include -#include -#include -#endif - -#define DEBUG_TYPE "host-detection" - -//===----------------------------------------------------------------------===// -// -// Implementations of the CPU detection routines -// -//===----------------------------------------------------------------------===// - -using namespace llvm; - -static std::unique_ptr - LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { - llvm::ErrorOr> Text = - llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); - if (std::error_code EC = Text.getError()) { - llvm::errs() << "Can't read " - << "/proc/cpuinfo: " << EC.message() << "\n"; - return nullptr; - } - return std::move(*Text); -} - -StringRef sys::detail::getHostCPUNameForPowerPC( - const StringRef &ProcCpuinfoContent) { - // Access to the Processor Version Register (PVR) on PowerPC is privileged, - // and so we must use an operating-system interface to determine the current - // processor type. On Linux, this is exposed through the /proc/cpuinfo file. - const char *generic = "generic"; - - // The cpu line is second (after the 'processor: 0' line), so if this - // buffer is too small then something has changed (or is wrong). - StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); - StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); - - StringRef::const_iterator CIP = CPUInfoStart; - - StringRef::const_iterator CPUStart = 0; - size_t CPULen = 0; - - // We need to find the first line which starts with cpu, spaces, and a colon. - // After the colon, there may be some additional spaces and then the cpu type. - while (CIP < CPUInfoEnd && CPUStart == 0) { - if (CIP < CPUInfoEnd && *CIP == '\n') - ++CIP; - - if (CIP < CPUInfoEnd && *CIP == 'c') { - ++CIP; - if (CIP < CPUInfoEnd && *CIP == 'p') { - ++CIP; - if (CIP < CPUInfoEnd && *CIP == 'u') { - ++CIP; - while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) - ++CIP; - - if (CIP < CPUInfoEnd && *CIP == ':') { - ++CIP; - while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) - ++CIP; - - if (CIP < CPUInfoEnd) { - CPUStart = CIP; - while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && - *CIP != ',' && *CIP != '\n')) - ++CIP; - CPULen = CIP - CPUStart; - } - } - } - } - } - - if (CPUStart == 0) - while (CIP < CPUInfoEnd && *CIP != '\n') - ++CIP; - } - - if (CPUStart == 0) - return generic; - - return StringSwitch(StringRef(CPUStart, CPULen)) - .Case("604e", "604e") - .Case("604", "604") - .Case("7400", "7400") - .Case("7410", "7400") - .Case("7447", "7400") - .Case("7455", "7450") - .Case("G4", "g4") - .Case("POWER4", "970") - .Case("PPC970FX", "970") - .Case("PPC970MP", "970") - .Case("G5", "g5") - .Case("POWER5", "g5") - .Case("A2", "a2") - .Case("POWER6", "pwr6") - .Case("POWER7", "pwr7") - .Case("POWER8", "pwr8") - .Case("POWER8E", "pwr8") - .Case("POWER8NVL", "pwr8") - .Case("POWER9", "pwr9") - .Default(generic); -} - -StringRef sys::detail::getHostCPUNameForARM( - const StringRef &ProcCpuinfoContent) { - // The cpuid register on arm is not accessible from user space. On Linux, - // it is exposed through the /proc/cpuinfo file. - - // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line - // in all cases. - SmallVector Lines; - ProcCpuinfoContent.split(Lines, "\n"); - - // Look for the CPU implementer line. - StringRef Implementer; - StringRef Hardware; - for (unsigned I = 0, E = Lines.size(); I != E; ++I) { - if (Lines[I].startswith("CPU implementer")) - Implementer = Lines[I].substr(15).ltrim("\t :"); - if (Lines[I].startswith("Hardware")) - Hardware = Lines[I].substr(8).ltrim("\t :"); - } - - if (Implementer == "0x41") { // ARM Ltd. - // MSM8992/8994 may give cpu part for the core that the kernel is running on, - // which is undeterministic and wrong. Always return cortex-a53 for these SoC. - if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) - return "cortex-a53"; - - - // Look for the CPU part line. - for (unsigned I = 0, E = Lines.size(); I != E; ++I) - if (Lines[I].startswith("CPU part")) - // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The - // values correspond to the "Part number" in the CP15/c0 register. The - // contents are specified in the various processor manuals. - return StringSwitch(Lines[I].substr(8).ltrim("\t :")) - .Case("0x926", "arm926ej-s") - .Case("0xb02", "mpcore") - .Case("0xb36", "arm1136j-s") - .Case("0xb56", "arm1156t2-s") - .Case("0xb76", "arm1176jz-s") - .Case("0xc08", "cortex-a8") - .Case("0xc09", "cortex-a9") - .Case("0xc0f", "cortex-a15") - .Case("0xc20", "cortex-m0") - .Case("0xc23", "cortex-m3") - .Case("0xc24", "cortex-m4") - .Case("0xd04", "cortex-a35") - .Case("0xd03", "cortex-a53") - .Case("0xd07", "cortex-a57") - .Case("0xd08", "cortex-a72") - .Case("0xd09", "cortex-a73") - .Default("generic"); - } - - if (Implementer == "0x51") // Qualcomm Technologies, Inc. - // Look for the CPU part line. - for (unsigned I = 0, E = Lines.size(); I != E; ++I) - if (Lines[I].startswith("CPU part")) - // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The - // values correspond to the "Part number" in the CP15/c0 register. The - // contents are specified in the various processor manuals. - return StringSwitch(Lines[I].substr(8).ltrim("\t :")) - .Case("0x06f", "krait") // APQ8064 - .Case("0x201", "kryo") - .Case("0x205", "kryo") - .Default("generic"); - - return "generic"; -} - -StringRef sys::detail::getHostCPUNameForS390x( - const StringRef &ProcCpuinfoContent) { - // STIDP is a privileged operation, so use /proc/cpuinfo instead. - - // The "processor 0:" line comes after a fair amount of other information, - // including a cache breakdown, but this should be plenty. - SmallVector Lines; - ProcCpuinfoContent.split(Lines, "\n"); - - // Look for the CPU features. - SmallVector CPUFeatures; - for (unsigned I = 0, E = Lines.size(); I != E; ++I) - if (Lines[I].startswith("features")) { - size_t Pos = Lines[I].find(":"); - if (Pos != StringRef::npos) { - Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); - break; - } - } - - // We need to check for the presence of vector support independently of - // the machine type, since we may only use the vector register set when - // supported by the kernel (and hypervisor). - bool HaveVectorSupport = false; - for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { - if (CPUFeatures[I] == "vx") - HaveVectorSupport = true; - } - - // Now check the processor machine type. - for (unsigned I = 0, E = Lines.size(); I != E; ++I) { - if (Lines[I].startswith("processor ")) { - size_t Pos = Lines[I].find("machine = "); - if (Pos != StringRef::npos) { - Pos += sizeof("machine = ") - 1; - unsigned int Id; - if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { - if (Id >= 2964 && HaveVectorSupport) - return "z13"; - if (Id >= 2827) - return "zEC12"; - if (Id >= 2817) - return "z196"; - } - } - break; - } - } - - return "generic"; -} - -#if defined(__i386__) || defined(_M_IX86) || \ - defined(__x86_64__) || defined(_M_X64) - -enum VendorSignatures { - SIG_INTEL = 0x756e6547 /* Genu */, - SIG_AMD = 0x68747541 /* Auth */ -}; - -enum ProcessorVendors { - VENDOR_INTEL = 1, - VENDOR_AMD, - VENDOR_OTHER, - VENDOR_MAX -}; - -enum ProcessorTypes { - INTEL_ATOM = 1, - INTEL_CORE2, - INTEL_COREI7, - AMDFAM10H, - AMDFAM15H, - INTEL_i386, - INTEL_i486, - INTEL_PENTIUM, - INTEL_PENTIUM_PRO, - INTEL_PENTIUM_II, - INTEL_PENTIUM_III, - INTEL_PENTIUM_IV, - INTEL_PENTIUM_M, - INTEL_CORE_DUO, - INTEL_XEONPHI, - INTEL_X86_64, - INTEL_NOCONA, - INTEL_PRESCOTT, - AMD_i486, - AMDPENTIUM, - AMDATHLON, - AMDFAM14H, - AMDFAM16H, - AMDFAM17H, - CPU_TYPE_MAX -}; - -enum ProcessorSubtypes { - INTEL_COREI7_NEHALEM = 1, - INTEL_COREI7_WESTMERE, - INTEL_COREI7_SANDYBRIDGE, - AMDFAM10H_BARCELONA, - AMDFAM10H_SHANGHAI, - AMDFAM10H_ISTANBUL, - AMDFAM15H_BDVER1, - AMDFAM15H_BDVER2, - INTEL_PENTIUM_MMX, - INTEL_CORE2_65, - INTEL_CORE2_45, - INTEL_COREI7_IVYBRIDGE, - INTEL_COREI7_HASWELL, - INTEL_COREI7_BROADWELL, - INTEL_COREI7_SKYLAKE, - INTEL_COREI7_SKYLAKE_AVX512, - INTEL_ATOM_BONNELL, - INTEL_ATOM_SILVERMONT, - INTEL_KNIGHTS_LANDING, - AMDPENTIUM_K6, - AMDPENTIUM_K62, - AMDPENTIUM_K63, - AMDPENTIUM_GEODE, - AMDATHLON_TBIRD, - AMDATHLON_MP, - AMDATHLON_XP, - AMDATHLON_K8SSE3, - AMDATHLON_OPTERON, - AMDATHLON_FX, - AMDATHLON_64, - AMD_BTVER1, - AMD_BTVER2, - AMDFAM15H_BDVER3, - AMDFAM15H_BDVER4, - AMDFAM17H_ZNVER1, - CPU_SUBTYPE_MAX -}; - -enum ProcessorFeatures { - FEATURE_CMOV = 0, - FEATURE_MMX, - FEATURE_POPCNT, - FEATURE_SSE, - FEATURE_SSE2, - FEATURE_SSE3, - FEATURE_SSSE3, - FEATURE_SSE4_1, - FEATURE_SSE4_2, - FEATURE_AVX, - FEATURE_AVX2, - FEATURE_AVX512, - FEATURE_AVX512SAVE, - FEATURE_MOVBE, - FEATURE_ADX, - FEATURE_EM64T -}; - -// The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). -// Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID -// support. Consequently, for i386, the presence of CPUID is checked first -// via the corresponding eflags bit. -// Removal of cpuid.h header motivated by PR30384 -// Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp -// or test-suite, but are used in external projects e.g. libstdcxx -static bool isCpuIdSupported() { -#if defined(__GNUC__) || defined(__clang__) -#if defined(__i386__) - int __cpuid_supported; - __asm__(" pushfl\n" - " popl %%eax\n" - " movl %%eax,%%ecx\n" - " xorl $0x00200000,%%eax\n" - " pushl %%eax\n" - " popfl\n" - " pushfl\n" - " popl %%eax\n" - " movl $0,%0\n" - " cmpl %%eax,%%ecx\n" - " je 1f\n" - " movl $1,%0\n" - "1:" - : "=r"(__cpuid_supported) - : - : "eax", "ecx"); - if (!__cpuid_supported) - return false; -#endif - return true; -#endif - return true; -} - -/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in -/// the specified arguments. If we can't run cpuid on the host, return true. -static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, - unsigned *rECX, unsigned *rEDX) { -#if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) -#if defined(__GNUC__) || defined(__clang__) -#if defined(__x86_64__) - // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. - // FIXME: should we save this for Clang? - __asm__("movq\t%%rbx, %%rsi\n\t" - "cpuid\n\t" - "xchgq\t%%rbx, %%rsi\n\t" - : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) - : "a"(value)); -#elif defined(__i386__) - __asm__("movl\t%%ebx, %%esi\n\t" - "cpuid\n\t" - "xchgl\t%%ebx, %%esi\n\t" - : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) - : "a"(value)); -#else - assert(0 && "This method is defined only for x86."); -#endif -#elif defined(_MSC_VER) - // The MSVC intrinsic is portable across x86 and x64. - int registers[4]; - __cpuid(registers, value); - *rEAX = registers[0]; - *rEBX = registers[1]; - *rECX = registers[2]; - *rEDX = registers[3]; -#endif - return false; -#else - return true; -#endif -} - -/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return -/// the 4 values in the specified arguments. If we can't run cpuid on the host, -/// return true. -static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, - unsigned *rEAX, unsigned *rEBX, unsigned *rECX, - unsigned *rEDX) { -#if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) -#if defined(__x86_64__) || defined(_M_X64) -#if defined(__GNUC__) || defined(__clang__) - // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. - // FIXME: should we save this for Clang? - __asm__("movq\t%%rbx, %%rsi\n\t" - "cpuid\n\t" - "xchgq\t%%rbx, %%rsi\n\t" - : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) - : "a"(value), "c"(subleaf)); -#elif defined(_MSC_VER) - int registers[4]; - __cpuidex(registers, value, subleaf); - *rEAX = registers[0]; - *rEBX = registers[1]; - *rECX = registers[2]; - *rEDX = registers[3]; -#endif -#elif defined(__i386__) || defined(_M_IX86) -#if defined(__GNUC__) || defined(__clang__) - __asm__("movl\t%%ebx, %%esi\n\t" - "cpuid\n\t" - "xchgl\t%%ebx, %%esi\n\t" - : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) - : "a"(value), "c"(subleaf)); -#elif defined(_MSC_VER) - __asm { - mov eax,value - mov ecx,subleaf - cpuid - mov esi,rEAX - mov dword ptr [esi],eax - mov esi,rEBX - mov dword ptr [esi],ebx - mov esi,rECX - mov dword ptr [esi],ecx - mov esi,rEDX - mov dword ptr [esi],edx - } -#endif -#else - assert(0 && "This method is defined only for x86."); -#endif - return false; -#else - return true; -#endif -} - -static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { -#if defined(__GNUC__) || defined(__clang__) - // Check xgetbv; this uses a .byte sequence instead of the instruction - // directly because older assemblers do not include support for xgetbv and - // there is no easy way to conditionally compile based on the assembler used. - __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); - return false; -#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) - unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); - *rEAX = Result; - *rEDX = Result >> 32; - return false; -#else - return true; -#endif -} - -static void detectX86FamilyModel(unsigned EAX, unsigned *Family, - unsigned *Model) { - *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 - *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 - if (*Family == 6 || *Family == 0xf) { - if (*Family == 0xf) - // Examine extended family ID if family ID is F. - *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 - // Examine extended model ID if family ID is 6 or F. - *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 - } -} - -static void -getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model, - unsigned int Brand_id, unsigned int Features, - unsigned *Type, unsigned *Subtype) { - if (Brand_id != 0) - return; - switch (Family) { - case 3: - *Type = INTEL_i386; - break; - case 4: - switch (Model) { - case 0: // Intel486 DX processors - case 1: // Intel486 DX processors - case 2: // Intel486 SX processors - case 3: // Intel487 processors, IntelDX2 OverDrive processors, - // IntelDX2 processors - case 4: // Intel486 SL processor - case 5: // IntelSX2 processors - case 7: // Write-Back Enhanced IntelDX2 processors - case 8: // IntelDX4 OverDrive processors, IntelDX4 processors - default: - *Type = INTEL_i486; - break; - } - break; - case 5: - switch (Model) { - case 1: // Pentium OverDrive processor for Pentium processor (60, 66), - // Pentium processors (60, 66) - case 2: // Pentium OverDrive processor for Pentium processor (75, 90, - // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, - // 150, 166, 200) - case 3: // Pentium OverDrive processors for Intel486 processor-based - // systems - *Type = INTEL_PENTIUM; - break; - case 4: // Pentium OverDrive processor with MMX technology for Pentium - // processor (75, 90, 100, 120, 133), Pentium processor with - // MMX technology (166, 200) - *Type = INTEL_PENTIUM; - *Subtype = INTEL_PENTIUM_MMX; - break; - default: - *Type = INTEL_PENTIUM; - break; - } - break; - case 6: - switch (Model) { - case 0x01: // Pentium Pro processor - *Type = INTEL_PENTIUM_PRO; - break; - case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, - // model 03 - case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, - // model 05, and Intel Celeron processor, model 05 - case 0x06: // Celeron processor, model 06 - *Type = INTEL_PENTIUM_II; - break; - case 0x07: // Pentium III processor, model 07, and Pentium III Xeon - // processor, model 07 - case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, - // model 08, and Celeron processor, model 08 - case 0x0a: // Pentium III Xeon processor, model 0Ah - case 0x0b: // Pentium III processor, model 0Bh - *Type = INTEL_PENTIUM_III; - break; - case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. - case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model - // 0Dh. All processors are manufactured using the 90 nm process. - case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 - // Integrated Processor with Intel QuickAssist Technology - *Type = INTEL_PENTIUM_M; - break; - case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model - // 0Eh. All processors are manufactured using the 65 nm process. - *Type = INTEL_CORE_DUO; - break; // yonah - case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile - // processor, Intel Core 2 Quad processor, Intel Core 2 Quad - // mobile processor, Intel Core 2 Extreme processor, Intel - // Pentium Dual-Core processor, Intel Xeon processor, model - // 0Fh. All processors are manufactured using the 65 nm process. - case 0x16: // Intel Celeron processor model 16h. All processors are - // manufactured using the 65 nm process - *Type = INTEL_CORE2; // "core2" - *Subtype = INTEL_CORE2_65; - break; - case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model - // 17h. All processors are manufactured using the 45 nm process. - // - // 45nm: Penryn , Wolfdale, Yorkfield (XE) - case 0x1d: // Intel Xeon processor MP. All processors are manufactured using - // the 45 nm process. - *Type = INTEL_CORE2; // "penryn" - *Subtype = INTEL_CORE2_45; - break; - case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All - // processors are manufactured using the 45 nm process. - case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. - // As found in a Summer 2010 model iMac. - case 0x1f: - case 0x2e: // Nehalem EX - *Type = INTEL_COREI7; // "nehalem" - *Subtype = INTEL_COREI7_NEHALEM; - break; - case 0x25: // Intel Core i7, laptop version. - case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All - // processors are manufactured using the 32 nm process. - case 0x2f: // Westmere EX - *Type = INTEL_COREI7; // "westmere" - *Subtype = INTEL_COREI7_WESTMERE; - break; - case 0x2a: // Intel Core i7 processor. All processors are manufactured - // using the 32 nm process. - case 0x2d: - *Type = INTEL_COREI7; //"sandybridge" - *Subtype = INTEL_COREI7_SANDYBRIDGE; - break; - case 0x3a: - case 0x3e: // Ivy Bridge EP - *Type = INTEL_COREI7; // "ivybridge" - *Subtype = INTEL_COREI7_IVYBRIDGE; - break; - - // Haswell: - case 0x3c: - case 0x3f: - case 0x45: - case 0x46: - *Type = INTEL_COREI7; // "haswell" - *Subtype = INTEL_COREI7_HASWELL; - break; - - // Broadwell: - case 0x3d: - case 0x47: - case 0x4f: - case 0x56: - *Type = INTEL_COREI7; // "broadwell" - *Subtype = INTEL_COREI7_BROADWELL; - break; - - // Skylake: - case 0x4e: // Skylake mobile - case 0x5e: // Skylake desktop - case 0x8e: // Kaby Lake mobile - case 0x9e: // Kaby Lake desktop - *Type = INTEL_COREI7; // "skylake" - *Subtype = INTEL_COREI7_SKYLAKE; - break; - - // Skylake Xeon: - case 0x55: - *Type = INTEL_COREI7; - // Check that we really have AVX512 - if (Features & (1 << FEATURE_AVX512)) { - *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" - } else { - *Subtype = INTEL_COREI7_SKYLAKE; // "skylake" - } - break; - - case 0x1c: // Most 45 nm Intel Atom processors - case 0x26: // 45 nm Atom Lincroft - case 0x27: // 32 nm Atom Medfield - case 0x35: // 32 nm Atom Midview - case 0x36: // 32 nm Atom Midview - *Type = INTEL_ATOM; - *Subtype = INTEL_ATOM_BONNELL; - break; // "bonnell" - - // Atom Silvermont codes from the Intel software optimization guide. - case 0x37: - case 0x4a: - case 0x4d: - case 0x5a: - case 0x5d: - case 0x4c: // really airmont - *Type = INTEL_ATOM; - *Subtype = INTEL_ATOM_SILVERMONT; - break; // "silvermont" - - case 0x57: - *Type = INTEL_XEONPHI; // knl - *Subtype = INTEL_KNIGHTS_LANDING; - break; - - default: // Unknown family 6 CPU, try to guess. - if (Features & (1 << FEATURE_AVX512)) { - *Type = INTEL_XEONPHI; // knl - *Subtype = INTEL_KNIGHTS_LANDING; - break; - } - if (Features & (1 << FEATURE_ADX)) { - *Type = INTEL_COREI7; - *Subtype = INTEL_COREI7_BROADWELL; - break; - } - if (Features & (1 << FEATURE_AVX2)) { - *Type = INTEL_COREI7; - *Subtype = INTEL_COREI7_HASWELL; - break; - } - if (Features & (1 << FEATURE_AVX)) { - *Type = INTEL_COREI7; - *Subtype = INTEL_COREI7_SANDYBRIDGE; - break; - } - if (Features & (1 << FEATURE_SSE4_2)) { - if (Features & (1 << FEATURE_MOVBE)) { - *Type = INTEL_ATOM; - *Subtype = INTEL_ATOM_SILVERMONT; - } else { - *Type = INTEL_COREI7; - *Subtype = INTEL_COREI7_NEHALEM; - } - break; - } - if (Features & (1 << FEATURE_SSE4_1)) { - *Type = INTEL_CORE2; // "penryn" - *Subtype = INTEL_CORE2_45; - break; - } - if (Features & (1 << FEATURE_SSSE3)) { - if (Features & (1 << FEATURE_MOVBE)) { - *Type = INTEL_ATOM; - *Subtype = INTEL_ATOM_BONNELL; // "bonnell" - } else { - *Type = INTEL_CORE2; // "core2" - *Subtype = INTEL_CORE2_65; - } - break; - } - if (Features & (1 << FEATURE_EM64T)) { - *Type = INTEL_X86_64; - break; // x86-64 - } - if (Features & (1 << FEATURE_SSE2)) { - *Type = INTEL_PENTIUM_M; - break; - } - if (Features & (1 << FEATURE_SSE)) { - *Type = INTEL_PENTIUM_III; - break; - } - if (Features & (1 << FEATURE_MMX)) { - *Type = INTEL_PENTIUM_II; - break; - } - *Type = INTEL_PENTIUM_PRO; - break; - } - break; - case 15: { - switch (Model) { - case 0: // Pentium 4 processor, Intel Xeon processor. All processors are - // model 00h and manufactured using the 0.18 micron process. - case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon - // processor MP, and Intel Celeron processor. All processors are - // model 01h and manufactured using the 0.18 micron process. - case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, - // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron - // processor, and Mobile Intel Celeron processor. All processors - // are model 02h and manufactured using the 0.13 micron process. - *Type = - ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); - break; - - case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D - // processor. All processors are model 03h and manufactured using - // the 90 nm process. - case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, - // Pentium D processor, Intel Xeon processor, Intel Xeon - // processor MP, Intel Celeron D processor. All processors are - // model 04h and manufactured using the 90 nm process. - case 6: // Pentium 4 processor, Pentium D processor, Pentium processor - // Extreme Edition, Intel Xeon processor, Intel Xeon processor - // MP, Intel Celeron D processor. All processors are model 06h - // and manufactured using the 65 nm process. - *Type = - ((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT); - break; - - default: - *Type = - ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); - break; - } - break; - } - default: - break; /*"generic"*/ - } -} - -static void getAMDProcessorTypeAndSubtype(unsigned int Family, - unsigned int Model, - unsigned int Features, - unsigned *Type, - unsigned *Subtype) { - // FIXME: this poorly matches the generated SubtargetFeatureKV table. There - // appears to be no way to generate the wide variety of AMD-specific targets - // from the information returned from CPUID. - switch (Family) { - case 4: - *Type = AMD_i486; - break; - case 5: - *Type = AMDPENTIUM; - switch (Model) { - case 6: - case 7: - *Subtype = AMDPENTIUM_K6; - break; // "k6" - case 8: - *Subtype = AMDPENTIUM_K62; - break; // "k6-2" - case 9: - case 13: - *Subtype = AMDPENTIUM_K63; - break; // "k6-3" - case 10: - *Subtype = AMDPENTIUM_GEODE; - break; // "geode" - } - break; - case 6: - *Type = AMDATHLON; - switch (Model) { - case 4: - *Subtype = AMDATHLON_TBIRD; - break; // "athlon-tbird" - case 6: - case 7: - case 8: - *Subtype = AMDATHLON_MP; - break; // "athlon-mp" - case 10: - *Subtype = AMDATHLON_XP; - break; // "athlon-xp" - } - break; - case 15: - *Type = AMDATHLON; - if (Features & (1 << FEATURE_SSE3)) { - *Subtype = AMDATHLON_K8SSE3; - break; // "k8-sse3" - } - switch (Model) { - case 1: - *Subtype = AMDATHLON_OPTERON; - break; // "opteron" - case 5: - *Subtype = AMDATHLON_FX; - break; // "athlon-fx"; also opteron - default: - *Subtype = AMDATHLON_64; - break; // "athlon64" - } - break; - case 16: - *Type = AMDFAM10H; // "amdfam10" - switch (Model) { - case 2: - *Subtype = AMDFAM10H_BARCELONA; - break; - case 4: - *Subtype = AMDFAM10H_SHANGHAI; - break; - case 8: - *Subtype = AMDFAM10H_ISTANBUL; - break; - } - break; - case 20: - *Type = AMDFAM14H; - *Subtype = AMD_BTVER1; - break; // "btver1"; - case 21: - *Type = AMDFAM15H; - if (!(Features & - (1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback. - *Subtype = AMD_BTVER1; - break; // "btver1" - } - if (Model >= 0x50 && Model <= 0x6f) { - *Subtype = AMDFAM15H_BDVER4; - break; // "bdver4"; 50h-6Fh: Excavator - } - if (Model >= 0x30 && Model <= 0x3f) { - *Subtype = AMDFAM15H_BDVER3; - break; // "bdver3"; 30h-3Fh: Steamroller - } - if (Model >= 0x10 && Model <= 0x1f) { - *Subtype = AMDFAM15H_BDVER2; - break; // "bdver2"; 10h-1Fh: Piledriver - } - if (Model <= 0x0f) { - *Subtype = AMDFAM15H_BDVER1; - break; // "bdver1"; 00h-0Fh: Bulldozer - } - break; - case 22: - *Type = AMDFAM16H; - if (!(Features & - (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback. - *Subtype = AMD_BTVER1; - break; // "btver1"; - } - *Subtype = AMD_BTVER2; - break; // "btver2" - case 23: - *Type = AMDFAM17H; - if (Features & (1 << FEATURE_ADX)) { - *Subtype = AMDFAM17H_ZNVER1; - break; // "znver1" - } - *Subtype = AMD_BTVER1; - break; - default: - break; // "generic" - } -} - -static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX, - unsigned MaxLeaf) { - unsigned Features = 0; - unsigned int EAX, EBX; - Features |= (((EDX >> 23) & 1) << FEATURE_MMX); - Features |= (((EDX >> 25) & 1) << FEATURE_SSE); - Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); - Features |= (((ECX >> 0) & 1) << FEATURE_SSE3); - Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3); - Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1); - Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2); - Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE); - - // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV - // indicates that the AVX registers will be saved and restored on context - // switch, then we have full AVX support. - const unsigned AVXBits = (1 << 27) | (1 << 28); - bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && - ((EAX & 0x6) == 0x6); - bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); - bool HasLeaf7 = - MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); - bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); - bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); - bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); - Features |= (HasAVX << FEATURE_AVX); - Features |= (HasAVX2 << FEATURE_AVX2); - Features |= (HasAVX512 << FEATURE_AVX512); - Features |= (HasAVX512Save << FEATURE_AVX512SAVE); - Features |= (HasADX << FEATURE_ADX); - - getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); - Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); - return Features; -} - -StringRef sys::getHostCPUName() { - unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; - unsigned MaxLeaf, Vendor; - -#if defined(__GNUC__) || defined(__clang__) - //FIXME: include cpuid.h from clang or copy __get_cpuid_max here - // and simplify it to not invoke __cpuid (like cpu_model.c in - // compiler-rt/lib/builtins/cpu_model.c? - // Opting for the second option. - if(!isCpuIdSupported()) - return "generic"; -#endif - if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX)) - return "generic"; - if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) - return "generic"; - - unsigned Brand_id = EBX & 0xff; - unsigned Family = 0, Model = 0; - unsigned Features = 0; - detectX86FamilyModel(EAX, &Family, &Model); - Features = getAvailableFeatures(ECX, EDX, MaxLeaf); - - unsigned Type; - unsigned Subtype; - - if (Vendor == SIG_INTEL) { - getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type, - &Subtype); - switch (Type) { - case INTEL_i386: - return "i386"; - case INTEL_i486: - return "i486"; - case INTEL_PENTIUM: - if (Subtype == INTEL_PENTIUM_MMX) - return "pentium-mmx"; - return "pentium"; - case INTEL_PENTIUM_PRO: - return "pentiumpro"; - case INTEL_PENTIUM_II: - return "pentium2"; - case INTEL_PENTIUM_III: - return "pentium3"; - case INTEL_PENTIUM_IV: - return "pentium4"; - case INTEL_PENTIUM_M: - return "pentium-m"; - case INTEL_CORE_DUO: - return "yonah"; - case INTEL_CORE2: - switch (Subtype) { - case INTEL_CORE2_65: - return "core2"; - case INTEL_CORE2_45: - return "penryn"; - default: - return "core2"; - } - case INTEL_COREI7: - switch (Subtype) { - case INTEL_COREI7_NEHALEM: - return "nehalem"; - case INTEL_COREI7_WESTMERE: - return "westmere"; - case INTEL_COREI7_SANDYBRIDGE: - return "sandybridge"; - case INTEL_COREI7_IVYBRIDGE: - return "ivybridge"; - case INTEL_COREI7_HASWELL: - return "haswell"; - case INTEL_COREI7_BROADWELL: - return "broadwell"; - case INTEL_COREI7_SKYLAKE: - return "skylake"; - case INTEL_COREI7_SKYLAKE_AVX512: - return "skylake-avx512"; - default: - return "corei7"; - } - case INTEL_ATOM: - switch (Subtype) { - case INTEL_ATOM_BONNELL: - return "bonnell"; - case INTEL_ATOM_SILVERMONT: - return "silvermont"; - default: - return "atom"; - } - case INTEL_XEONPHI: - return "knl"; /*update for more variants added*/ - case INTEL_X86_64: - return "x86-64"; - case INTEL_NOCONA: - return "nocona"; - case INTEL_PRESCOTT: - return "prescott"; - default: - return "generic"; - } - } else if (Vendor == SIG_AMD) { - getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); - switch (Type) { - case AMD_i486: - return "i486"; - case AMDPENTIUM: - switch (Subtype) { - case AMDPENTIUM_K6: - return "k6"; - case AMDPENTIUM_K62: - return "k6-2"; - case AMDPENTIUM_K63: - return "k6-3"; - case AMDPENTIUM_GEODE: - return "geode"; - default: - return "pentium"; - } - case AMDATHLON: - switch (Subtype) { - case AMDATHLON_TBIRD: - return "athlon-tbird"; - case AMDATHLON_MP: - return "athlon-mp"; - case AMDATHLON_XP: - return "athlon-xp"; - case AMDATHLON_K8SSE3: - return "k8-sse3"; - case AMDATHLON_OPTERON: - return "opteron"; - case AMDATHLON_FX: - return "athlon-fx"; - case AMDATHLON_64: - return "athlon64"; - default: - return "athlon"; - } - case AMDFAM10H: - if(Subtype == AMDFAM10H_BARCELONA) - return "barcelona"; - return "amdfam10"; - case AMDFAM14H: - return "btver1"; - case AMDFAM15H: - switch (Subtype) { - case AMDFAM15H_BDVER1: - return "bdver1"; - case AMDFAM15H_BDVER2: - return "bdver2"; - case AMDFAM15H_BDVER3: - return "bdver3"; - case AMDFAM15H_BDVER4: - return "bdver4"; - case AMD_BTVER1: - return "btver1"; - default: - return "amdfam15"; - } - case AMDFAM16H: - switch (Subtype) { - case AMD_BTVER1: - return "btver1"; - case AMD_BTVER2: - return "btver2"; - default: - return "amdfam16"; - } - case AMDFAM17H: - switch (Subtype) { - case AMD_BTVER1: - return "btver1"; - case AMDFAM17H_ZNVER1: - return "znver1"; - default: - return "amdfam17"; - } - default: - return "generic"; - } - } - return "generic"; -} - -#elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) -StringRef sys::getHostCPUName() { - host_basic_info_data_t hostInfo; - mach_msg_type_number_t infoCount; - - infoCount = HOST_BASIC_INFO_COUNT; - host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, - &infoCount); - - if (hostInfo.cpu_type != CPU_TYPE_POWERPC) - return "generic"; - - switch (hostInfo.cpu_subtype) { - case CPU_SUBTYPE_POWERPC_601: - return "601"; - case CPU_SUBTYPE_POWERPC_602: - return "602"; - case CPU_SUBTYPE_POWERPC_603: - return "603"; - case CPU_SUBTYPE_POWERPC_603e: - return "603e"; - case CPU_SUBTYPE_POWERPC_603ev: - return "603ev"; - case CPU_SUBTYPE_POWERPC_604: - return "604"; - case CPU_SUBTYPE_POWERPC_604e: - return "604e"; - case CPU_SUBTYPE_POWERPC_620: - return "620"; - case CPU_SUBTYPE_POWERPC_750: - return "750"; - case CPU_SUBTYPE_POWERPC_7400: - return "7400"; - case CPU_SUBTYPE_POWERPC_7450: - return "7450"; - case CPU_SUBTYPE_POWERPC_970: - return "970"; - default:; - } - - return "generic"; -} -#elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) -StringRef sys::getHostCPUName() { - std::unique_ptr P = getProcCpuinfoContent(); - const StringRef& Content = P ? P->getBuffer() : ""; - return detail::getHostCPUNameForPowerPC(Content); -} -#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) -StringRef sys::getHostCPUName() { - std::unique_ptr P = getProcCpuinfoContent(); - const StringRef& Content = P ? P->getBuffer() : ""; - return detail::getHostCPUNameForARM(Content); -} -#elif defined(__linux__) && defined(__s390x__) -StringRef sys::getHostCPUName() { - std::unique_ptr P = getProcCpuinfoContent(); - const StringRef& Content = P ? P->getBuffer() : ""; - return detail::getHostCPUNameForS390x(Content); -} -#else -StringRef sys::getHostCPUName() { return "generic"; } -#endif - -#if defined(__linux__) && defined(__x86_64__) -// On Linux, the number of physical cores can be computed from /proc/cpuinfo, -// using the number of unique physical/core id pairs. The following -// implementation reads the /proc/cpuinfo format on an x86_64 system. -static int computeHostNumPhysicalCores() { - // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be - // mmapped because it appears to have 0 size. - llvm::ErrorOr> Text = - llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); - if (std::error_code EC = Text.getError()) { - llvm::errs() << "Can't read " - << "/proc/cpuinfo: " << EC.message() << "\n"; - return -1; - } - SmallVector strs; - (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, - /*KeepEmpty=*/false); - int CurPhysicalId = -1; - int CurCoreId = -1; - SmallSet, 32> UniqueItems; - for (auto &Line : strs) { - Line = Line.trim(); - if (!Line.startswith("physical id") && !Line.startswith("core id")) - continue; - std::pair Data = Line.split(':'); - auto Name = Data.first.trim(); - auto Val = Data.second.trim(); - if (Name == "physical id") { - assert(CurPhysicalId == -1 && - "Expected a core id before seeing another physical id"); - Val.getAsInteger(10, CurPhysicalId); - } - if (Name == "core id") { - assert(CurCoreId == -1 && - "Expected a physical id before seeing another core id"); - Val.getAsInteger(10, CurCoreId); - } - if (CurPhysicalId != -1 && CurCoreId != -1) { - UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); - CurPhysicalId = -1; - CurCoreId = -1; - } - } - return UniqueItems.size(); -} -#elif defined(__APPLE__) && defined(__x86_64__) -#include -#include - -// Gets the number of *physical cores* on the machine. -static int computeHostNumPhysicalCores() { - uint32_t count; - size_t len = sizeof(count); - sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); - if (count < 1) { - int nm[2]; - nm[0] = CTL_HW; - nm[1] = HW_AVAILCPU; - sysctl(nm, 2, &count, &len, NULL, 0); - if (count < 1) - return -1; - } - return count; -} -#else -// On other systems, return -1 to indicate unknown. -static int computeHostNumPhysicalCores() { return -1; } -#endif - -int sys::getHostNumPhysicalCores() { - static int NumCores = computeHostNumPhysicalCores(); - return NumCores; -} - -#if defined(__i386__) || defined(_M_IX86) || \ - defined(__x86_64__) || defined(_M_X64) -bool sys::getHostCPUFeatures(StringMap &Features) { - unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; - unsigned MaxLevel; - union { - unsigned u[3]; - char c[12]; - } text; - - if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || - MaxLevel < 1) - return false; - - getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); - - Features["cmov"] = (EDX >> 15) & 1; - Features["mmx"] = (EDX >> 23) & 1; - Features["sse"] = (EDX >> 25) & 1; - Features["sse2"] = (EDX >> 26) & 1; - Features["sse3"] = (ECX >> 0) & 1; - Features["ssse3"] = (ECX >> 9) & 1; - Features["sse4.1"] = (ECX >> 19) & 1; - Features["sse4.2"] = (ECX >> 20) & 1; - - Features["pclmul"] = (ECX >> 1) & 1; - Features["cx16"] = (ECX >> 13) & 1; - Features["movbe"] = (ECX >> 22) & 1; - Features["popcnt"] = (ECX >> 23) & 1; - Features["aes"] = (ECX >> 25) & 1; - Features["rdrnd"] = (ECX >> 30) & 1; - - // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV - // indicates that the AVX registers will be saved and restored on context - // switch, then we have full AVX support. - bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && - !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); - Features["avx"] = HasAVXSave; - Features["fma"] = HasAVXSave && (ECX >> 12) & 1; - Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; - - // Only enable XSAVE if OS has enabled support for saving YMM state. - Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; - - // AVX512 requires additional context to be saved by the OS. - bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); - - unsigned MaxExtLevel; - getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); - - bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && - !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); - Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); - Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); - Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); - Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; - Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; - Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); - Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); - - bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && - !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX); - Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); - - bool HasLeaf7 = - MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); - - // AVX2 is only supported if we have the OS save support from AVX. - Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); - - Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); - Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); - Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); - Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); - Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); - Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); - Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); - Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); - Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); - Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); - - // AVX512 is only supported if the OS supports the context save for it. - Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; - Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; - Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; - Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; - Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; - Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; - Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; - Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; - - Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); - Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; - // Enable protection keys - Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); - - bool HasLeafD = MaxLevel >= 0xd && - !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); - - // Only enable XSAVE if OS has enabled support for saving YMM state. - Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); - Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); - Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); - - return true; -} -#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) -bool sys::getHostCPUFeatures(StringMap &Features) { - std::unique_ptr P = getProcCpuinfoContent(); - if (!P) - return false; - - SmallVector Lines; - P->getBuffer().split(Lines, "\n"); - - SmallVector CPUFeatures; - - // Look for the CPU features. - for (unsigned I = 0, E = Lines.size(); I != E; ++I) - if (Lines[I].startswith("Features")) { - Lines[I].split(CPUFeatures, ' '); - break; - } - -#if defined(__aarch64__) - // Keep track of which crypto features we have seen - enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; - uint32_t crypto = 0; -#endif - - for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { - StringRef LLVMFeatureStr = StringSwitch(CPUFeatures[I]) -#if defined(__aarch64__) - .Case("asimd", "neon") - .Case("fp", "fp-armv8") - .Case("crc32", "crc") -#else - .Case("half", "fp16") - .Case("neon", "neon") - .Case("vfpv3", "vfp3") - .Case("vfpv3d16", "d16") - .Case("vfpv4", "vfp4") - .Case("idiva", "hwdiv-arm") - .Case("idivt", "hwdiv") -#endif - .Default(""); - -#if defined(__aarch64__) - // We need to check crypto separately since we need all of the crypto - // extensions to enable the subtarget feature - if (CPUFeatures[I] == "aes") - crypto |= CAP_AES; - else if (CPUFeatures[I] == "pmull") - crypto |= CAP_PMULL; - else if (CPUFeatures[I] == "sha1") - crypto |= CAP_SHA1; - else if (CPUFeatures[I] == "sha2") - crypto |= CAP_SHA2; -#endif - - if (LLVMFeatureStr != "") - Features[LLVMFeatureStr] = true; - } - -#if defined(__aarch64__) - // If we have all crypto bits we can add the feature - if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) - Features["crypto"] = true; -#endif - - return true; -} -#else -bool sys::getHostCPUFeatures(StringMap &Features) { return false; } -#endif - -std::string sys::getProcessTriple() { - Triple PT(Triple::normalize(LLVM_HOST_TRIPLE)); - - if (sizeof(void *) == 8 && PT.isArch32Bit()) - PT = PT.get64BitArchVariant(); - if (sizeof(void *) == 4 && PT.isArch64Bit()) - PT = PT.get32BitArchVariant(); - - return PT.str(); -} +//===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the operating system Host concept. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Support/Host.h" +#include "llvm/ADT/SmallSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/StringSwitch.h" +#include "llvm/ADT/Triple.h" +#include "llvm/Config/config.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/raw_ostream.h" +#include +#include + +// Include the platform-specific parts of this class. +#ifdef LLVM_ON_UNIX +#include "Unix/Host.inc" +#endif +#ifdef LLVM_ON_WIN32 +#include "Windows/Host.inc" +#endif +#ifdef _MSC_VER +#include +#endif +#if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) +#include +#include +#include +#include +#endif + +#define DEBUG_TYPE "host-detection" + +//===----------------------------------------------------------------------===// +// +// Implementations of the CPU detection routines +// +//===----------------------------------------------------------------------===// + +using namespace llvm; + +static std::unique_ptr + LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { + llvm::ErrorOr> Text = + llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); + if (std::error_code EC = Text.getError()) { + llvm::errs() << "Can't read " + << "/proc/cpuinfo: " << EC.message() << "\n"; + return nullptr; + } + return std::move(*Text); +} + +StringRef sys::detail::getHostCPUNameForPowerPC( + const StringRef &ProcCpuinfoContent) { + // Access to the Processor Version Register (PVR) on PowerPC is privileged, + // and so we must use an operating-system interface to determine the current + // processor type. On Linux, this is exposed through the /proc/cpuinfo file. + const char *generic = "generic"; + + // The cpu line is second (after the 'processor: 0' line), so if this + // buffer is too small then something has changed (or is wrong). + StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); + StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); + + StringRef::const_iterator CIP = CPUInfoStart; + + StringRef::const_iterator CPUStart = 0; + size_t CPULen = 0; + + // We need to find the first line which starts with cpu, spaces, and a colon. + // After the colon, there may be some additional spaces and then the cpu type. + while (CIP < CPUInfoEnd && CPUStart == 0) { + if (CIP < CPUInfoEnd && *CIP == '\n') + ++CIP; + + if (CIP < CPUInfoEnd && *CIP == 'c') { + ++CIP; + if (CIP < CPUInfoEnd && *CIP == 'p') { + ++CIP; + if (CIP < CPUInfoEnd && *CIP == 'u') { + ++CIP; + while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) + ++CIP; + + if (CIP < CPUInfoEnd && *CIP == ':') { + ++CIP; + while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) + ++CIP; + + if (CIP < CPUInfoEnd) { + CPUStart = CIP; + while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && + *CIP != ',' && *CIP != '\n')) + ++CIP; + CPULen = CIP - CPUStart; + } + } + } + } + } + + if (CPUStart == 0) + while (CIP < CPUInfoEnd && *CIP != '\n') + ++CIP; + } + + if (CPUStart == 0) + return generic; + + return StringSwitch(StringRef(CPUStart, CPULen)) + .Case("604e", "604e") + .Case("604", "604") + .Case("7400", "7400") + .Case("7410", "7400") + .Case("7447", "7400") + .Case("7455", "7450") + .Case("G4", "g4") + .Case("POWER4", "970") + .Case("PPC970FX", "970") + .Case("PPC970MP", "970") + .Case("G5", "g5") + .Case("POWER5", "g5") + .Case("A2", "a2") + .Case("POWER6", "pwr6") + .Case("POWER7", "pwr7") + .Case("POWER8", "pwr8") + .Case("POWER8E", "pwr8") + .Case("POWER8NVL", "pwr8") + .Case("POWER9", "pwr9") + .Default(generic); +} + +StringRef sys::detail::getHostCPUNameForARM( + const StringRef &ProcCpuinfoContent) { + // The cpuid register on arm is not accessible from user space. On Linux, + // it is exposed through the /proc/cpuinfo file. + + // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line + // in all cases. + SmallVector Lines; + ProcCpuinfoContent.split(Lines, "\n"); + + // Look for the CPU implementer line. + StringRef Implementer; + StringRef Hardware; + for (unsigned I = 0, E = Lines.size(); I != E; ++I) { + if (Lines[I].startswith("CPU implementer")) + Implementer = Lines[I].substr(15).ltrim("\t :"); + if (Lines[I].startswith("Hardware")) + Hardware = Lines[I].substr(8).ltrim("\t :"); + } + + if (Implementer == "0x41") { // ARM Ltd. + // MSM8992/8994 may give cpu part for the core that the kernel is running on, + // which is undeterministic and wrong. Always return cortex-a53 for these SoC. + if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) + return "cortex-a53"; + + + // Look for the CPU part line. + for (unsigned I = 0, E = Lines.size(); I != E; ++I) + if (Lines[I].startswith("CPU part")) + // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The + // values correspond to the "Part number" in the CP15/c0 register. The + // contents are specified in the various processor manuals. + return StringSwitch(Lines[I].substr(8).ltrim("\t :")) + .Case("0x926", "arm926ej-s") + .Case("0xb02", "mpcore") + .Case("0xb36", "arm1136j-s") + .Case("0xb56", "arm1156t2-s") + .Case("0xb76", "arm1176jz-s") + .Case("0xc08", "cortex-a8") + .Case("0xc09", "cortex-a9") + .Case("0xc0f", "cortex-a15") + .Case("0xc20", "cortex-m0") + .Case("0xc23", "cortex-m3") + .Case("0xc24", "cortex-m4") + .Case("0xd04", "cortex-a35") + .Case("0xd03", "cortex-a53") + .Case("0xd07", "cortex-a57") + .Case("0xd08", "cortex-a72") + .Case("0xd09", "cortex-a73") + .Default("generic"); + } + + if (Implementer == "0x51") // Qualcomm Technologies, Inc. + // Look for the CPU part line. + for (unsigned I = 0, E = Lines.size(); I != E; ++I) + if (Lines[I].startswith("CPU part")) + // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The + // values correspond to the "Part number" in the CP15/c0 register. The + // contents are specified in the various processor manuals. + return StringSwitch(Lines[I].substr(8).ltrim("\t :")) + .Case("0x06f", "krait") // APQ8064 + .Case("0x201", "kryo") + .Case("0x205", "kryo") + .Default("generic"); + + return "generic"; +} + +StringRef sys::detail::getHostCPUNameForS390x( + const StringRef &ProcCpuinfoContent) { + // STIDP is a privileged operation, so use /proc/cpuinfo instead. + + // The "processor 0:" line comes after a fair amount of other information, + // including a cache breakdown, but this should be plenty. + SmallVector Lines; + ProcCpuinfoContent.split(Lines, "\n"); + + // Look for the CPU features. + SmallVector CPUFeatures; + for (unsigned I = 0, E = Lines.size(); I != E; ++I) + if (Lines[I].startswith("features")) { + size_t Pos = Lines[I].find(":"); + if (Pos != StringRef::npos) { + Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); + break; + } + } + + // We need to check for the presence of vector support independently of + // the machine type, since we may only use the vector register set when + // supported by the kernel (and hypervisor). + bool HaveVectorSupport = false; + for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { + if (CPUFeatures[I] == "vx") + HaveVectorSupport = true; + } + + // Now check the processor machine type. + for (unsigned I = 0, E = Lines.size(); I != E; ++I) { + if (Lines[I].startswith("processor ")) { + size_t Pos = Lines[I].find("machine = "); + if (Pos != StringRef::npos) { + Pos += sizeof("machine = ") - 1; + unsigned int Id; + if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { + if (Id >= 2964 && HaveVectorSupport) + return "z13"; + if (Id >= 2827) + return "zEC12"; + if (Id >= 2817) + return "z196"; + } + } + break; + } + } + + return "generic"; +} + +#if defined(__i386__) || defined(_M_IX86) || \ + defined(__x86_64__) || defined(_M_X64) + +enum VendorSignatures { + SIG_INTEL = 0x756e6547 /* Genu */, + SIG_AMD = 0x68747541 /* Auth */ +}; + +enum ProcessorVendors { + VENDOR_INTEL = 1, + VENDOR_AMD, + VENDOR_OTHER, + VENDOR_MAX +}; + +enum ProcessorTypes { + INTEL_ATOM = 1, + INTEL_CORE2, + INTEL_COREI7, + AMDFAM10H, + AMDFAM15H, + INTEL_i386, + INTEL_i486, + INTEL_PENTIUM, + INTEL_PENTIUM_PRO, + INTEL_PENTIUM_II, + INTEL_PENTIUM_III, + INTEL_PENTIUM_IV, + INTEL_PENTIUM_M, + INTEL_CORE_DUO, + INTEL_XEONPHI, + INTEL_X86_64, + INTEL_NOCONA, + INTEL_PRESCOTT, + AMD_i486, + AMDPENTIUM, + AMDATHLON, + AMDFAM14H, + AMDFAM16H, + AMDFAM17H, + CPU_TYPE_MAX +}; + +enum ProcessorSubtypes { + INTEL_COREI7_NEHALEM = 1, + INTEL_COREI7_WESTMERE, + INTEL_COREI7_SANDYBRIDGE, + AMDFAM10H_BARCELONA, + AMDFAM10H_SHANGHAI, + AMDFAM10H_ISTANBUL, + AMDFAM15H_BDVER1, + AMDFAM15H_BDVER2, + INTEL_PENTIUM_MMX, + INTEL_CORE2_65, + INTEL_CORE2_45, + INTEL_COREI7_IVYBRIDGE, + INTEL_COREI7_HASWELL, + INTEL_COREI7_BROADWELL, + INTEL_COREI7_SKYLAKE, + INTEL_COREI7_SKYLAKE_AVX512, + INTEL_ATOM_BONNELL, + INTEL_ATOM_SILVERMONT, + INTEL_KNIGHTS_LANDING, + AMDPENTIUM_K6, + AMDPENTIUM_K62, + AMDPENTIUM_K63, + AMDPENTIUM_GEODE, + AMDATHLON_TBIRD, + AMDATHLON_MP, + AMDATHLON_XP, + AMDATHLON_K8SSE3, + AMDATHLON_OPTERON, + AMDATHLON_FX, + AMDATHLON_64, + AMD_BTVER1, + AMD_BTVER2, + AMDFAM15H_BDVER3, + AMDFAM15H_BDVER4, + AMDFAM17H_ZNVER1, + CPU_SUBTYPE_MAX +}; + +enum ProcessorFeatures { + FEATURE_CMOV = 0, + FEATURE_MMX, + FEATURE_POPCNT, + FEATURE_SSE, + FEATURE_SSE2, + FEATURE_SSE3, + FEATURE_SSSE3, + FEATURE_SSE4_1, + FEATURE_SSE4_2, + FEATURE_AVX, + FEATURE_AVX2, + FEATURE_AVX512, + FEATURE_AVX512SAVE, + FEATURE_MOVBE, + FEATURE_ADX, + FEATURE_EM64T +}; + +// The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). +// Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID +// support. Consequently, for i386, the presence of CPUID is checked first +// via the corresponding eflags bit. +// Removal of cpuid.h header motivated by PR30384 +// Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp +// or test-suite, but are used in external projects e.g. libstdcxx +static bool isCpuIdSupported() { +#if defined(__GNUC__) || defined(__clang__) +#if defined(__i386__) + int __cpuid_supported; + __asm__(" pushfl\n" + " popl %%eax\n" + " movl %%eax,%%ecx\n" + " xorl $0x00200000,%%eax\n" + " pushl %%eax\n" + " popfl\n" + " pushfl\n" + " popl %%eax\n" + " movl $0,%0\n" + " cmpl %%eax,%%ecx\n" + " je 1f\n" + " movl $1,%0\n" + "1:" + : "=r"(__cpuid_supported) + : + : "eax", "ecx"); + if (!__cpuid_supported) + return false; +#endif + return true; +#endif + return true; +} + +/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in +/// the specified arguments. If we can't run cpuid on the host, return true. +static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, + unsigned *rECX, unsigned *rEDX) { +#if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) +#if defined(__GNUC__) || defined(__clang__) +#if defined(__x86_64__) + // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. + // FIXME: should we save this for Clang? + __asm__("movq\t%%rbx, %%rsi\n\t" + "cpuid\n\t" + "xchgq\t%%rbx, %%rsi\n\t" + : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) + : "a"(value)); +#elif defined(__i386__) + __asm__("movl\t%%ebx, %%esi\n\t" + "cpuid\n\t" + "xchgl\t%%ebx, %%esi\n\t" + : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) + : "a"(value)); +#else + assert(0 && "This method is defined only for x86."); +#endif +#elif defined(_MSC_VER) + // The MSVC intrinsic is portable across x86 and x64. + int registers[4]; + __cpuid(registers, value); + *rEAX = registers[0]; + *rEBX = registers[1]; + *rECX = registers[2]; + *rEDX = registers[3]; +#endif + return false; +#else + return true; +#endif +} + +/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return +/// the 4 values in the specified arguments. If we can't run cpuid on the host, +/// return true. +static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, + unsigned *rEAX, unsigned *rEBX, unsigned *rECX, + unsigned *rEDX) { +#if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER) +#if defined(__x86_64__) || defined(_M_X64) +#if defined(__GNUC__) || defined(__clang__) + // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. + // FIXME: should we save this for Clang? + __asm__("movq\t%%rbx, %%rsi\n\t" + "cpuid\n\t" + "xchgq\t%%rbx, %%rsi\n\t" + : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) + : "a"(value), "c"(subleaf)); +#elif defined(_MSC_VER) + int registers[4]; + __cpuidex(registers, value, subleaf); + *rEAX = registers[0]; + *rEBX = registers[1]; + *rECX = registers[2]; + *rEDX = registers[3]; +#endif +#elif defined(__i386__) || defined(_M_IX86) +#if defined(__GNUC__) || defined(__clang__) + __asm__("movl\t%%ebx, %%esi\n\t" + "cpuid\n\t" + "xchgl\t%%ebx, %%esi\n\t" + : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) + : "a"(value), "c"(subleaf)); +#elif defined(_MSC_VER) + __asm { + mov eax,value + mov ecx,subleaf + cpuid + mov esi,rEAX + mov dword ptr [esi],eax + mov esi,rEBX + mov dword ptr [esi],ebx + mov esi,rECX + mov dword ptr [esi],ecx + mov esi,rEDX + mov dword ptr [esi],edx + } +#endif +#else + assert(0 && "This method is defined only for x86."); +#endif + return false; +#else + return true; +#endif +} + +static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { +#if defined(__GNUC__) || defined(__clang__) + // Check xgetbv; this uses a .byte sequence instead of the instruction + // directly because older assemblers do not include support for xgetbv and + // there is no easy way to conditionally compile based on the assembler used. + __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); + return false; +#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) + unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); + *rEAX = Result; + *rEDX = Result >> 32; + return false; +#else + return true; +#endif +} + +static void detectX86FamilyModel(unsigned EAX, unsigned *Family, + unsigned *Model) { + *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 + *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 + if (*Family == 6 || *Family == 0xf) { + if (*Family == 0xf) + // Examine extended family ID if family ID is F. + *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 + // Examine extended model ID if family ID is 6 or F. + *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 + } +} + +static void +getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model, + unsigned int Brand_id, unsigned int Features, + unsigned *Type, unsigned *Subtype) { + if (Brand_id != 0) + return; + switch (Family) { + case 3: + *Type = INTEL_i386; + break; + case 4: + switch (Model) { + case 0: // Intel486 DX processors + case 1: // Intel486 DX processors + case 2: // Intel486 SX processors + case 3: // Intel487 processors, IntelDX2 OverDrive processors, + // IntelDX2 processors + case 4: // Intel486 SL processor + case 5: // IntelSX2 processors + case 7: // Write-Back Enhanced IntelDX2 processors + case 8: // IntelDX4 OverDrive processors, IntelDX4 processors + default: + *Type = INTEL_i486; + break; + } + break; + case 5: + switch (Model) { + case 1: // Pentium OverDrive processor for Pentium processor (60, 66), + // Pentium processors (60, 66) + case 2: // Pentium OverDrive processor for Pentium processor (75, 90, + // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, + // 150, 166, 200) + case 3: // Pentium OverDrive processors for Intel486 processor-based + // systems + *Type = INTEL_PENTIUM; + break; + case 4: // Pentium OverDrive processor with MMX technology for Pentium + // processor (75, 90, 100, 120, 133), Pentium processor with + // MMX technology (166, 200) + *Type = INTEL_PENTIUM; + *Subtype = INTEL_PENTIUM_MMX; + break; + default: + *Type = INTEL_PENTIUM; + break; + } + break; + case 6: + switch (Model) { + case 0x01: // Pentium Pro processor + *Type = INTEL_PENTIUM_PRO; + break; + case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, + // model 03 + case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, + // model 05, and Intel Celeron processor, model 05 + case 0x06: // Celeron processor, model 06 + *Type = INTEL_PENTIUM_II; + break; + case 0x07: // Pentium III processor, model 07, and Pentium III Xeon + // processor, model 07 + case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, + // model 08, and Celeron processor, model 08 + case 0x0a: // Pentium III Xeon processor, model 0Ah + case 0x0b: // Pentium III processor, model 0Bh + *Type = INTEL_PENTIUM_III; + break; + case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. + case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model + // 0Dh. All processors are manufactured using the 90 nm process. + case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 + // Integrated Processor with Intel QuickAssist Technology + *Type = INTEL_PENTIUM_M; + break; + case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model + // 0Eh. All processors are manufactured using the 65 nm process. + *Type = INTEL_CORE_DUO; + break; // yonah + case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile + // processor, Intel Core 2 Quad processor, Intel Core 2 Quad + // mobile processor, Intel Core 2 Extreme processor, Intel + // Pentium Dual-Core processor, Intel Xeon processor, model + // 0Fh. All processors are manufactured using the 65 nm process. + case 0x16: // Intel Celeron processor model 16h. All processors are + // manufactured using the 65 nm process + *Type = INTEL_CORE2; // "core2" + *Subtype = INTEL_CORE2_65; + break; + case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model + // 17h. All processors are manufactured using the 45 nm process. + // + // 45nm: Penryn , Wolfdale, Yorkfield (XE) + case 0x1d: // Intel Xeon processor MP. All processors are manufactured using + // the 45 nm process. + *Type = INTEL_CORE2; // "penryn" + *Subtype = INTEL_CORE2_45; + break; + case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All + // processors are manufactured using the 45 nm process. + case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. + // As found in a Summer 2010 model iMac. + case 0x1f: + case 0x2e: // Nehalem EX + *Type = INTEL_COREI7; // "nehalem" + *Subtype = INTEL_COREI7_NEHALEM; + break; + case 0x25: // Intel Core i7, laptop version. + case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All + // processors are manufactured using the 32 nm process. + case 0x2f: // Westmere EX + *Type = INTEL_COREI7; // "westmere" + *Subtype = INTEL_COREI7_WESTMERE; + break; + case 0x2a: // Intel Core i7 processor. All processors are manufactured + // using the 32 nm process. + case 0x2d: + *Type = INTEL_COREI7; //"sandybridge" + *Subtype = INTEL_COREI7_SANDYBRIDGE; + break; + case 0x3a: + case 0x3e: // Ivy Bridge EP + *Type = INTEL_COREI7; // "ivybridge" + *Subtype = INTEL_COREI7_IVYBRIDGE; + break; + + // Haswell: + case 0x3c: + case 0x3f: + case 0x45: + case 0x46: + *Type = INTEL_COREI7; // "haswell" + *Subtype = INTEL_COREI7_HASWELL; + break; + + // Broadwell: + case 0x3d: + case 0x47: + case 0x4f: + case 0x56: + *Type = INTEL_COREI7; // "broadwell" + *Subtype = INTEL_COREI7_BROADWELL; + break; + + // Skylake: + case 0x4e: // Skylake mobile + case 0x5e: // Skylake desktop + case 0x8e: // Kaby Lake mobile + case 0x9e: // Kaby Lake desktop + *Type = INTEL_COREI7; // "skylake" + *Subtype = INTEL_COREI7_SKYLAKE; + break; + + // Skylake Xeon: + case 0x55: + *Type = INTEL_COREI7; + // Check that we really have AVX512 + if (Features & (1 << FEATURE_AVX512)) { + *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" + } else { + *Subtype = INTEL_COREI7_SKYLAKE; // "skylake" + } + break; + + case 0x1c: // Most 45 nm Intel Atom processors + case 0x26: // 45 nm Atom Lincroft + case 0x27: // 32 nm Atom Medfield + case 0x35: // 32 nm Atom Midview + case 0x36: // 32 nm Atom Midview + *Type = INTEL_ATOM; + *Subtype = INTEL_ATOM_BONNELL; + break; // "bonnell" + + // Atom Silvermont codes from the Intel software optimization guide. + case 0x37: + case 0x4a: + case 0x4d: + case 0x5a: + case 0x5d: + case 0x4c: // really airmont + *Type = INTEL_ATOM; + *Subtype = INTEL_ATOM_SILVERMONT; + break; // "silvermont" + + case 0x57: + *Type = INTEL_XEONPHI; // knl + *Subtype = INTEL_KNIGHTS_LANDING; + break; + + default: // Unknown family 6 CPU, try to guess. + if (Features & (1 << FEATURE_AVX512)) { + *Type = INTEL_XEONPHI; // knl + *Subtype = INTEL_KNIGHTS_LANDING; + break; + } + if (Features & (1 << FEATURE_ADX)) { + *Type = INTEL_COREI7; + *Subtype = INTEL_COREI7_BROADWELL; + break; + } + if (Features & (1 << FEATURE_AVX2)) { + *Type = INTEL_COREI7; + *Subtype = INTEL_COREI7_HASWELL; + break; + } + if (Features & (1 << FEATURE_AVX)) { + *Type = INTEL_COREI7; + *Subtype = INTEL_COREI7_SANDYBRIDGE; + break; + } + if (Features & (1 << FEATURE_SSE4_2)) { + if (Features & (1 << FEATURE_MOVBE)) { + *Type = INTEL_ATOM; + *Subtype = INTEL_ATOM_SILVERMONT; + } else { + *Type = INTEL_COREI7; + *Subtype = INTEL_COREI7_NEHALEM; + } + break; + } + if (Features & (1 << FEATURE_SSE4_1)) { + *Type = INTEL_CORE2; // "penryn" + *Subtype = INTEL_CORE2_45; + break; + } + if (Features & (1 << FEATURE_SSSE3)) { + if (Features & (1 << FEATURE_MOVBE)) { + *Type = INTEL_ATOM; + *Subtype = INTEL_ATOM_BONNELL; // "bonnell" + } else { + *Type = INTEL_CORE2; // "core2" + *Subtype = INTEL_CORE2_65; + } + break; + } + if (Features & (1 << FEATURE_EM64T)) { + *Type = INTEL_X86_64; + break; // x86-64 + } + if (Features & (1 << FEATURE_SSE2)) { + *Type = INTEL_PENTIUM_M; + break; + } + if (Features & (1 << FEATURE_SSE)) { + *Type = INTEL_PENTIUM_III; + break; + } + if (Features & (1 << FEATURE_MMX)) { + *Type = INTEL_PENTIUM_II; + break; + } + *Type = INTEL_PENTIUM_PRO; + break; + } + break; + case 15: { + switch (Model) { + case 0: // Pentium 4 processor, Intel Xeon processor. All processors are + // model 00h and manufactured using the 0.18 micron process. + case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon + // processor MP, and Intel Celeron processor. All processors are + // model 01h and manufactured using the 0.18 micron process. + case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, + // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron + // processor, and Mobile Intel Celeron processor. All processors + // are model 02h and manufactured using the 0.13 micron process. + *Type = + ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); + break; + + case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D + // processor. All processors are model 03h and manufactured using + // the 90 nm process. + case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, + // Pentium D processor, Intel Xeon processor, Intel Xeon + // processor MP, Intel Celeron D processor. All processors are + // model 04h and manufactured using the 90 nm process. + case 6: // Pentium 4 processor, Pentium D processor, Pentium processor + // Extreme Edition, Intel Xeon processor, Intel Xeon processor + // MP, Intel Celeron D processor. All processors are model 06h + // and manufactured using the 65 nm process. + *Type = + ((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT); + break; + + default: + *Type = + ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV); + break; + } + break; + } + default: + break; /*"generic"*/ + } +} + +static void getAMDProcessorTypeAndSubtype(unsigned int Family, + unsigned int Model, + unsigned int Features, + unsigned *Type, + unsigned *Subtype) { + // FIXME: this poorly matches the generated SubtargetFeatureKV table. There + // appears to be no way to generate the wide variety of AMD-specific targets + // from the information returned from CPUID. + switch (Family) { + case 4: + *Type = AMD_i486; + break; + case 5: + *Type = AMDPENTIUM; + switch (Model) { + case 6: + case 7: + *Subtype = AMDPENTIUM_K6; + break; // "k6" + case 8: + *Subtype = AMDPENTIUM_K62; + break; // "k6-2" + case 9: + case 13: + *Subtype = AMDPENTIUM_K63; + break; // "k6-3" + case 10: + *Subtype = AMDPENTIUM_GEODE; + break; // "geode" + } + break; + case 6: + *Type = AMDATHLON; + switch (Model) { + case 4: + *Subtype = AMDATHLON_TBIRD; + break; // "athlon-tbird" + case 6: + case 7: + case 8: + *Subtype = AMDATHLON_MP; + break; // "athlon-mp" + case 10: + *Subtype = AMDATHLON_XP; + break; // "athlon-xp" + } + break; + case 15: + *Type = AMDATHLON; + if (Features & (1 << FEATURE_SSE3)) { + *Subtype = AMDATHLON_K8SSE3; + break; // "k8-sse3" + } + switch (Model) { + case 1: + *Subtype = AMDATHLON_OPTERON; + break; // "opteron" + case 5: + *Subtype = AMDATHLON_FX; + break; // "athlon-fx"; also opteron + default: + *Subtype = AMDATHLON_64; + break; // "athlon64" + } + break; + case 16: + *Type = AMDFAM10H; // "amdfam10" + switch (Model) { + case 2: + *Subtype = AMDFAM10H_BARCELONA; + break; + case 4: + *Subtype = AMDFAM10H_SHANGHAI; + break; + case 8: + *Subtype = AMDFAM10H_ISTANBUL; + break; + } + break; + case 20: + *Type = AMDFAM14H; + *Subtype = AMD_BTVER1; + break; // "btver1"; + case 21: + *Type = AMDFAM15H; + if (!(Features & + (1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback. + *Subtype = AMD_BTVER1; + break; // "btver1" + } + if (Model >= 0x50 && Model <= 0x6f) { + *Subtype = AMDFAM15H_BDVER4; + break; // "bdver4"; 50h-6Fh: Excavator + } + if (Model >= 0x30 && Model <= 0x3f) { + *Subtype = AMDFAM15H_BDVER3; + break; // "bdver3"; 30h-3Fh: Steamroller + } + if (Model >= 0x10 && Model <= 0x1f) { + *Subtype = AMDFAM15H_BDVER2; + break; // "bdver2"; 10h-1Fh: Piledriver + } + if (Model <= 0x0f) { + *Subtype = AMDFAM15H_BDVER1; + break; // "bdver1"; 00h-0Fh: Bulldozer + } + break; + case 22: + *Type = AMDFAM16H; + if (!(Features & + (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback. + *Subtype = AMD_BTVER1; + break; // "btver1"; + } + *Subtype = AMD_BTVER2; + break; // "btver2" + case 23: + *Type = AMDFAM17H; + if (Features & (1 << FEATURE_ADX)) { + *Subtype = AMDFAM17H_ZNVER1; + break; // "znver1" + } + *Subtype = AMD_BTVER1; + break; + default: + break; // "generic" + } +} + +static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX, + unsigned MaxLeaf) { + unsigned Features = 0; + unsigned int EAX, EBX; + Features |= (((EDX >> 23) & 1) << FEATURE_MMX); + Features |= (((EDX >> 25) & 1) << FEATURE_SSE); + Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); + Features |= (((ECX >> 0) & 1) << FEATURE_SSE3); + Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3); + Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1); + Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2); + Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE); + + // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV + // indicates that the AVX registers will be saved and restored on context + // switch, then we have full AVX support. + const unsigned AVXBits = (1 << 27) | (1 << 28); + bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && + ((EAX & 0x6) == 0x6); + bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); + bool HasLeaf7 = + MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); + bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); + bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); + bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); + Features |= (HasAVX << FEATURE_AVX); + Features |= (HasAVX2 << FEATURE_AVX2); + Features |= (HasAVX512 << FEATURE_AVX512); + Features |= (HasAVX512Save << FEATURE_AVX512SAVE); + Features |= (HasADX << FEATURE_ADX); + + getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); + Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); + return Features; +} + +StringRef sys::getHostCPUName() { + unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; + unsigned MaxLeaf, Vendor; + +#if defined(__GNUC__) || defined(__clang__) + //FIXME: include cpuid.h from clang or copy __get_cpuid_max here + // and simplify it to not invoke __cpuid (like cpu_model.c in + // compiler-rt/lib/builtins/cpu_model.c? + // Opting for the second option. + if(!isCpuIdSupported()) + return "generic"; +#endif + if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX)) + return "generic"; + if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) + return "generic"; + + unsigned Brand_id = EBX & 0xff; + unsigned Family = 0, Model = 0; + unsigned Features = 0; + detectX86FamilyModel(EAX, &Family, &Model); + Features = getAvailableFeatures(ECX, EDX, MaxLeaf); + + unsigned Type; + unsigned Subtype; + + if (Vendor == SIG_INTEL) { + getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type, + &Subtype); + switch (Type) { + case INTEL_i386: + return "i386"; + case INTEL_i486: + return "i486"; + case INTEL_PENTIUM: + if (Subtype == INTEL_PENTIUM_MMX) + return "pentium-mmx"; + return "pentium"; + case INTEL_PENTIUM_PRO: + return "pentiumpro"; + case INTEL_PENTIUM_II: + return "pentium2"; + case INTEL_PENTIUM_III: + return "pentium3"; + case INTEL_PENTIUM_IV: + return "pentium4"; + case INTEL_PENTIUM_M: + return "pentium-m"; + case INTEL_CORE_DUO: + return "yonah"; + case INTEL_CORE2: + switch (Subtype) { + case INTEL_CORE2_65: + return "core2"; + case INTEL_CORE2_45: + return "penryn"; + default: + return "core2"; + } + case INTEL_COREI7: + switch (Subtype) { + case INTEL_COREI7_NEHALEM: + return "nehalem"; + case INTEL_COREI7_WESTMERE: + return "westmere"; + case INTEL_COREI7_SANDYBRIDGE: + return "sandybridge"; + case INTEL_COREI7_IVYBRIDGE: + return "ivybridge"; + case INTEL_COREI7_HASWELL: + return "haswell"; + case INTEL_COREI7_BROADWELL: + return "broadwell"; + case INTEL_COREI7_SKYLAKE: + return "skylake"; + case INTEL_COREI7_SKYLAKE_AVX512: + return "skylake-avx512"; + default: + return "corei7"; + } + case INTEL_ATOM: + switch (Subtype) { + case INTEL_ATOM_BONNELL: + return "bonnell"; + case INTEL_ATOM_SILVERMONT: + return "silvermont"; + default: + return "atom"; + } + case INTEL_XEONPHI: + return "knl"; /*update for more variants added*/ + case INTEL_X86_64: + return "x86-64"; + case INTEL_NOCONA: + return "nocona"; + case INTEL_PRESCOTT: + return "prescott"; + default: + return "generic"; + } + } else if (Vendor == SIG_AMD) { + getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); + switch (Type) { + case AMD_i486: + return "i486"; + case AMDPENTIUM: + switch (Subtype) { + case AMDPENTIUM_K6: + return "k6"; + case AMDPENTIUM_K62: + return "k6-2"; + case AMDPENTIUM_K63: + return "k6-3"; + case AMDPENTIUM_GEODE: + return "geode"; + default: + return "pentium"; + } + case AMDATHLON: + switch (Subtype) { + case AMDATHLON_TBIRD: + return "athlon-tbird"; + case AMDATHLON_MP: + return "athlon-mp"; + case AMDATHLON_XP: + return "athlon-xp"; + case AMDATHLON_K8SSE3: + return "k8-sse3"; + case AMDATHLON_OPTERON: + return "opteron"; + case AMDATHLON_FX: + return "athlon-fx"; + case AMDATHLON_64: + return "athlon64"; + default: + return "athlon"; + } + case AMDFAM10H: + if(Subtype == AMDFAM10H_BARCELONA) + return "barcelona"; + return "amdfam10"; + case AMDFAM14H: + return "btver1"; + case AMDFAM15H: + switch (Subtype) { + case AMDFAM15H_BDVER1: + return "bdver1"; + case AMDFAM15H_BDVER2: + return "bdver2"; + case AMDFAM15H_BDVER3: + return "bdver3"; + case AMDFAM15H_BDVER4: + return "bdver4"; + case AMD_BTVER1: + return "btver1"; + default: + return "amdfam15"; + } + case AMDFAM16H: + switch (Subtype) { + case AMD_BTVER1: + return "btver1"; + case AMD_BTVER2: + return "btver2"; + default: + return "amdfam16"; + } + case AMDFAM17H: + switch (Subtype) { + case AMD_BTVER1: + return "btver1"; + case AMDFAM17H_ZNVER1: + return "znver1"; + default: + return "amdfam17"; + } + default: + return "generic"; + } + } + return "generic"; +} + +#elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) +StringRef sys::getHostCPUName() { + host_basic_info_data_t hostInfo; + mach_msg_type_number_t infoCount; + + infoCount = HOST_BASIC_INFO_COUNT; + host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, + &infoCount); + + if (hostInfo.cpu_type != CPU_TYPE_POWERPC) + return "generic"; + + switch (hostInfo.cpu_subtype) { + case CPU_SUBTYPE_POWERPC_601: + return "601"; + case CPU_SUBTYPE_POWERPC_602: + return "602"; + case CPU_SUBTYPE_POWERPC_603: + return "603"; + case CPU_SUBTYPE_POWERPC_603e: + return "603e"; + case CPU_SUBTYPE_POWERPC_603ev: + return "603ev"; + case CPU_SUBTYPE_POWERPC_604: + return "604"; + case CPU_SUBTYPE_POWERPC_604e: + return "604e"; + case CPU_SUBTYPE_POWERPC_620: + return "620"; + case CPU_SUBTYPE_POWERPC_750: + return "750"; + case CPU_SUBTYPE_POWERPC_7400: + return "7400"; + case CPU_SUBTYPE_POWERPC_7450: + return "7450"; + case CPU_SUBTYPE_POWERPC_970: + return "970"; + default:; + } + + return "generic"; +} +#elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) +StringRef sys::getHostCPUName() { + std::unique_ptr P = getProcCpuinfoContent(); + const StringRef& Content = P ? P->getBuffer() : ""; + return detail::getHostCPUNameForPowerPC(Content); +} +#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) +StringRef sys::getHostCPUName() { + std::unique_ptr P = getProcCpuinfoContent(); + const StringRef& Content = P ? P->getBuffer() : ""; + return detail::getHostCPUNameForARM(Content); +} +#elif defined(__linux__) && defined(__s390x__) +StringRef sys::getHostCPUName() { + std::unique_ptr P = getProcCpuinfoContent(); + const StringRef& Content = P ? P->getBuffer() : ""; + return detail::getHostCPUNameForS390x(Content); +} +#else +StringRef sys::getHostCPUName() { return "generic"; } +#endif + +#if defined(__linux__) && defined(__x86_64__) +// On Linux, the number of physical cores can be computed from /proc/cpuinfo, +// using the number of unique physical/core id pairs. The following +// implementation reads the /proc/cpuinfo format on an x86_64 system. +static int computeHostNumPhysicalCores() { + // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be + // mmapped because it appears to have 0 size. + llvm::ErrorOr> Text = + llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); + if (std::error_code EC = Text.getError()) { + llvm::errs() << "Can't read " + << "/proc/cpuinfo: " << EC.message() << "\n"; + return -1; + } + SmallVector strs; + (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, + /*KeepEmpty=*/false); + int CurPhysicalId = -1; + int CurCoreId = -1; + SmallSet, 32> UniqueItems; + for (auto &Line : strs) { + Line = Line.trim(); + if (!Line.startswith("physical id") && !Line.startswith("core id")) + continue; + std::pair Data = Line.split(':'); + auto Name = Data.first.trim(); + auto Val = Data.second.trim(); + if (Name == "physical id") { + assert(CurPhysicalId == -1 && + "Expected a core id before seeing another physical id"); + Val.getAsInteger(10, CurPhysicalId); + } + if (Name == "core id") { + assert(CurCoreId == -1 && + "Expected a physical id before seeing another core id"); + Val.getAsInteger(10, CurCoreId); + } + if (CurPhysicalId != -1 && CurCoreId != -1) { + UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); + CurPhysicalId = -1; + CurCoreId = -1; + } + } + return UniqueItems.size(); +} +#elif defined(__APPLE__) && defined(__x86_64__) +#include +#include + +// Gets the number of *physical cores* on the machine. +static int computeHostNumPhysicalCores() { + uint32_t count; + size_t len = sizeof(count); + sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); + if (count < 1) { + int nm[2]; + nm[0] = CTL_HW; + nm[1] = HW_AVAILCPU; + sysctl(nm, 2, &count, &len, NULL, 0); + if (count < 1) + return -1; + } + return count; +} +#else +// On other systems, return -1 to indicate unknown. +static int computeHostNumPhysicalCores() { return -1; } +#endif + +int sys::getHostNumPhysicalCores() { + static int NumCores = computeHostNumPhysicalCores(); + return NumCores; +} + +#if defined(__i386__) || defined(_M_IX86) || \ + defined(__x86_64__) || defined(_M_X64) +bool sys::getHostCPUFeatures(StringMap &Features) { + unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; + unsigned MaxLevel; + union { + unsigned u[3]; + char c[12]; + } text; + + if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || + MaxLevel < 1) + return false; + + getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); + + Features["cmov"] = (EDX >> 15) & 1; + Features["mmx"] = (EDX >> 23) & 1; + Features["sse"] = (EDX >> 25) & 1; + Features["sse2"] = (EDX >> 26) & 1; + Features["sse3"] = (ECX >> 0) & 1; + Features["ssse3"] = (ECX >> 9) & 1; + Features["sse4.1"] = (ECX >> 19) & 1; + Features["sse4.2"] = (ECX >> 20) & 1; + + Features["pclmul"] = (ECX >> 1) & 1; + Features["cx16"] = (ECX >> 13) & 1; + Features["movbe"] = (ECX >> 22) & 1; + Features["popcnt"] = (ECX >> 23) & 1; + Features["aes"] = (ECX >> 25) & 1; + Features["rdrnd"] = (ECX >> 30) & 1; + + // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV + // indicates that the AVX registers will be saved and restored on context + // switch, then we have full AVX support. + bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && + !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); + Features["avx"] = HasAVXSave; + Features["fma"] = HasAVXSave && (ECX >> 12) & 1; + Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; + + // Only enable XSAVE if OS has enabled support for saving YMM state. + Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; + + // AVX512 requires additional context to be saved by the OS. + bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); + + unsigned MaxExtLevel; + getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); + + bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && + !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); + Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); + Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); + Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); + Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; + Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); + Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; + Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); + Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); + + bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && + !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX); + Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); + + bool HasLeaf7 = + MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); + + // AVX2 is only supported if we have the OS save support from AVX. + Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); + + Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); + Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); + Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); + Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); + Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); + Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); + Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); + Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); + Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); + Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); + + // AVX512 is only supported if the OS supports the context save for it. + Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; + Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; + Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; + Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; + Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; + Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; + Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; + Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; + + Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); + Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; + // Enable protection keys + Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); + + bool HasLeafD = MaxLevel >= 0xd && + !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); + + // Only enable XSAVE if OS has enabled support for saving YMM state. + Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); + Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); + Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); + + return true; +} +#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) +bool sys::getHostCPUFeatures(StringMap &Features) { + std::unique_ptr P = getProcCpuinfoContent(); + if (!P) + return false; + + SmallVector Lines; + P->getBuffer().split(Lines, "\n"); + + SmallVector CPUFeatures; + + // Look for the CPU features. + for (unsigned I = 0, E = Lines.size(); I != E; ++I) + if (Lines[I].startswith("Features")) { + Lines[I].split(CPUFeatures, ' '); + break; + } + +#if defined(__aarch64__) + // Keep track of which crypto features we have seen + enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; + uint32_t crypto = 0; +#endif + + for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { + StringRef LLVMFeatureStr = StringSwitch(CPUFeatures[I]) +#if defined(__aarch64__) + .Case("asimd", "neon") + .Case("fp", "fp-armv8") + .Case("crc32", "crc") +#else + .Case("half", "fp16") + .Case("neon", "neon") + .Case("vfpv3", "vfp3") + .Case("vfpv3d16", "d16") + .Case("vfpv4", "vfp4") + .Case("idiva", "hwdiv-arm") + .Case("idivt", "hwdiv") +#endif + .Default(""); + +#if defined(__aarch64__) + // We need to check crypto separately since we need all of the crypto + // extensions to enable the subtarget feature + if (CPUFeatures[I] == "aes") + crypto |= CAP_AES; + else if (CPUFeatures[I] == "pmull") + crypto |= CAP_PMULL; + else if (CPUFeatures[I] == "sha1") + crypto |= CAP_SHA1; + else if (CPUFeatures[I] == "sha2") + crypto |= CAP_SHA2; +#endif + + if (LLVMFeatureStr != "") + Features[LLVMFeatureStr] = true; + } + +#if defined(__aarch64__) + // If we have all crypto bits we can add the feature + if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) + Features["crypto"] = true; +#endif + + return true; +} +#else +bool sys::getHostCPUFeatures(StringMap &Features) { return false; } +#endif + +std::string sys::getProcessTriple() { + Triple PT(Triple::normalize(LLVM_HOST_TRIPLE)); + + if (sizeof(void *) == 8 && PT.isArch32Bit()) + PT = PT.get64BitArchVariant(); + if (sizeof(void *) == 4 && PT.isArch64Bit()) + PT = PT.get32BitArchVariant(); + + return PT.str(); +} Index: llvm/trunk/lib/Target/X86/X86.td =================================================================== --- llvm/trunk/lib/Target/X86/X86.td +++ llvm/trunk/lib/Target/X86/X86.td @@ -170,6 +170,8 @@ [FeatureSSE2]>; def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", "Enable TBM instructions">; +def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", + "Enable LWP instructions">; def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", "Support MOVBE instruction">; def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", @@ -691,6 +693,7 @@ FeatureLZCNT, FeaturePOPCNT, FeatureXSAVE, + FeatureLWP, FeatureSlowSHLD, FeatureLAHFSAHF ]>; @@ -713,6 +716,7 @@ FeatureXSAVE, FeatureBMI, FeatureTBM, + FeatureLWP, FeatureFMA, FeatureSlowSHLD, FeatureLAHFSAHF @@ -737,6 +741,7 @@ FeatureXSAVE, FeatureBMI, FeatureTBM, + FeatureLWP, FeatureFMA, FeatureXSAVEOPT, FeatureSlowSHLD, @@ -763,6 +768,7 @@ FeatureBMI, FeatureBMI2, FeatureTBM, + FeatureLWP, FeatureFMA, FeatureXSAVEOPT, FeatureSlowSHLD, Index: llvm/trunk/lib/Target/X86/X86ISelLowering.h =================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h @@ -559,6 +559,9 @@ // Conversions between float and half-float. CVTPS2PH, CVTPH2PS, + // LWP insert record. + LWPINS, + // Compare and swap. LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, LCMPXCHG8_DAG, Index: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp @@ -20318,6 +20318,19 @@ // during ExpandISelPseudos in EmitInstrWithCustomInserter. return SDValue(); } + case Intrinsic::x86_lwpins32: + case Intrinsic::x86_lwpins64: { + SDLoc dl(Op); + SDValue Chain = Op->getOperand(0); + SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); + SDValue LwpIns = + DAG.getNode(X86ISD::LWPINS, dl, VTs, Chain, Op->getOperand(2), + Op->getOperand(3), Op->getOperand(4)); + SDValue SetCC = getSETCC(X86::COND_B, LwpIns.getValue(0), dl, DAG); + SDValue Result = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, SetCC); + return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, + LwpIns.getValue(1)); + } } return SDValue(); } @@ -24494,6 +24507,7 @@ case X86ISD::CVTP2UI_RND: return "X86ISD::CVTP2UI_RND"; case X86ISD::CVTS2SI_RND: return "X86ISD::CVTS2SI_RND"; case X86ISD::CVTS2UI_RND: return "X86ISD::CVTS2UI_RND"; + case X86ISD::LWPINS: return "X86ISD::LWPINS"; } return nullptr; } Index: llvm/trunk/lib/Target/X86/X86InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td @@ -283,6 +283,11 @@ def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; +def X86lwpins : SDNode<"X86ISD::LWPINS", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; + //===----------------------------------------------------------------------===// // X86 Operand Definitions. // @@ -836,6 +841,7 @@ def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; def HasXOP : Predicate<"Subtarget->hasXOP()">; def HasTBM : Predicate<"Subtarget->hasTBM()">; +def HasLWP : Predicate<"Subtarget->hasLWP()">; def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; def HasF16C : Predicate<"Subtarget->hasF16C()">; @@ -2444,6 +2450,59 @@ } // HasTBM, EFLAGS //===----------------------------------------------------------------------===// +// Lightweight Profiling Instructions + +let Predicates = [HasLWP] in { + +def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR32:$src)], IIC_LWP>, + XOP, XOP9, Requires<[Not64BitMode]>; +def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", + [(set GR32:$dst, (int_x86_slwpcb))], IIC_LWP>, + XOP, XOP9, Requires<[Not64BitMode]>; + +def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR64:$src)], IIC_LWP>, + XOP, XOP9, VEX_W, Requires<[In64BitMode]>; +def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", + [(set GR64:$dst, (int_x86_slwpcb))], IIC_LWP>, + XOP, XOP9, VEX_W, Requires<[In64BitMode]>; + +multiclass lwpins_intr { + def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))]>, + XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), imm:$cntl))]>, + XOP_4V, XOPA; +} + +let Defs = [EFLAGS] in { + defm LWPINS32 : lwpins_intr; + defm LWPINS64 : lwpins_intr, VEX_W; +} // EFLAGS + +multiclass lwpval_intr { + def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, GR32:$src1, imm:$cntl)], IIC_LWP>, + XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, (loadi32 addr:$src1), imm:$cntl)], IIC_LWP>, + XOP_4V, XOPA; +} + +defm LWPVAL32 : lwpval_intr; +defm LWPVAL64 : lwpval_intr, VEX_W; + +} // HasLWP + +//===----------------------------------------------------------------------===// // MONITORX/MWAITX Instructions // let SchedRW = [ WriteSystem ] in { Index: llvm/trunk/lib/Target/X86/X86Schedule.td =================================================================== --- llvm/trunk/lib/Target/X86/X86Schedule.td +++ llvm/trunk/lib/Target/X86/X86Schedule.td @@ -1,662 +1,663 @@ -//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -// InstrSchedModel annotations for out-of-order CPUs. -// -// These annotations are independent of the itinerary classes defined below. - -// Instructions with folded loads need to read the memory operand immediately, -// but other register operands don't have to be read until the load is ready. -// These operands are marked with ReadAfterLd. -def ReadAfterLd : SchedRead; - -// Instructions with both a load and a store folded are modeled as a folded -// load + WriteRMW. -def WriteRMW : SchedWrite; - -// Most instructions can fold loads, so almost every SchedWrite comes in two -// variants: With and without a folded load. -// An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite -// with a folded load. -class X86FoldableSchedWrite : SchedWrite { - // The SchedWrite to use when a load is folded into the instruction. - SchedWrite Folded; -} - -// Multiclass that produces a linked pair of SchedWrites. -multiclass X86SchedWritePair { - // Register-Memory operation. - def Ld : SchedWrite; - // Register-Register operation. - def NAME : X86FoldableSchedWrite { - let Folded = !cast(NAME#"Ld"); - } -} - -// Arithmetic. -defm WriteALU : X86SchedWritePair; // Simple integer ALU op. -defm WriteIMul : X86SchedWritePair; // Integer multiplication. -def WriteIMulH : SchedWrite; // Integer multiplication, high part. -defm WriteIDiv : X86SchedWritePair; // Integer division. -def WriteLEA : SchedWrite; // LEA instructions can't fold loads. - -// Integer shifts and rotates. -defm WriteShift : X86SchedWritePair; - -// Loads, stores, and moves, not folded with other operations. -def WriteLoad : SchedWrite; -def WriteStore : SchedWrite; -def WriteMove : SchedWrite; - -// Idioms that clear a register, like xorps %xmm0, %xmm0. -// These can often bypass execution ports completely. -def WriteZero : SchedWrite; - -// Branches don't produce values, so they have no latency, but they still -// consume resources. Indirect branches can fold loads. -defm WriteJump : X86SchedWritePair; - -// Floating point. This covers both scalar and vector operations. -defm WriteFAdd : X86SchedWritePair; // Floating point add/sub/compare. -defm WriteFMul : X86SchedWritePair; // Floating point multiplication. -defm WriteFDiv : X86SchedWritePair; // Floating point division. -defm WriteFSqrt : X86SchedWritePair; // Floating point square root. -defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal estimate. -defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate. -defm WriteFMA : X86SchedWritePair; // Fused Multiply Add. -defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles. -defm WriteFBlend : X86SchedWritePair; // Floating point vector blends. -defm WriteFVarBlend : X86SchedWritePair; // Fp vector variable blends. - -// FMA Scheduling helper class. -class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } - -// Vector integer operations. -defm WriteVecALU : X86SchedWritePair; // Vector integer ALU op, no logicals. -defm WriteVecShift : X86SchedWritePair; // Vector integer shifts. -defm WriteVecIMul : X86SchedWritePair; // Vector integer multiply. -defm WriteShuffle : X86SchedWritePair; // Vector shuffles. -defm WriteBlend : X86SchedWritePair; // Vector blends. -defm WriteVarBlend : X86SchedWritePair; // Vector variable blends. -defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD. - -// Vector bitwise operations. -// These are often used on both floating point and integer vectors. -defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor. - -// Conversion between integer and float. -defm WriteCvtF2I : X86SchedWritePair; // Float -> Integer. -defm WriteCvtI2F : X86SchedWritePair; // Integer -> Float. -defm WriteCvtF2F : X86SchedWritePair; // Float -> Float size conversion. - -// Strings instructions. -// Packed Compare Implicit Length Strings, Return Mask -defm WritePCmpIStrM : X86SchedWritePair; -// Packed Compare Explicit Length Strings, Return Mask -defm WritePCmpEStrM : X86SchedWritePair; -// Packed Compare Implicit Length Strings, Return Index -defm WritePCmpIStrI : X86SchedWritePair; -// Packed Compare Explicit Length Strings, Return Index -defm WritePCmpEStrI : X86SchedWritePair; - -// AES instructions. -defm WriteAESDecEnc : X86SchedWritePair; // Decryption, encryption. -defm WriteAESIMC : X86SchedWritePair; // InvMixColumn. -defm WriteAESKeyGen : X86SchedWritePair; // Key Generation. - -// Carry-less multiplication instructions. -defm WriteCLMul : X86SchedWritePair; - -// Catch-all for expensive system instructions. -def WriteSystem : SchedWrite; - -// AVX2. -defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles. -defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles. -defm WriteVarVecShift : X86SchedWritePair; // Variable vector shifts. - -// Old microcoded instructions that nobody use. -def WriteMicrocoded : SchedWrite; - -// Fence instructions. -def WriteFence : SchedWrite; - -// Nop, not very useful expect it provides a model for nops! -def WriteNop : SchedWrite; - -//===----------------------------------------------------------------------===// -// Instruction Itinerary classes used for X86 -def IIC_ALU_MEM : InstrItinClass; -def IIC_ALU_NONMEM : InstrItinClass; -def IIC_LEA : InstrItinClass; -def IIC_LEA_16 : InstrItinClass; -def IIC_MUL8 : InstrItinClass; -def IIC_MUL16_MEM : InstrItinClass; -def IIC_MUL16_REG : InstrItinClass; -def IIC_MUL32_MEM : InstrItinClass; -def IIC_MUL32_REG : InstrItinClass; -def IIC_MUL64 : InstrItinClass; -// imul by al, ax, eax, tax -def IIC_IMUL8 : InstrItinClass; -def IIC_IMUL16_MEM : InstrItinClass; -def IIC_IMUL16_REG : InstrItinClass; -def IIC_IMUL32_MEM : InstrItinClass; -def IIC_IMUL32_REG : InstrItinClass; -def IIC_IMUL64 : InstrItinClass; -// imul reg by reg|mem -def IIC_IMUL16_RM : InstrItinClass; -def IIC_IMUL16_RR : InstrItinClass; -def IIC_IMUL32_RM : InstrItinClass; -def IIC_IMUL32_RR : InstrItinClass; -def IIC_IMUL64_RM : InstrItinClass; -def IIC_IMUL64_RR : InstrItinClass; -// imul reg = reg/mem * imm -def IIC_IMUL16_RMI : InstrItinClass; -def IIC_IMUL16_RRI : InstrItinClass; -def IIC_IMUL32_RMI : InstrItinClass; -def IIC_IMUL32_RRI : InstrItinClass; -def IIC_IMUL64_RMI : InstrItinClass; -def IIC_IMUL64_RRI : InstrItinClass; -// div -def IIC_DIV8_MEM : InstrItinClass; -def IIC_DIV8_REG : InstrItinClass; -def IIC_DIV16 : InstrItinClass; -def IIC_DIV32 : InstrItinClass; -def IIC_DIV64 : InstrItinClass; -// idiv -def IIC_IDIV8 : InstrItinClass; -def IIC_IDIV16 : InstrItinClass; -def IIC_IDIV32 : InstrItinClass; -def IIC_IDIV64 : InstrItinClass; -// neg/not/inc/dec -def IIC_UNARY_REG : InstrItinClass; -def IIC_UNARY_MEM : InstrItinClass; -// add/sub/and/or/xor/sbc/cmp/test -def IIC_BIN_MEM : InstrItinClass; -def IIC_BIN_NONMEM : InstrItinClass; -// adc/sbc -def IIC_BIN_CARRY_MEM : InstrItinClass; -def IIC_BIN_CARRY_NONMEM : InstrItinClass; -// shift/rotate -def IIC_SR : InstrItinClass; -// shift double -def IIC_SHD16_REG_IM : InstrItinClass; -def IIC_SHD16_REG_CL : InstrItinClass; -def IIC_SHD16_MEM_IM : InstrItinClass; -def IIC_SHD16_MEM_CL : InstrItinClass; -def IIC_SHD32_REG_IM : InstrItinClass; -def IIC_SHD32_REG_CL : InstrItinClass; -def IIC_SHD32_MEM_IM : InstrItinClass; -def IIC_SHD32_MEM_CL : InstrItinClass; -def IIC_SHD64_REG_IM : InstrItinClass; -def IIC_SHD64_REG_CL : InstrItinClass; -def IIC_SHD64_MEM_IM : InstrItinClass; -def IIC_SHD64_MEM_CL : InstrItinClass; -// cmov -def IIC_CMOV16_RM : InstrItinClass; -def IIC_CMOV16_RR : InstrItinClass; -def IIC_CMOV32_RM : InstrItinClass; -def IIC_CMOV32_RR : InstrItinClass; -def IIC_CMOV64_RM : InstrItinClass; -def IIC_CMOV64_RR : InstrItinClass; -// set -def IIC_SET_R : InstrItinClass; -def IIC_SET_M : InstrItinClass; -// jmp/jcc/jcxz -def IIC_Jcc : InstrItinClass; -def IIC_JCXZ : InstrItinClass; -def IIC_JMP_REL : InstrItinClass; -def IIC_JMP_REG : InstrItinClass; -def IIC_JMP_MEM : InstrItinClass; -def IIC_JMP_FAR_MEM : InstrItinClass; -def IIC_JMP_FAR_PTR : InstrItinClass; -// loop -def IIC_LOOP : InstrItinClass; -def IIC_LOOPE : InstrItinClass; -def IIC_LOOPNE : InstrItinClass; -// call -def IIC_CALL_RI : InstrItinClass; -def IIC_CALL_MEM : InstrItinClass; -def IIC_CALL_FAR_MEM : InstrItinClass; -def IIC_CALL_FAR_PTR : InstrItinClass; -// ret -def IIC_RET : InstrItinClass; -def IIC_RET_IMM : InstrItinClass; -//sign extension movs -def IIC_MOVSX : InstrItinClass; -def IIC_MOVSX_R16_R8 : InstrItinClass; -def IIC_MOVSX_R16_M8 : InstrItinClass; -def IIC_MOVSX_R16_R16 : InstrItinClass; -def IIC_MOVSX_R32_R32 : InstrItinClass; -//zero extension movs -def IIC_MOVZX : InstrItinClass; -def IIC_MOVZX_R16_R8 : InstrItinClass; -def IIC_MOVZX_R16_M8 : InstrItinClass; - -def IIC_REP_MOVS : InstrItinClass; -def IIC_REP_STOS : InstrItinClass; - -// SSE scalar/parallel binary operations -def IIC_SSE_ALU_F32S_RR : InstrItinClass; -def IIC_SSE_ALU_F32S_RM : InstrItinClass; -def IIC_SSE_ALU_F64S_RR : InstrItinClass; -def IIC_SSE_ALU_F64S_RM : InstrItinClass; -def IIC_SSE_MUL_F32S_RR : InstrItinClass; -def IIC_SSE_MUL_F32S_RM : InstrItinClass; -def IIC_SSE_MUL_F64S_RR : InstrItinClass; -def IIC_SSE_MUL_F64S_RM : InstrItinClass; -def IIC_SSE_DIV_F32S_RR : InstrItinClass; -def IIC_SSE_DIV_F32S_RM : InstrItinClass; -def IIC_SSE_DIV_F64S_RR : InstrItinClass; -def IIC_SSE_DIV_F64S_RM : InstrItinClass; -def IIC_SSE_ALU_F32P_RR : InstrItinClass; -def IIC_SSE_ALU_F32P_RM : InstrItinClass; -def IIC_SSE_ALU_F64P_RR : InstrItinClass; -def IIC_SSE_ALU_F64P_RM : InstrItinClass; -def IIC_SSE_MUL_F32P_RR : InstrItinClass; -def IIC_SSE_MUL_F32P_RM : InstrItinClass; -def IIC_SSE_MUL_F64P_RR : InstrItinClass; -def IIC_SSE_MUL_F64P_RM : InstrItinClass; -def IIC_SSE_DIV_F32P_RR : InstrItinClass; -def IIC_SSE_DIV_F32P_RM : InstrItinClass; -def IIC_SSE_DIV_F64P_RR : InstrItinClass; -def IIC_SSE_DIV_F64P_RM : InstrItinClass; - -def IIC_SSE_COMIS_RR : InstrItinClass; -def IIC_SSE_COMIS_RM : InstrItinClass; - -def IIC_SSE_HADDSUB_RR : InstrItinClass; -def IIC_SSE_HADDSUB_RM : InstrItinClass; - -def IIC_SSE_BIT_P_RR : InstrItinClass; -def IIC_SSE_BIT_P_RM : InstrItinClass; - -def IIC_SSE_INTALU_P_RR : InstrItinClass; -def IIC_SSE_INTALU_P_RM : InstrItinClass; -def IIC_SSE_INTALUQ_P_RR : InstrItinClass; -def IIC_SSE_INTALUQ_P_RM : InstrItinClass; - -def IIC_SSE_INTMUL_P_RR : InstrItinClass; -def IIC_SSE_INTMUL_P_RM : InstrItinClass; - -def IIC_SSE_INTSH_P_RR : InstrItinClass; -def IIC_SSE_INTSH_P_RM : InstrItinClass; -def IIC_SSE_INTSH_P_RI : InstrItinClass; - -def IIC_SSE_INTSHDQ_P_RI : InstrItinClass; - -def IIC_SSE_SHUFP : InstrItinClass; -def IIC_SSE_PSHUF_RI : InstrItinClass; -def IIC_SSE_PSHUF_MI : InstrItinClass; - -def IIC_SSE_UNPCK : InstrItinClass; - -def IIC_SSE_MOVMSK : InstrItinClass; -def IIC_SSE_MASKMOV : InstrItinClass; - -def IIC_SSE_PEXTRW : InstrItinClass; -def IIC_SSE_PINSRW : InstrItinClass; - -def IIC_SSE_PABS_RR : InstrItinClass; -def IIC_SSE_PABS_RM : InstrItinClass; - -def IIC_SSE_SQRTPS_RR : InstrItinClass; -def IIC_SSE_SQRTPS_RM : InstrItinClass; -def IIC_SSE_SQRTSS_RR : InstrItinClass; -def IIC_SSE_SQRTSS_RM : InstrItinClass; -def IIC_SSE_SQRTPD_RR : InstrItinClass; -def IIC_SSE_SQRTPD_RM : InstrItinClass; -def IIC_SSE_SQRTSD_RR : InstrItinClass; -def IIC_SSE_SQRTSD_RM : InstrItinClass; - -def IIC_SSE_RSQRTPS_RR : InstrItinClass; -def IIC_SSE_RSQRTPS_RM : InstrItinClass; -def IIC_SSE_RSQRTSS_RR : InstrItinClass; -def IIC_SSE_RSQRTSS_RM : InstrItinClass; - -def IIC_SSE_RCPP_RR : InstrItinClass; -def IIC_SSE_RCPP_RM : InstrItinClass; -def IIC_SSE_RCPS_RR : InstrItinClass; -def IIC_SSE_RCPS_RM : InstrItinClass; - -def IIC_SSE_MOV_S_RR : InstrItinClass; -def IIC_SSE_MOV_S_RM : InstrItinClass; -def IIC_SSE_MOV_S_MR : InstrItinClass; - -def IIC_SSE_MOVA_P_RR : InstrItinClass; -def IIC_SSE_MOVA_P_RM : InstrItinClass; -def IIC_SSE_MOVA_P_MR : InstrItinClass; - -def IIC_SSE_MOVU_P_RR : InstrItinClass; -def IIC_SSE_MOVU_P_RM : InstrItinClass; -def IIC_SSE_MOVU_P_MR : InstrItinClass; - -def IIC_SSE_MOVDQ : InstrItinClass; -def IIC_SSE_MOVD_ToGP : InstrItinClass; -def IIC_SSE_MOVQ_RR : InstrItinClass; - -def IIC_SSE_MOV_LH : InstrItinClass; - -def IIC_SSE_LDDQU : InstrItinClass; - -def IIC_SSE_MOVNT : InstrItinClass; - -def IIC_SSE_PHADDSUBD_RR : InstrItinClass; -def IIC_SSE_PHADDSUBD_RM : InstrItinClass; -def IIC_SSE_PHADDSUBSW_RR : InstrItinClass; -def IIC_SSE_PHADDSUBSW_RM : InstrItinClass; -def IIC_SSE_PHADDSUBW_RR : InstrItinClass; -def IIC_SSE_PHADDSUBW_RM : InstrItinClass; -def IIC_SSE_PSHUFB_RR : InstrItinClass; -def IIC_SSE_PSHUFB_RM : InstrItinClass; -def IIC_SSE_PSIGN_RR : InstrItinClass; -def IIC_SSE_PSIGN_RM : InstrItinClass; - -def IIC_SSE_PMADD : InstrItinClass; -def IIC_SSE_PMULHRSW : InstrItinClass; -def IIC_SSE_PALIGNRR : InstrItinClass; -def IIC_SSE_PALIGNRM : InstrItinClass; -def IIC_SSE_MWAIT : InstrItinClass; -def IIC_SSE_MONITOR : InstrItinClass; -def IIC_SSE_MWAITX : InstrItinClass; -def IIC_SSE_MONITORX : InstrItinClass; -def IIC_SSE_CLZERO : InstrItinClass; - -def IIC_SSE_PREFETCH : InstrItinClass; -def IIC_SSE_PAUSE : InstrItinClass; -def IIC_SSE_LFENCE : InstrItinClass; -def IIC_SSE_MFENCE : InstrItinClass; -def IIC_SSE_SFENCE : InstrItinClass; -def IIC_SSE_LDMXCSR : InstrItinClass; -def IIC_SSE_STMXCSR : InstrItinClass; - -def IIC_SSE_CVT_PD_RR : InstrItinClass; -def IIC_SSE_CVT_PD_RM : InstrItinClass; -def IIC_SSE_CVT_PS_RR : InstrItinClass; -def IIC_SSE_CVT_PS_RM : InstrItinClass; -def IIC_SSE_CVT_PI2PS_RR : InstrItinClass; -def IIC_SSE_CVT_PI2PS_RM : InstrItinClass; -def IIC_SSE_CVT_Scalar_RR : InstrItinClass; -def IIC_SSE_CVT_Scalar_RM : InstrItinClass; -def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass; -def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass; -def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass; -def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass; -def IIC_SSE_CVT_SD2SI_RM : InstrItinClass; -def IIC_SSE_CVT_SD2SI_RR : InstrItinClass; - -// MMX -def IIC_MMX_MOV_MM_RM : InstrItinClass; -def IIC_MMX_MOV_REG_MM : InstrItinClass; -def IIC_MMX_MOVQ_RM : InstrItinClass; -def IIC_MMX_MOVQ_RR : InstrItinClass; - -def IIC_MMX_ALU_RM : InstrItinClass; -def IIC_MMX_ALU_RR : InstrItinClass; -def IIC_MMX_ALUQ_RM : InstrItinClass; -def IIC_MMX_ALUQ_RR : InstrItinClass; -def IIC_MMX_PHADDSUBW_RM : InstrItinClass; -def IIC_MMX_PHADDSUBW_RR : InstrItinClass; -def IIC_MMX_PHADDSUBD_RM : InstrItinClass; -def IIC_MMX_PHADDSUBD_RR : InstrItinClass; -def IIC_MMX_PMUL : InstrItinClass; -def IIC_MMX_MISC_FUNC_MEM : InstrItinClass; -def IIC_MMX_MISC_FUNC_REG : InstrItinClass; -def IIC_MMX_PSADBW : InstrItinClass; -def IIC_MMX_SHIFT_RI : InstrItinClass; -def IIC_MMX_SHIFT_RM : InstrItinClass; -def IIC_MMX_SHIFT_RR : InstrItinClass; -def IIC_MMX_UNPCK_H_RM : InstrItinClass; -def IIC_MMX_UNPCK_H_RR : InstrItinClass; -def IIC_MMX_UNPCK_L : InstrItinClass; -def IIC_MMX_PCK_RM : InstrItinClass; -def IIC_MMX_PCK_RR : InstrItinClass; -def IIC_MMX_PSHUF : InstrItinClass; -def IIC_MMX_PEXTR : InstrItinClass; -def IIC_MMX_PINSRW : InstrItinClass; -def IIC_MMX_MASKMOV : InstrItinClass; - -def IIC_MMX_CVT_PD_RR : InstrItinClass; -def IIC_MMX_CVT_PD_RM : InstrItinClass; -def IIC_MMX_CVT_PS_RR : InstrItinClass; -def IIC_MMX_CVT_PS_RM : InstrItinClass; - -def IIC_CMPX_LOCK : InstrItinClass; -def IIC_CMPX_LOCK_8 : InstrItinClass; -def IIC_CMPX_LOCK_8B : InstrItinClass; -def IIC_CMPX_LOCK_16B : InstrItinClass; - -def IIC_XADD_LOCK_MEM : InstrItinClass; -def IIC_XADD_LOCK_MEM8 : InstrItinClass; - -def IIC_FILD : InstrItinClass; -def IIC_FLD : InstrItinClass; -def IIC_FLD80 : InstrItinClass; -def IIC_FST : InstrItinClass; -def IIC_FST80 : InstrItinClass; -def IIC_FIST : InstrItinClass; -def IIC_FLDZ : InstrItinClass; -def IIC_FUCOM : InstrItinClass; -def IIC_FUCOMI : InstrItinClass; -def IIC_FCOMI : InstrItinClass; -def IIC_FNSTSW : InstrItinClass; -def IIC_FNSTCW : InstrItinClass; -def IIC_FLDCW : InstrItinClass; -def IIC_FNINIT : InstrItinClass; -def IIC_FFREE : InstrItinClass; -def IIC_FNCLEX : InstrItinClass; -def IIC_WAIT : InstrItinClass; -def IIC_FXAM : InstrItinClass; -def IIC_FNOP : InstrItinClass; -def IIC_FLDL : InstrItinClass; -def IIC_F2XM1 : InstrItinClass; -def IIC_FYL2X : InstrItinClass; -def IIC_FPTAN : InstrItinClass; -def IIC_FPATAN : InstrItinClass; -def IIC_FXTRACT : InstrItinClass; -def IIC_FPREM1 : InstrItinClass; -def IIC_FPSTP : InstrItinClass; -def IIC_FPREM : InstrItinClass; -def IIC_FYL2XP1 : InstrItinClass; -def IIC_FSINCOS : InstrItinClass; -def IIC_FRNDINT : InstrItinClass; -def IIC_FSCALE : InstrItinClass; -def IIC_FCOMPP : InstrItinClass; -def IIC_FXSAVE : InstrItinClass; -def IIC_FXRSTOR : InstrItinClass; - -def IIC_FXCH : InstrItinClass; - -// System instructions -def IIC_CPUID : InstrItinClass; -def IIC_INT : InstrItinClass; -def IIC_INT3 : InstrItinClass; -def IIC_INVD : InstrItinClass; -def IIC_INVLPG : InstrItinClass; -def IIC_IRET : InstrItinClass; -def IIC_HLT : InstrItinClass; -def IIC_LXS : InstrItinClass; -def IIC_LTR : InstrItinClass; -def IIC_RDTSC : InstrItinClass; -def IIC_RSM : InstrItinClass; -def IIC_SIDT : InstrItinClass; -def IIC_SGDT : InstrItinClass; -def IIC_SLDT : InstrItinClass; -def IIC_STR : InstrItinClass; -def IIC_SWAPGS : InstrItinClass; -def IIC_SYSCALL : InstrItinClass; -def IIC_SYS_ENTER_EXIT : InstrItinClass; -def IIC_IN_RR : InstrItinClass; -def IIC_IN_RI : InstrItinClass; -def IIC_OUT_RR : InstrItinClass; -def IIC_OUT_IR : InstrItinClass; -def IIC_INS : InstrItinClass; -def IIC_MOV_REG_DR : InstrItinClass; -def IIC_MOV_DR_REG : InstrItinClass; -def IIC_MOV_REG_CR : InstrItinClass; -def IIC_MOV_CR_REG : InstrItinClass; -def IIC_MOV_REG_SR : InstrItinClass; -def IIC_MOV_MEM_SR : InstrItinClass; -def IIC_MOV_SR_REG : InstrItinClass; -def IIC_MOV_SR_MEM : InstrItinClass; -def IIC_LAR_RM : InstrItinClass; -def IIC_LAR_RR : InstrItinClass; -def IIC_LSL_RM : InstrItinClass; -def IIC_LSL_RR : InstrItinClass; -def IIC_LGDT : InstrItinClass; -def IIC_LIDT : InstrItinClass; -def IIC_LLDT_REG : InstrItinClass; -def IIC_LLDT_MEM : InstrItinClass; -def IIC_PUSH_CS : InstrItinClass; -def IIC_PUSH_SR : InstrItinClass; -def IIC_POP_SR : InstrItinClass; -def IIC_POP_SR_SS : InstrItinClass; -def IIC_VERR : InstrItinClass; -def IIC_VERW_REG : InstrItinClass; -def IIC_VERW_MEM : InstrItinClass; -def IIC_WRMSR : InstrItinClass; -def IIC_RDMSR : InstrItinClass; -def IIC_RDPMC : InstrItinClass; -def IIC_SMSW : InstrItinClass; -def IIC_LMSW_REG : InstrItinClass; -def IIC_LMSW_MEM : InstrItinClass; -def IIC_ENTER : InstrItinClass; -def IIC_LEAVE : InstrItinClass; -def IIC_POP_MEM : InstrItinClass; -def IIC_POP_REG16 : InstrItinClass; -def IIC_POP_REG : InstrItinClass; -def IIC_POP_F : InstrItinClass; -def IIC_POP_FD : InstrItinClass; -def IIC_POP_A : InstrItinClass; -def IIC_PUSH_IMM : InstrItinClass; -def IIC_PUSH_MEM : InstrItinClass; -def IIC_PUSH_REG : InstrItinClass; -def IIC_PUSH_F : InstrItinClass; -def IIC_PUSH_A : InstrItinClass; -def IIC_BSWAP : InstrItinClass; -def IIC_BIT_SCAN_MEM : InstrItinClass; -def IIC_BIT_SCAN_REG : InstrItinClass; -def IIC_MOVS : InstrItinClass; -def IIC_STOS : InstrItinClass; -def IIC_SCAS : InstrItinClass; -def IIC_CMPS : InstrItinClass; -def IIC_MOV : InstrItinClass; -def IIC_MOV_MEM : InstrItinClass; -def IIC_AHF : InstrItinClass; -def IIC_BT_MI : InstrItinClass; -def IIC_BT_MR : InstrItinClass; -def IIC_BT_RI : InstrItinClass; -def IIC_BT_RR : InstrItinClass; -def IIC_BTX_MI : InstrItinClass; -def IIC_BTX_MR : InstrItinClass; -def IIC_BTX_RI : InstrItinClass; -def IIC_BTX_RR : InstrItinClass; -def IIC_XCHG_REG : InstrItinClass; -def IIC_XCHG_MEM : InstrItinClass; -def IIC_XADD_REG : InstrItinClass; -def IIC_XADD_MEM : InstrItinClass; -def IIC_CMPXCHG_MEM : InstrItinClass; -def IIC_CMPXCHG_REG : InstrItinClass; -def IIC_CMPXCHG_MEM8 : InstrItinClass; -def IIC_CMPXCHG_REG8 : InstrItinClass; -def IIC_CMPXCHG_8B : InstrItinClass; -def IIC_CMPXCHG_16B : InstrItinClass; -def IIC_LODS : InstrItinClass; -def IIC_OUTS : InstrItinClass; -def IIC_CLC : InstrItinClass; -def IIC_CLD : InstrItinClass; -def IIC_CLI : InstrItinClass; -def IIC_CMC : InstrItinClass; -def IIC_CLTS : InstrItinClass; -def IIC_STC : InstrItinClass; -def IIC_STI : InstrItinClass; -def IIC_STD : InstrItinClass; -def IIC_XLAT : InstrItinClass; -def IIC_AAA : InstrItinClass; -def IIC_AAD : InstrItinClass; -def IIC_AAM : InstrItinClass; -def IIC_AAS : InstrItinClass; -def IIC_DAA : InstrItinClass; -def IIC_DAS : InstrItinClass; -def IIC_BOUND : InstrItinClass; -def IIC_ARPL_REG : InstrItinClass; -def IIC_ARPL_MEM : InstrItinClass; -def IIC_MOVBE : InstrItinClass; -def IIC_AES : InstrItinClass; -def IIC_BLEND_MEM : InstrItinClass; -def IIC_BLEND_NOMEM : InstrItinClass; -def IIC_CBW : InstrItinClass; -def IIC_CRC32_REG : InstrItinClass; -def IIC_CRC32_MEM : InstrItinClass; -def IIC_SSE_DPPD_RR : InstrItinClass; -def IIC_SSE_DPPD_RM : InstrItinClass; -def IIC_SSE_DPPS_RR : InstrItinClass; -def IIC_SSE_DPPS_RM : InstrItinClass; -def IIC_MMX_EMMS : InstrItinClass; -def IIC_SSE_EXTRACTPS_RR : InstrItinClass; -def IIC_SSE_EXTRACTPS_RM : InstrItinClass; -def IIC_SSE_INSERTPS_RR : InstrItinClass; -def IIC_SSE_INSERTPS_RM : InstrItinClass; -def IIC_SSE_MPSADBW_RR : InstrItinClass; -def IIC_SSE_MPSADBW_RM : InstrItinClass; -def IIC_SSE_PMULLD_RR : InstrItinClass; -def IIC_SSE_PMULLD_RM : InstrItinClass; -def IIC_SSE_ROUNDPS_REG : InstrItinClass; -def IIC_SSE_ROUNDPS_MEM : InstrItinClass; -def IIC_SSE_ROUNDPD_REG : InstrItinClass; -def IIC_SSE_ROUNDPD_MEM : InstrItinClass; -def IIC_SSE_POPCNT_RR : InstrItinClass; -def IIC_SSE_POPCNT_RM : InstrItinClass; -def IIC_SSE_PCLMULQDQ_RR : InstrItinClass; -def IIC_SSE_PCLMULQDQ_RM : InstrItinClass; - -def IIC_NOP : InstrItinClass; - -//===----------------------------------------------------------------------===// -// Processor instruction itineraries. - -// IssueWidth is analogous to the number of decode units. Core and its -// descendents, including Nehalem and SandyBridge have 4 decoders. -// Resources beyond the decoder operate on micro-ops and are bufferred -// so adjacent micro-ops don't directly compete. -// -// MicroOpBufferSize > 1 indicates that RAW dependencies can be -// decoded in the same cycle. The value 32 is a reasonably arbitrary -// number of in-flight instructions. -// -// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef -// indicates high latency opcodes. Alternatively, InstrItinData -// entries may be included here to define specific operand -// latencies. Since these latencies are not used for pipeline hazards, -// they do not need to be exact. -// -// The GenericX86Model contains no instruction itineraries -// and disables PostRAScheduler. -class GenericX86Model : SchedMachineModel { - let IssueWidth = 4; - let MicroOpBufferSize = 32; - let LoadLatency = 4; - let HighLatency = 10; - let PostRAScheduler = 0; - let CompleteModel = 0; -} - -def GenericModel : GenericX86Model; - -// Define a model with the PostRAScheduler enabled. -def GenericPostRAModel : GenericX86Model { - let PostRAScheduler = 1; -} - -include "X86ScheduleAtom.td" -include "X86SchedSandyBridge.td" -include "X86SchedHaswell.td" -include "X86ScheduleSLM.td" -include "X86ScheduleBtVer2.td" - +//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +// InstrSchedModel annotations for out-of-order CPUs. +// +// These annotations are independent of the itinerary classes defined below. + +// Instructions with folded loads need to read the memory operand immediately, +// but other register operands don't have to be read until the load is ready. +// These operands are marked with ReadAfterLd. +def ReadAfterLd : SchedRead; + +// Instructions with both a load and a store folded are modeled as a folded +// load + WriteRMW. +def WriteRMW : SchedWrite; + +// Most instructions can fold loads, so almost every SchedWrite comes in two +// variants: With and without a folded load. +// An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite +// with a folded load. +class X86FoldableSchedWrite : SchedWrite { + // The SchedWrite to use when a load is folded into the instruction. + SchedWrite Folded; +} + +// Multiclass that produces a linked pair of SchedWrites. +multiclass X86SchedWritePair { + // Register-Memory operation. + def Ld : SchedWrite; + // Register-Register operation. + def NAME : X86FoldableSchedWrite { + let Folded = !cast(NAME#"Ld"); + } +} + +// Arithmetic. +defm WriteALU : X86SchedWritePair; // Simple integer ALU op. +defm WriteIMul : X86SchedWritePair; // Integer multiplication. +def WriteIMulH : SchedWrite; // Integer multiplication, high part. +defm WriteIDiv : X86SchedWritePair; // Integer division. +def WriteLEA : SchedWrite; // LEA instructions can't fold loads. + +// Integer shifts and rotates. +defm WriteShift : X86SchedWritePair; + +// Loads, stores, and moves, not folded with other operations. +def WriteLoad : SchedWrite; +def WriteStore : SchedWrite; +def WriteMove : SchedWrite; + +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +def WriteZero : SchedWrite; + +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +defm WriteJump : X86SchedWritePair; + +// Floating point. This covers both scalar and vector operations. +defm WriteFAdd : X86SchedWritePair; // Floating point add/sub/compare. +defm WriteFMul : X86SchedWritePair; // Floating point multiplication. +defm WriteFDiv : X86SchedWritePair; // Floating point division. +defm WriteFSqrt : X86SchedWritePair; // Floating point square root. +defm WriteFRcp : X86SchedWritePair; // Floating point reciprocal estimate. +defm WriteFRsqrt : X86SchedWritePair; // Floating point reciprocal square root estimate. +defm WriteFMA : X86SchedWritePair; // Fused Multiply Add. +defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles. +defm WriteFBlend : X86SchedWritePair; // Floating point vector blends. +defm WriteFVarBlend : X86SchedWritePair; // Fp vector variable blends. + +// FMA Scheduling helper class. +class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } + +// Vector integer operations. +defm WriteVecALU : X86SchedWritePair; // Vector integer ALU op, no logicals. +defm WriteVecShift : X86SchedWritePair; // Vector integer shifts. +defm WriteVecIMul : X86SchedWritePair; // Vector integer multiply. +defm WriteShuffle : X86SchedWritePair; // Vector shuffles. +defm WriteBlend : X86SchedWritePair; // Vector blends. +defm WriteVarBlend : X86SchedWritePair; // Vector variable blends. +defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD. + +// Vector bitwise operations. +// These are often used on both floating point and integer vectors. +defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor. + +// Conversion between integer and float. +defm WriteCvtF2I : X86SchedWritePair; // Float -> Integer. +defm WriteCvtI2F : X86SchedWritePair; // Integer -> Float. +defm WriteCvtF2F : X86SchedWritePair; // Float -> Float size conversion. + +// Strings instructions. +// Packed Compare Implicit Length Strings, Return Mask +defm WritePCmpIStrM : X86SchedWritePair; +// Packed Compare Explicit Length Strings, Return Mask +defm WritePCmpEStrM : X86SchedWritePair; +// Packed Compare Implicit Length Strings, Return Index +defm WritePCmpIStrI : X86SchedWritePair; +// Packed Compare Explicit Length Strings, Return Index +defm WritePCmpEStrI : X86SchedWritePair; + +// AES instructions. +defm WriteAESDecEnc : X86SchedWritePair; // Decryption, encryption. +defm WriteAESIMC : X86SchedWritePair; // InvMixColumn. +defm WriteAESKeyGen : X86SchedWritePair; // Key Generation. + +// Carry-less multiplication instructions. +defm WriteCLMul : X86SchedWritePair; + +// Catch-all for expensive system instructions. +def WriteSystem : SchedWrite; + +// AVX2. +defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles. +defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles. +defm WriteVarVecShift : X86SchedWritePair; // Variable vector shifts. + +// Old microcoded instructions that nobody use. +def WriteMicrocoded : SchedWrite; + +// Fence instructions. +def WriteFence : SchedWrite; + +// Nop, not very useful expect it provides a model for nops! +def WriteNop : SchedWrite; + +//===----------------------------------------------------------------------===// +// Instruction Itinerary classes used for X86 +def IIC_ALU_MEM : InstrItinClass; +def IIC_ALU_NONMEM : InstrItinClass; +def IIC_LEA : InstrItinClass; +def IIC_LEA_16 : InstrItinClass; +def IIC_MUL8 : InstrItinClass; +def IIC_MUL16_MEM : InstrItinClass; +def IIC_MUL16_REG : InstrItinClass; +def IIC_MUL32_MEM : InstrItinClass; +def IIC_MUL32_REG : InstrItinClass; +def IIC_MUL64 : InstrItinClass; +// imul by al, ax, eax, tax +def IIC_IMUL8 : InstrItinClass; +def IIC_IMUL16_MEM : InstrItinClass; +def IIC_IMUL16_REG : InstrItinClass; +def IIC_IMUL32_MEM : InstrItinClass; +def IIC_IMUL32_REG : InstrItinClass; +def IIC_IMUL64 : InstrItinClass; +// imul reg by reg|mem +def IIC_IMUL16_RM : InstrItinClass; +def IIC_IMUL16_RR : InstrItinClass; +def IIC_IMUL32_RM : InstrItinClass; +def IIC_IMUL32_RR : InstrItinClass; +def IIC_IMUL64_RM : InstrItinClass; +def IIC_IMUL64_RR : InstrItinClass; +// imul reg = reg/mem * imm +def IIC_IMUL16_RMI : InstrItinClass; +def IIC_IMUL16_RRI : InstrItinClass; +def IIC_IMUL32_RMI : InstrItinClass; +def IIC_IMUL32_RRI : InstrItinClass; +def IIC_IMUL64_RMI : InstrItinClass; +def IIC_IMUL64_RRI : InstrItinClass; +// div +def IIC_DIV8_MEM : InstrItinClass; +def IIC_DIV8_REG : InstrItinClass; +def IIC_DIV16 : InstrItinClass; +def IIC_DIV32 : InstrItinClass; +def IIC_DIV64 : InstrItinClass; +// idiv +def IIC_IDIV8 : InstrItinClass; +def IIC_IDIV16 : InstrItinClass; +def IIC_IDIV32 : InstrItinClass; +def IIC_IDIV64 : InstrItinClass; +// neg/not/inc/dec +def IIC_UNARY_REG : InstrItinClass; +def IIC_UNARY_MEM : InstrItinClass; +// add/sub/and/or/xor/sbc/cmp/test +def IIC_BIN_MEM : InstrItinClass; +def IIC_BIN_NONMEM : InstrItinClass; +// adc/sbc +def IIC_BIN_CARRY_MEM : InstrItinClass; +def IIC_BIN_CARRY_NONMEM : InstrItinClass; +// shift/rotate +def IIC_SR : InstrItinClass; +// shift double +def IIC_SHD16_REG_IM : InstrItinClass; +def IIC_SHD16_REG_CL : InstrItinClass; +def IIC_SHD16_MEM_IM : InstrItinClass; +def IIC_SHD16_MEM_CL : InstrItinClass; +def IIC_SHD32_REG_IM : InstrItinClass; +def IIC_SHD32_REG_CL : InstrItinClass; +def IIC_SHD32_MEM_IM : InstrItinClass; +def IIC_SHD32_MEM_CL : InstrItinClass; +def IIC_SHD64_REG_IM : InstrItinClass; +def IIC_SHD64_REG_CL : InstrItinClass; +def IIC_SHD64_MEM_IM : InstrItinClass; +def IIC_SHD64_MEM_CL : InstrItinClass; +// cmov +def IIC_CMOV16_RM : InstrItinClass; +def IIC_CMOV16_RR : InstrItinClass; +def IIC_CMOV32_RM : InstrItinClass; +def IIC_CMOV32_RR : InstrItinClass; +def IIC_CMOV64_RM : InstrItinClass; +def IIC_CMOV64_RR : InstrItinClass; +// set +def IIC_SET_R : InstrItinClass; +def IIC_SET_M : InstrItinClass; +// jmp/jcc/jcxz +def IIC_Jcc : InstrItinClass; +def IIC_JCXZ : InstrItinClass; +def IIC_JMP_REL : InstrItinClass; +def IIC_JMP_REG : InstrItinClass; +def IIC_JMP_MEM : InstrItinClass; +def IIC_JMP_FAR_MEM : InstrItinClass; +def IIC_JMP_FAR_PTR : InstrItinClass; +// loop +def IIC_LOOP : InstrItinClass; +def IIC_LOOPE : InstrItinClass; +def IIC_LOOPNE : InstrItinClass; +// call +def IIC_CALL_RI : InstrItinClass; +def IIC_CALL_MEM : InstrItinClass; +def IIC_CALL_FAR_MEM : InstrItinClass; +def IIC_CALL_FAR_PTR : InstrItinClass; +// ret +def IIC_RET : InstrItinClass; +def IIC_RET_IMM : InstrItinClass; +//sign extension movs +def IIC_MOVSX : InstrItinClass; +def IIC_MOVSX_R16_R8 : InstrItinClass; +def IIC_MOVSX_R16_M8 : InstrItinClass; +def IIC_MOVSX_R16_R16 : InstrItinClass; +def IIC_MOVSX_R32_R32 : InstrItinClass; +//zero extension movs +def IIC_MOVZX : InstrItinClass; +def IIC_MOVZX_R16_R8 : InstrItinClass; +def IIC_MOVZX_R16_M8 : InstrItinClass; + +def IIC_REP_MOVS : InstrItinClass; +def IIC_REP_STOS : InstrItinClass; + +// SSE scalar/parallel binary operations +def IIC_SSE_ALU_F32S_RR : InstrItinClass; +def IIC_SSE_ALU_F32S_RM : InstrItinClass; +def IIC_SSE_ALU_F64S_RR : InstrItinClass; +def IIC_SSE_ALU_F64S_RM : InstrItinClass; +def IIC_SSE_MUL_F32S_RR : InstrItinClass; +def IIC_SSE_MUL_F32S_RM : InstrItinClass; +def IIC_SSE_MUL_F64S_RR : InstrItinClass; +def IIC_SSE_MUL_F64S_RM : InstrItinClass; +def IIC_SSE_DIV_F32S_RR : InstrItinClass; +def IIC_SSE_DIV_F32S_RM : InstrItinClass; +def IIC_SSE_DIV_F64S_RR : InstrItinClass; +def IIC_SSE_DIV_F64S_RM : InstrItinClass; +def IIC_SSE_ALU_F32P_RR : InstrItinClass; +def IIC_SSE_ALU_F32P_RM : InstrItinClass; +def IIC_SSE_ALU_F64P_RR : InstrItinClass; +def IIC_SSE_ALU_F64P_RM : InstrItinClass; +def IIC_SSE_MUL_F32P_RR : InstrItinClass; +def IIC_SSE_MUL_F32P_RM : InstrItinClass; +def IIC_SSE_MUL_F64P_RR : InstrItinClass; +def IIC_SSE_MUL_F64P_RM : InstrItinClass; +def IIC_SSE_DIV_F32P_RR : InstrItinClass; +def IIC_SSE_DIV_F32P_RM : InstrItinClass; +def IIC_SSE_DIV_F64P_RR : InstrItinClass; +def IIC_SSE_DIV_F64P_RM : InstrItinClass; + +def IIC_SSE_COMIS_RR : InstrItinClass; +def IIC_SSE_COMIS_RM : InstrItinClass; + +def IIC_SSE_HADDSUB_RR : InstrItinClass; +def IIC_SSE_HADDSUB_RM : InstrItinClass; + +def IIC_SSE_BIT_P_RR : InstrItinClass; +def IIC_SSE_BIT_P_RM : InstrItinClass; + +def IIC_SSE_INTALU_P_RR : InstrItinClass; +def IIC_SSE_INTALU_P_RM : InstrItinClass; +def IIC_SSE_INTALUQ_P_RR : InstrItinClass; +def IIC_SSE_INTALUQ_P_RM : InstrItinClass; + +def IIC_SSE_INTMUL_P_RR : InstrItinClass; +def IIC_SSE_INTMUL_P_RM : InstrItinClass; + +def IIC_SSE_INTSH_P_RR : InstrItinClass; +def IIC_SSE_INTSH_P_RM : InstrItinClass; +def IIC_SSE_INTSH_P_RI : InstrItinClass; + +def IIC_SSE_INTSHDQ_P_RI : InstrItinClass; + +def IIC_SSE_SHUFP : InstrItinClass; +def IIC_SSE_PSHUF_RI : InstrItinClass; +def IIC_SSE_PSHUF_MI : InstrItinClass; + +def IIC_SSE_UNPCK : InstrItinClass; + +def IIC_SSE_MOVMSK : InstrItinClass; +def IIC_SSE_MASKMOV : InstrItinClass; + +def IIC_SSE_PEXTRW : InstrItinClass; +def IIC_SSE_PINSRW : InstrItinClass; + +def IIC_SSE_PABS_RR : InstrItinClass; +def IIC_SSE_PABS_RM : InstrItinClass; + +def IIC_SSE_SQRTPS_RR : InstrItinClass; +def IIC_SSE_SQRTPS_RM : InstrItinClass; +def IIC_SSE_SQRTSS_RR : InstrItinClass; +def IIC_SSE_SQRTSS_RM : InstrItinClass; +def IIC_SSE_SQRTPD_RR : InstrItinClass; +def IIC_SSE_SQRTPD_RM : InstrItinClass; +def IIC_SSE_SQRTSD_RR : InstrItinClass; +def IIC_SSE_SQRTSD_RM : InstrItinClass; + +def IIC_SSE_RSQRTPS_RR : InstrItinClass; +def IIC_SSE_RSQRTPS_RM : InstrItinClass; +def IIC_SSE_RSQRTSS_RR : InstrItinClass; +def IIC_SSE_RSQRTSS_RM : InstrItinClass; + +def IIC_SSE_RCPP_RR : InstrItinClass; +def IIC_SSE_RCPP_RM : InstrItinClass; +def IIC_SSE_RCPS_RR : InstrItinClass; +def IIC_SSE_RCPS_RM : InstrItinClass; + +def IIC_SSE_MOV_S_RR : InstrItinClass; +def IIC_SSE_MOV_S_RM : InstrItinClass; +def IIC_SSE_MOV_S_MR : InstrItinClass; + +def IIC_SSE_MOVA_P_RR : InstrItinClass; +def IIC_SSE_MOVA_P_RM : InstrItinClass; +def IIC_SSE_MOVA_P_MR : InstrItinClass; + +def IIC_SSE_MOVU_P_RR : InstrItinClass; +def IIC_SSE_MOVU_P_RM : InstrItinClass; +def IIC_SSE_MOVU_P_MR : InstrItinClass; + +def IIC_SSE_MOVDQ : InstrItinClass; +def IIC_SSE_MOVD_ToGP : InstrItinClass; +def IIC_SSE_MOVQ_RR : InstrItinClass; + +def IIC_SSE_MOV_LH : InstrItinClass; + +def IIC_SSE_LDDQU : InstrItinClass; + +def IIC_SSE_MOVNT : InstrItinClass; + +def IIC_SSE_PHADDSUBD_RR : InstrItinClass; +def IIC_SSE_PHADDSUBD_RM : InstrItinClass; +def IIC_SSE_PHADDSUBSW_RR : InstrItinClass; +def IIC_SSE_PHADDSUBSW_RM : InstrItinClass; +def IIC_SSE_PHADDSUBW_RR : InstrItinClass; +def IIC_SSE_PHADDSUBW_RM : InstrItinClass; +def IIC_SSE_PSHUFB_RR : InstrItinClass; +def IIC_SSE_PSHUFB_RM : InstrItinClass; +def IIC_SSE_PSIGN_RR : InstrItinClass; +def IIC_SSE_PSIGN_RM : InstrItinClass; + +def IIC_SSE_PMADD : InstrItinClass; +def IIC_SSE_PMULHRSW : InstrItinClass; +def IIC_SSE_PALIGNRR : InstrItinClass; +def IIC_SSE_PALIGNRM : InstrItinClass; +def IIC_SSE_MWAIT : InstrItinClass; +def IIC_SSE_MONITOR : InstrItinClass; +def IIC_SSE_MWAITX : InstrItinClass; +def IIC_SSE_MONITORX : InstrItinClass; +def IIC_SSE_CLZERO : InstrItinClass; + +def IIC_SSE_PREFETCH : InstrItinClass; +def IIC_SSE_PAUSE : InstrItinClass; +def IIC_SSE_LFENCE : InstrItinClass; +def IIC_SSE_MFENCE : InstrItinClass; +def IIC_SSE_SFENCE : InstrItinClass; +def IIC_SSE_LDMXCSR : InstrItinClass; +def IIC_SSE_STMXCSR : InstrItinClass; + +def IIC_SSE_CVT_PD_RR : InstrItinClass; +def IIC_SSE_CVT_PD_RM : InstrItinClass; +def IIC_SSE_CVT_PS_RR : InstrItinClass; +def IIC_SSE_CVT_PS_RM : InstrItinClass; +def IIC_SSE_CVT_PI2PS_RR : InstrItinClass; +def IIC_SSE_CVT_PI2PS_RM : InstrItinClass; +def IIC_SSE_CVT_Scalar_RR : InstrItinClass; +def IIC_SSE_CVT_Scalar_RM : InstrItinClass; +def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass; +def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass; +def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass; +def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass; +def IIC_SSE_CVT_SD2SI_RM : InstrItinClass; +def IIC_SSE_CVT_SD2SI_RR : InstrItinClass; + +// MMX +def IIC_MMX_MOV_MM_RM : InstrItinClass; +def IIC_MMX_MOV_REG_MM : InstrItinClass; +def IIC_MMX_MOVQ_RM : InstrItinClass; +def IIC_MMX_MOVQ_RR : InstrItinClass; + +def IIC_MMX_ALU_RM : InstrItinClass; +def IIC_MMX_ALU_RR : InstrItinClass; +def IIC_MMX_ALUQ_RM : InstrItinClass; +def IIC_MMX_ALUQ_RR : InstrItinClass; +def IIC_MMX_PHADDSUBW_RM : InstrItinClass; +def IIC_MMX_PHADDSUBW_RR : InstrItinClass; +def IIC_MMX_PHADDSUBD_RM : InstrItinClass; +def IIC_MMX_PHADDSUBD_RR : InstrItinClass; +def IIC_MMX_PMUL : InstrItinClass; +def IIC_MMX_MISC_FUNC_MEM : InstrItinClass; +def IIC_MMX_MISC_FUNC_REG : InstrItinClass; +def IIC_MMX_PSADBW : InstrItinClass; +def IIC_MMX_SHIFT_RI : InstrItinClass; +def IIC_MMX_SHIFT_RM : InstrItinClass; +def IIC_MMX_SHIFT_RR : InstrItinClass; +def IIC_MMX_UNPCK_H_RM : InstrItinClass; +def IIC_MMX_UNPCK_H_RR : InstrItinClass; +def IIC_MMX_UNPCK_L : InstrItinClass; +def IIC_MMX_PCK_RM : InstrItinClass; +def IIC_MMX_PCK_RR : InstrItinClass; +def IIC_MMX_PSHUF : InstrItinClass; +def IIC_MMX_PEXTR : InstrItinClass; +def IIC_MMX_PINSRW : InstrItinClass; +def IIC_MMX_MASKMOV : InstrItinClass; + +def IIC_MMX_CVT_PD_RR : InstrItinClass; +def IIC_MMX_CVT_PD_RM : InstrItinClass; +def IIC_MMX_CVT_PS_RR : InstrItinClass; +def IIC_MMX_CVT_PS_RM : InstrItinClass; + +def IIC_CMPX_LOCK : InstrItinClass; +def IIC_CMPX_LOCK_8 : InstrItinClass; +def IIC_CMPX_LOCK_8B : InstrItinClass; +def IIC_CMPX_LOCK_16B : InstrItinClass; + +def IIC_XADD_LOCK_MEM : InstrItinClass; +def IIC_XADD_LOCK_MEM8 : InstrItinClass; + +def IIC_FILD : InstrItinClass; +def IIC_FLD : InstrItinClass; +def IIC_FLD80 : InstrItinClass; +def IIC_FST : InstrItinClass; +def IIC_FST80 : InstrItinClass; +def IIC_FIST : InstrItinClass; +def IIC_FLDZ : InstrItinClass; +def IIC_FUCOM : InstrItinClass; +def IIC_FUCOMI : InstrItinClass; +def IIC_FCOMI : InstrItinClass; +def IIC_FNSTSW : InstrItinClass; +def IIC_FNSTCW : InstrItinClass; +def IIC_FLDCW : InstrItinClass; +def IIC_FNINIT : InstrItinClass; +def IIC_FFREE : InstrItinClass; +def IIC_FNCLEX : InstrItinClass; +def IIC_WAIT : InstrItinClass; +def IIC_FXAM : InstrItinClass; +def IIC_FNOP : InstrItinClass; +def IIC_FLDL : InstrItinClass; +def IIC_F2XM1 : InstrItinClass; +def IIC_FYL2X : InstrItinClass; +def IIC_FPTAN : InstrItinClass; +def IIC_FPATAN : InstrItinClass; +def IIC_FXTRACT : InstrItinClass; +def IIC_FPREM1 : InstrItinClass; +def IIC_FPSTP : InstrItinClass; +def IIC_FPREM : InstrItinClass; +def IIC_FYL2XP1 : InstrItinClass; +def IIC_FSINCOS : InstrItinClass; +def IIC_FRNDINT : InstrItinClass; +def IIC_FSCALE : InstrItinClass; +def IIC_FCOMPP : InstrItinClass; +def IIC_FXSAVE : InstrItinClass; +def IIC_FXRSTOR : InstrItinClass; + +def IIC_FXCH : InstrItinClass; + +// System instructions +def IIC_CPUID : InstrItinClass; +def IIC_INT : InstrItinClass; +def IIC_INT3 : InstrItinClass; +def IIC_INVD : InstrItinClass; +def IIC_INVLPG : InstrItinClass; +def IIC_IRET : InstrItinClass; +def IIC_HLT : InstrItinClass; +def IIC_LXS : InstrItinClass; +def IIC_LTR : InstrItinClass; +def IIC_RDTSC : InstrItinClass; +def IIC_RSM : InstrItinClass; +def IIC_SIDT : InstrItinClass; +def IIC_SGDT : InstrItinClass; +def IIC_SLDT : InstrItinClass; +def IIC_STR : InstrItinClass; +def IIC_SWAPGS : InstrItinClass; +def IIC_SYSCALL : InstrItinClass; +def IIC_SYS_ENTER_EXIT : InstrItinClass; +def IIC_IN_RR : InstrItinClass; +def IIC_IN_RI : InstrItinClass; +def IIC_OUT_RR : InstrItinClass; +def IIC_OUT_IR : InstrItinClass; +def IIC_INS : InstrItinClass; +def IIC_LWP : InstrItinClass; +def IIC_MOV_REG_DR : InstrItinClass; +def IIC_MOV_DR_REG : InstrItinClass; +def IIC_MOV_REG_CR : InstrItinClass; +def IIC_MOV_CR_REG : InstrItinClass; +def IIC_MOV_REG_SR : InstrItinClass; +def IIC_MOV_MEM_SR : InstrItinClass; +def IIC_MOV_SR_REG : InstrItinClass; +def IIC_MOV_SR_MEM : InstrItinClass; +def IIC_LAR_RM : InstrItinClass; +def IIC_LAR_RR : InstrItinClass; +def IIC_LSL_RM : InstrItinClass; +def IIC_LSL_RR : InstrItinClass; +def IIC_LGDT : InstrItinClass; +def IIC_LIDT : InstrItinClass; +def IIC_LLDT_REG : InstrItinClass; +def IIC_LLDT_MEM : InstrItinClass; +def IIC_PUSH_CS : InstrItinClass; +def IIC_PUSH_SR : InstrItinClass; +def IIC_POP_SR : InstrItinClass; +def IIC_POP_SR_SS : InstrItinClass; +def IIC_VERR : InstrItinClass; +def IIC_VERW_REG : InstrItinClass; +def IIC_VERW_MEM : InstrItinClass; +def IIC_WRMSR : InstrItinClass; +def IIC_RDMSR : InstrItinClass; +def IIC_RDPMC : InstrItinClass; +def IIC_SMSW : InstrItinClass; +def IIC_LMSW_REG : InstrItinClass; +def IIC_LMSW_MEM : InstrItinClass; +def IIC_ENTER : InstrItinClass; +def IIC_LEAVE : InstrItinClass; +def IIC_POP_MEM : InstrItinClass; +def IIC_POP_REG16 : InstrItinClass; +def IIC_POP_REG : InstrItinClass; +def IIC_POP_F : InstrItinClass; +def IIC_POP_FD : InstrItinClass; +def IIC_POP_A : InstrItinClass; +def IIC_PUSH_IMM : InstrItinClass; +def IIC_PUSH_MEM : InstrItinClass; +def IIC_PUSH_REG : InstrItinClass; +def IIC_PUSH_F : InstrItinClass; +def IIC_PUSH_A : InstrItinClass; +def IIC_BSWAP : InstrItinClass; +def IIC_BIT_SCAN_MEM : InstrItinClass; +def IIC_BIT_SCAN_REG : InstrItinClass; +def IIC_MOVS : InstrItinClass; +def IIC_STOS : InstrItinClass; +def IIC_SCAS : InstrItinClass; +def IIC_CMPS : InstrItinClass; +def IIC_MOV : InstrItinClass; +def IIC_MOV_MEM : InstrItinClass; +def IIC_AHF : InstrItinClass; +def IIC_BT_MI : InstrItinClass; +def IIC_BT_MR : InstrItinClass; +def IIC_BT_RI : InstrItinClass; +def IIC_BT_RR : InstrItinClass; +def IIC_BTX_MI : InstrItinClass; +def IIC_BTX_MR : InstrItinClass; +def IIC_BTX_RI : InstrItinClass; +def IIC_BTX_RR : InstrItinClass; +def IIC_XCHG_REG : InstrItinClass; +def IIC_XCHG_MEM : InstrItinClass; +def IIC_XADD_REG : InstrItinClass; +def IIC_XADD_MEM : InstrItinClass; +def IIC_CMPXCHG_MEM : InstrItinClass; +def IIC_CMPXCHG_REG : InstrItinClass; +def IIC_CMPXCHG_MEM8 : InstrItinClass; +def IIC_CMPXCHG_REG8 : InstrItinClass; +def IIC_CMPXCHG_8B : InstrItinClass; +def IIC_CMPXCHG_16B : InstrItinClass; +def IIC_LODS : InstrItinClass; +def IIC_OUTS : InstrItinClass; +def IIC_CLC : InstrItinClass; +def IIC_CLD : InstrItinClass; +def IIC_CLI : InstrItinClass; +def IIC_CMC : InstrItinClass; +def IIC_CLTS : InstrItinClass; +def IIC_STC : InstrItinClass; +def IIC_STI : InstrItinClass; +def IIC_STD : InstrItinClass; +def IIC_XLAT : InstrItinClass; +def IIC_AAA : InstrItinClass; +def IIC_AAD : InstrItinClass; +def IIC_AAM : InstrItinClass; +def IIC_AAS : InstrItinClass; +def IIC_DAA : InstrItinClass; +def IIC_DAS : InstrItinClass; +def IIC_BOUND : InstrItinClass; +def IIC_ARPL_REG : InstrItinClass; +def IIC_ARPL_MEM : InstrItinClass; +def IIC_MOVBE : InstrItinClass; +def IIC_AES : InstrItinClass; +def IIC_BLEND_MEM : InstrItinClass; +def IIC_BLEND_NOMEM : InstrItinClass; +def IIC_CBW : InstrItinClass; +def IIC_CRC32_REG : InstrItinClass; +def IIC_CRC32_MEM : InstrItinClass; +def IIC_SSE_DPPD_RR : InstrItinClass; +def IIC_SSE_DPPD_RM : InstrItinClass; +def IIC_SSE_DPPS_RR : InstrItinClass; +def IIC_SSE_DPPS_RM : InstrItinClass; +def IIC_MMX_EMMS : InstrItinClass; +def IIC_SSE_EXTRACTPS_RR : InstrItinClass; +def IIC_SSE_EXTRACTPS_RM : InstrItinClass; +def IIC_SSE_INSERTPS_RR : InstrItinClass; +def IIC_SSE_INSERTPS_RM : InstrItinClass; +def IIC_SSE_MPSADBW_RR : InstrItinClass; +def IIC_SSE_MPSADBW_RM : InstrItinClass; +def IIC_SSE_PMULLD_RR : InstrItinClass; +def IIC_SSE_PMULLD_RM : InstrItinClass; +def IIC_SSE_ROUNDPS_REG : InstrItinClass; +def IIC_SSE_ROUNDPS_MEM : InstrItinClass; +def IIC_SSE_ROUNDPD_REG : InstrItinClass; +def IIC_SSE_ROUNDPD_MEM : InstrItinClass; +def IIC_SSE_POPCNT_RR : InstrItinClass; +def IIC_SSE_POPCNT_RM : InstrItinClass; +def IIC_SSE_PCLMULQDQ_RR : InstrItinClass; +def IIC_SSE_PCLMULQDQ_RM : InstrItinClass; + +def IIC_NOP : InstrItinClass; + +//===----------------------------------------------------------------------===// +// Processor instruction itineraries. + +// IssueWidth is analogous to the number of decode units. Core and its +// descendents, including Nehalem and SandyBridge have 4 decoders. +// Resources beyond the decoder operate on micro-ops and are bufferred +// so adjacent micro-ops don't directly compete. +// +// MicroOpBufferSize > 1 indicates that RAW dependencies can be +// decoded in the same cycle. The value 32 is a reasonably arbitrary +// number of in-flight instructions. +// +// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef +// indicates high latency opcodes. Alternatively, InstrItinData +// entries may be included here to define specific operand +// latencies. Since these latencies are not used for pipeline hazards, +// they do not need to be exact. +// +// The GenericX86Model contains no instruction itineraries +// and disables PostRAScheduler. +class GenericX86Model : SchedMachineModel { + let IssueWidth = 4; + let MicroOpBufferSize = 32; + let LoadLatency = 4; + let HighLatency = 10; + let PostRAScheduler = 0; + let CompleteModel = 0; +} + +def GenericModel : GenericX86Model; + +// Define a model with the PostRAScheduler enabled. +def GenericPostRAModel : GenericX86Model { + let PostRAScheduler = 1; +} + +include "X86ScheduleAtom.td" +include "X86SchedSandyBridge.td" +include "X86SchedHaswell.td" +include "X86ScheduleSLM.td" +include "X86ScheduleBtVer2.td" + Index: llvm/trunk/lib/Target/X86/X86Subtarget.h =================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h +++ llvm/trunk/lib/Target/X86/X86Subtarget.h @@ -124,6 +124,9 @@ /// Target has TBM instructions. bool HasTBM; + /// Target has LWP instructions + bool HasLWP; + /// True if the processor has the MOVBE instruction. bool HasMOVBE; @@ -447,6 +450,7 @@ bool hasAnyFMA() const { return hasFMA() || hasFMA4(); } bool hasXOP() const { return HasXOP; } bool hasTBM() const { return HasTBM; } + bool hasLWP() const { return HasLWP; } bool hasMOVBE() const { return HasMOVBE; } bool hasRDRAND() const { return HasRDRAND; } bool hasF16C() const { return HasF16C; } Index: llvm/trunk/lib/Target/X86/X86Subtarget.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp @@ -265,6 +265,7 @@ HasFMA4 = false; HasXOP = false; HasTBM = false; + HasLWP = false; HasMOVBE = false; HasRDRAND = false; HasF16C = false; Index: llvm/trunk/test/CodeGen/X86/lwp-intrinsics-x86_64.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/lwp-intrinsics-x86_64.ll +++ llvm/trunk/test/CodeGen/X86/lwp-intrinsics-x86_64.ll @@ -0,0 +1,49 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X64 + +define i8 @test_lwpins64_rri(i64 %a0, i32 %a1) nounwind { +; X64-LABEL: test_lwpins64_rri: +; X64: # BB#0: +; X64-NEXT: lwpins $-1985229329, %esi, %rdi # imm = 0x89ABCDEF +; X64-NEXT: setb %al +; X64-NEXT: retq + %1 = tail call i8 @llvm.x86.lwpins64(i64 %a0, i32 %a1, i32 2309737967) + ret i8 %1 +} + +define i8 @test_lwpins64_rmi(i64 %a0, i32 *%p1) nounwind { +; X64-LABEL: test_lwpins64_rmi: +; X64: # BB#0: +; X64-NEXT: lwpins $1985229328, (%rsi), %rdi # imm = 0x76543210 +; X64-NEXT: setb %al +; X64-NEXT: retq + %a1 = load i32, i32 *%p1 + %1 = tail call i8 @llvm.x86.lwpins64(i64 %a0, i32 %a1, i32 1985229328) + ret i8 %1 +} + +define void @test_lwpval64_rri(i64 %a0, i32 %a1) nounwind { +; X64-LABEL: test_lwpval64_rri: +; X64: # BB#0: +; X64-NEXT: lwpval $-19088744, %esi, %rdi # imm = 0xFEDCBA98 +; X64-NEXT: retq + tail call void @llvm.x86.lwpval64(i64 %a0, i32 %a1, i32 4275878552) + ret void +} + +define void @test_lwpval64_rmi(i64 %a0, i32 *%p1) nounwind { +; X64-LABEL: test_lwpval64_rmi: +; X64: # BB#0: +; X64-NEXT: lwpval $305419896, (%rsi), %rdi # imm = 0x12345678 +; X64-NEXT: retq + %a1 = load i32, i32 *%p1 + tail call void @llvm.x86.lwpval64(i64 %a0, i32 %a1, i32 305419896) + ret void +} + +declare i8 @llvm.x86.lwpins64(i64, i32, i32) nounwind +declare void @llvm.x86.lwpval64(i64, i32, i32) nounwind Index: llvm/trunk/test/CodeGen/X86/lwp-intrinsics.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/lwp-intrinsics.ll +++ llvm/trunk/test/CodeGen/X86/lwp-intrinsics.ll @@ -0,0 +1,121 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown -mattr=+lwp | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X64 + +define void @test_llwpcb(i8 *%a0) nounwind { +; X86-LABEL: test_llwpcb: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: llwpcb %eax +; X86-NEXT: retl +; +; X64-LABEL: test_llwpcb: +; X64: # BB#0: +; X64-NEXT: llwpcb %rdi +; X64-NEXT: retq + tail call void @llvm.x86.llwpcb(i8 *%a0) + ret void +} + +define i8* @test_slwpcb(i8 *%a0) nounwind { +; X86-LABEL: test_slwpcb: +; X86: # BB#0: +; X86-NEXT: slwpcb %eax +; X86-NEXT: retl +; +; X64-LABEL: test_slwpcb: +; X64: # BB#0: +; X64-NEXT: slwpcb %rax +; X64-NEXT: retq + %1 = tail call i8* @llvm.x86.slwpcb() + ret i8 *%1 +} + +define i8 @test_lwpins32_rri(i32 %a0, i32 %a1) nounwind { +; X86-LABEL: test_lwpins32_rri: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: addl %ecx, %ecx +; X86-NEXT: lwpins $-1985229329, %ecx, %eax # imm = 0x89ABCDEF +; X86-NEXT: setb %al +; X86-NEXT: retl +; +; X64-LABEL: test_lwpins32_rri: +; X64: # BB#0: +; X64-NEXT: addl %esi, %esi +; X64-NEXT: lwpins $-1985229329, %esi, %edi # imm = 0x89ABCDEF +; X64-NEXT: setb %al +; X64-NEXT: retq + %1 = add i32 %a1, %a1 + %2 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %1, i32 2309737967) + ret i8 %2 +} + +define i8 @test_lwpins32_rmi(i32 %a0, i32 *%p1) nounwind { +; X86-LABEL: test_lwpins32_rmi: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: lwpins $1985229328, (%eax), %ecx # imm = 0x76543210 +; X86-NEXT: setb %al +; X86-NEXT: retl +; +; X64-LABEL: test_lwpins32_rmi: +; X64: # BB#0: +; X64-NEXT: lwpins $1985229328, (%rsi), %edi # imm = 0x76543210 +; X64-NEXT: setb %al +; X64-NEXT: retq + %a1 = load i32, i32 *%p1 + %1 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %a1, i32 1985229328) + ret i8 %1 +} + +define void @test_lwpval32_rri(i32 %a0, i32 %a1) nounwind { +; X86-LABEL: test_lwpval32_rri: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: addl %ecx, %ecx +; X86-NEXT: lwpval $-19088744, %ecx, %eax # imm = 0xFEDCBA98 +; X86-NEXT: retl +; +; X64-LABEL: test_lwpval32_rri: +; X64: # BB#0: +; X64-NEXT: addl %esi, %esi +; X64-NEXT: lwpval $-19088744, %esi, %edi # imm = 0xFEDCBA98 +; X64-NEXT: retq + %1 = add i32 %a1, %a1 + tail call void @llvm.x86.lwpval32(i32 %a0, i32 %1, i32 4275878552) + ret void +} + +define void @test_lwpval32_rmi(i32 %a0, i32 *%p1) nounwind { +; X86-LABEL: test_lwpval32_rmi: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: lwpval $305419896, (%eax), %ecx # imm = 0x12345678 +; X86-NEXT: retl +; +; X64-LABEL: test_lwpval32_rmi: +; X64: # BB#0: +; X64-NEXT: lwpval $305419896, (%rsi), %edi # imm = 0x12345678 +; X64-NEXT: retq + %a1 = load i32, i32 *%p1 + tail call void @llvm.x86.lwpval32(i32 %a0, i32 %a1, i32 305419896) + ret void +} + +declare void @llvm.x86.llwpcb(i8*) nounwind +declare i8* @llvm.x86.slwpcb() nounwind +declare i8 @llvm.x86.lwpins32(i32, i32, i32) nounwind +declare void @llvm.x86.lwpval32(i32, i32, i32) nounwind Index: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt +++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt @@ -773,3 +773,21 @@ #CHECK: getsec 0x0f 0x37 + +#CHECK: llwpcb %ecx +0x8f 0xe9 0x78 0x12 0xc1 + +#CHECK: slwpcb %ecx +0x8f 0xe9 0x78 0x12 0xc9 + +# CHECK: lwpins $305419896, %ebx, %eax +0x8f 0xea 0x78 0x12 0xc3 0x78 0x56 0x34 0x12 + +# CHECK: lwpins $591751049, (%esp), %edx +0x8f 0xea 0x68 0x12 0x04 0x24 0x89 0x67 0x45 0x23 + +# CHECK: lwpval $1737075661, %ebx, %eax +0x8f 0xea 0x78 0x12 0xcb 0xcd 0xab 0x89 0x67 + +# CHECK: lwpval $2309737967, (%esp), %edx +0x8f 0xea 0x68 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89 Index: llvm/trunk/test/MC/Disassembler/X86/x86-64.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/X86/x86-64.txt +++ llvm/trunk/test/MC/Disassembler/X86/x86-64.txt @@ -456,3 +456,27 @@ # CHECK: callq -32769 0xe8 0xff 0x7f 0xff 0xff + +# CHECK: llwpcb %rax +0x8f 0xe9 0xf8 0x12 0xc0 + +# CHECK: slwpcb %rax +0x8f 0xe9 0xf8 0x12 0xc8 + +# CHECK: lwpins $305419896, %ebx, %rax +0x8f 0xea 0xf8 0x12 0xc3 0x78 0x56 0x34 0x12 + +# CHECK: lwpins $591751049, (%rsp), %rdx +0x8f 0xea 0xe8 0x12 0x04 0x24 0x89 0x67 0x45 0x23 + +# CHECK: lwpins $591751049, (%esp), %edx +0x67 0x8f 0xea 0x68 0x12 0x04 0x24 0x89 0x67 0x45 0x23 + +# CHECK: lwpval $1737075661, %ebx, %rax +0x8f 0xea 0xf8 0x12 0xcb 0xcd 0xab 0x89 0x67 + +# CHECK: lwpval $2309737967, (%rsp), %rdx +0x8f 0xea 0xe8 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89 + +# CHECK: lwpval $2309737967, (%esp), %edx +0x67 0x8f 0xea 0x68 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89 Index: llvm/trunk/test/MC/X86/lwp-x86_64.s =================================================================== --- llvm/trunk/test/MC/X86/lwp-x86_64.s +++ llvm/trunk/test/MC/X86/lwp-x86_64.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s --check-prefix=CHECK + +llwpcb %rcx +# CHECK: llwpcb %rcx +# CHECK: encoding: [0x8f,0xe9,0xf8,0x12,0xc1] + +slwpcb %rax +# CHECK: slwpcb %rax +# CHECK: encoding: [0x8f,0xe9,0xf8,0x12,0xc8] + +lwpins $305419896, %ebx, %rax +# CHECK: lwpins $305419896, %ebx, %rax +# CHECK: encoding: [0x8f,0xea,0xf8,0x12,0xc3,0x78,0x56,0x34,0x12] + +lwpins $591751049, (%rsp), %rdx +# CHECK: lwpins $591751049, (%rsp), %rdx +# CHECK: encoding: [0x8f,0xea,0xe8,0x12,0x04,0x24,0x89,0x67,0x45,0x23] + +lwpval $1737075661, %ebx, %rax +# CHECK: lwpval $1737075661, %ebx, %rax +# CHECK: encoding: [0x8f,0xea,0xf8,0x12,0xcb,0xcd,0xab,0x89,0x67] + +lwpval $2309737967, (%rsp), %rdx +# CHECK: lwpval $2309737967, (%rsp), %rdx +# CHECK: encoding: [0x8f,0xea,0xe8,0x12,0x0c,0x24,0xef,0xcd,0xab,0x89] Index: llvm/trunk/test/MC/X86/lwp.s =================================================================== --- llvm/trunk/test/MC/X86/lwp.s +++ llvm/trunk/test/MC/X86/lwp.s @@ -0,0 +1,32 @@ +# RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-X86 +# RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-X64 + +llwpcb %ecx +# CHECK: llwpcb %ecx +# CHECK-X86: encoding: [0x8f,0xe9,0x78,0x12,0xc1] +# CHECK-X64: encoding: [0x8f,0xe9,0x78,0x12,0xc1] + +slwpcb %eax +# CHECK: slwpcb %eax +# CHECK-X86: encoding: [0x8f,0xe9,0x78,0x12,0xc8] +# CHECK-X64: encoding: [0x8f,0xe9,0x78,0x12,0xc8] + +lwpins $305419896, %ebx, %eax +# CHECK: lwpins $305419896, %ebx, %eax +# CHECK-X86: encoding: [0x8f,0xea,0x78,0x12,0xc3,0x78,0x56,0x34,0x12] +# CHECK-X64: encoding: [0x8f,0xea,0x78,0x12,0xc3,0x78,0x56,0x34,0x12] + +lwpins $591751049, (%esp), %edx +# CHECK: lwpins $591751049, (%esp), %edx +# CHECK-X86: encoding: [0x8f,0xea,0x68,0x12,0x04,0x24,0x89,0x67,0x45,0x23] +# CHECK-X64: encoding: [0x67,0x8f,0xea,0x68,0x12,0x04,0x24,0x89,0x67,0x45,0x23] + +lwpval $1737075661, %ebx, %eax +# CHECK: lwpval $1737075661, %ebx, %eax +# CHECK-X86: encoding: [0x8f,0xea,0x78,0x12,0xcb,0xcd,0xab,0x89,0x67] +# CHECK-X64: encoding: [0x8f,0xea,0x78,0x12,0xcb,0xcd,0xab,0x89,0x67] + +lwpval $2309737967, (%esp), %edx +# CHECK: lwpval $2309737967, (%esp), %edx +# CHECK-X86: encoding: [0x8f,0xea,0x68,0x12,0x0c,0x24,0xef,0xcd,0xab,0x89] +# CHECK-X64: encoding: [0x67,0x8f,0xea,0x68,0x12,0x0c,0x24,0xef,0xcd,0xab,0x89]