Index: include/llvm/IR/IntrinsicsX86.td =================================================================== --- include/llvm/IR/IntrinsicsX86.td +++ include/llvm/IR/IntrinsicsX86.td @@ -3221,6 +3221,29 @@ } //===----------------------------------------------------------------------===// +// LWP +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_llwpcb : + GCCBuiltin<"__builtin_ia32_llwpcb">, + Intrinsic<[], [llvm_ptr_ty], []>; + def int_x86_slwpcb : + GCCBuiltin<"__builtin_ia32_slwpcb">, + Intrinsic<[llvm_ptr_ty], [], []>; + def int_x86_lwpins32 : + GCCBuiltin<"__builtin_ia32_lwpins32">, + Intrinsic<[llvm_i8_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_x86_lwpins64 : + GCCBuiltin<"__builtin_ia32_lwpins64">, + Intrinsic<[llvm_i8_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_x86_lwpval32 : + GCCBuiltin<"__builtin_ia32_lwpval32">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_x86_lwpval64 : + GCCBuiltin<"__builtin_ia32_lwpval64">, + Intrinsic<[], [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty], []>; +} + +//===----------------------------------------------------------------------===// // MMX // Empty MMX state op. Index: lib/Support/Host.cpp =================================================================== --- lib/Support/Host.cpp +++ lib/Support/Host.cpp @@ -1363,6 +1363,7 @@ Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; + Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); Index: lib/Target/X86/X86.td =================================================================== --- lib/Target/X86/X86.td +++ lib/Target/X86/X86.td @@ -170,6 +170,8 @@ [FeatureSSE2]>; def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", "Enable TBM instructions">; +def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", + "Enable LWP instructions">; def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", "Support MOVBE instruction">; def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", @@ -691,6 +693,7 @@ FeatureLZCNT, FeaturePOPCNT, FeatureXSAVE, + FeatureLWP, FeatureSlowSHLD, FeatureLAHFSAHF ]>; @@ -713,6 +716,7 @@ FeatureXSAVE, FeatureBMI, FeatureTBM, + FeatureLWP, FeatureFMA, FeatureSlowSHLD, FeatureLAHFSAHF @@ -737,6 +741,7 @@ FeatureXSAVE, FeatureBMI, FeatureTBM, + FeatureLWP, FeatureFMA, FeatureXSAVEOPT, FeatureSlowSHLD, @@ -763,6 +768,7 @@ FeatureBMI, FeatureBMI2, FeatureTBM, + FeatureLWP, FeatureFMA, FeatureXSAVEOPT, FeatureSlowSHLD, Index: lib/Target/X86/X86ISelLowering.h =================================================================== --- lib/Target/X86/X86ISelLowering.h +++ lib/Target/X86/X86ISelLowering.h @@ -559,6 +559,9 @@ // Conversions between float and half-float. CVTPS2PH, CVTPH2PS, + // LWP insert record. + LWPINS, + // Compare and swap. LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, LCMPXCHG8_DAG, Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp +++ lib/Target/X86/X86ISelLowering.cpp @@ -20319,6 +20319,19 @@ // during ExpandISelPseudos in EmitInstrWithCustomInserter. return SDValue(); } + case Intrinsic::x86_lwpins32: + case Intrinsic::x86_lwpins64: { + SDLoc dl(Op); + SDValue Chain = Op->getOperand(0); + SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); + SDValue LwpIns = + DAG.getNode(X86ISD::LWPINS, dl, VTs, Chain, Op->getOperand(2), + Op->getOperand(3), Op->getOperand(4)); + SDValue SetCC = getSETCC(X86::COND_B, LwpIns.getValue(0), dl, DAG); + SDValue Result = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, SetCC); + return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, + LwpIns.getValue(1)); + } } return SDValue(); } @@ -24495,6 +24508,7 @@ case X86ISD::CVTP2UI_RND: return "X86ISD::CVTP2UI_RND"; case X86ISD::CVTS2SI_RND: return "X86ISD::CVTS2SI_RND"; case X86ISD::CVTS2UI_RND: return "X86ISD::CVTS2UI_RND"; + case X86ISD::LWPINS: return "X86ISD::LWPINS"; } return nullptr; } Index: lib/Target/X86/X86InstrInfo.td =================================================================== --- lib/Target/X86/X86InstrInfo.td +++ lib/Target/X86/X86InstrInfo.td @@ -283,6 +283,11 @@ def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; +def X86lwpins : SDNode<"X86ISD::LWPINS", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + //===----------------------------------------------------------------------===// // X86 Operand Definitions. // @@ -836,6 +841,7 @@ def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; def HasXOP : Predicate<"Subtarget->hasXOP()">; def HasTBM : Predicate<"Subtarget->hasTBM()">; +def HasLWP : Predicate<"Subtarget->hasLWP()">; def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; def HasF16C : Predicate<"Subtarget->hasF16C()">; @@ -2444,6 +2450,59 @@ } // HasTBM, EFLAGS //===----------------------------------------------------------------------===// +// Lightweight Profiling Instructions + +let Predicates = [HasLWP] in { + +def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR32:$src)], IIC_LWP>, + XOP, XOP9, Requires<[Not64BitMode]>; +def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", + [(set GR32:$dst, (int_x86_slwpcb))], IIC_LWP>, + XOP, XOP9, Requires<[Not64BitMode]>; + +def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", + [(int_x86_llwpcb GR64:$src)], IIC_LWP>, + XOP, XOP9, VEX_W, Requires<[In64BitMode]>; +def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", + [(set GR64:$dst, (int_x86_slwpcb))], IIC_LWP>, + XOP, XOP9, VEX_W, Requires<[In64BitMode]>; + +multiclass lwpins_intr { + def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))]>, + XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), imm:$cntl))]>, + XOP_4V, XOPA; +} + +let Defs = [EFLAGS] in { + defm LWPINS32 : lwpins_intr; + defm LWPINS64 : lwpins_intr, VEX_W; +} // EFLAGS + +multiclass lwpval_intr { + def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, GR32:$src1, imm:$cntl)], IIC_LWP>, + XOP_4V, XOPA; + let mayLoad = 1 in + def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), + "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", + [(Int RC:$src0, (loadi32 addr:$src1), imm:$cntl)], IIC_LWP>, + XOP_4V, XOPA; +} + +defm LWPVAL32 : lwpval_intr; +defm LWPVAL64 : lwpval_intr, VEX_W; + +} // HasLWP + +//===----------------------------------------------------------------------===// // MONITORX/MWAITX Instructions // let SchedRW = [ WriteSystem ] in { Index: lib/Target/X86/X86Schedule.td =================================================================== --- lib/Target/X86/X86Schedule.td +++ lib/Target/X86/X86Schedule.td @@ -497,6 +497,7 @@ def IIC_OUT_RR : InstrItinClass; def IIC_OUT_IR : InstrItinClass; def IIC_INS : InstrItinClass; +def IIC_LWP : InstrItinClass; def IIC_MOV_REG_DR : InstrItinClass; def IIC_MOV_DR_REG : InstrItinClass; def IIC_MOV_REG_CR : InstrItinClass; Index: lib/Target/X86/X86Subtarget.h =================================================================== --- lib/Target/X86/X86Subtarget.h +++ lib/Target/X86/X86Subtarget.h @@ -124,6 +124,9 @@ /// Target has TBM instructions. bool HasTBM; + /// Target has LWP instructions + bool HasLWP; + /// True if the processor has the MOVBE instruction. bool HasMOVBE; @@ -447,6 +450,7 @@ bool hasAnyFMA() const { return hasFMA() || hasFMA4(); } bool hasXOP() const { return HasXOP; } bool hasTBM() const { return HasTBM; } + bool hasLWP() const { return HasLWP; } bool hasMOVBE() const { return HasMOVBE; } bool hasRDRAND() const { return HasRDRAND; } bool hasF16C() const { return HasF16C; } Index: lib/Target/X86/X86Subtarget.cpp =================================================================== --- lib/Target/X86/X86Subtarget.cpp +++ lib/Target/X86/X86Subtarget.cpp @@ -265,6 +265,7 @@ HasFMA4 = false; HasXOP = false; HasTBM = false; + HasLWP = false; HasMOVBE = false; HasRDRAND = false; HasF16C = false; Index: test/CodeGen/X86/lwp-intrinsics-x86_64.ll =================================================================== --- test/CodeGen/X86/lwp-intrinsics-x86_64.ll +++ test/CodeGen/X86/lwp-intrinsics-x86_64.ll @@ -0,0 +1,49 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X64 + +define i8 @test_lwpins64_rri(i64 %a0, i32 %a1) nounwind { +; X64-LABEL: test_lwpins64_rri: +; X64: # BB#0: +; X64-NEXT: lwpins $-1985229329, %esi, %rdi # imm = 0x89ABCDEF +; X64-NEXT: setb %al +; X64-NEXT: retq + %1 = tail call i8 @llvm.x86.lwpins64(i64 %a0, i32 %a1, i32 2309737967) + ret i8 %1 +} + +define i8 @test_lwpins64_rmi(i64 %a0, i32 *%p1) nounwind { +; X64-LABEL: test_lwpins64_rmi: +; X64: # BB#0: +; X64-NEXT: lwpins $1985229328, (%rsi), %rdi # imm = 0x76543210 +; X64-NEXT: setb %al +; X64-NEXT: retq + %a1 = load i32, i32 *%p1 + %1 = tail call i8 @llvm.x86.lwpins64(i64 %a0, i32 %a1, i32 1985229328) + ret i8 %1 +} + +define void @test_lwpval64_rri(i64 %a0, i32 %a1) nounwind { +; X64-LABEL: test_lwpval64_rri: +; X64: # BB#0: +; X64-NEXT: lwpval $-19088744, %esi, %rdi # imm = 0xFEDCBA98 +; X64-NEXT: retq + tail call void @llvm.x86.lwpval64(i64 %a0, i32 %a1, i32 4275878552) + ret void +} + +define void @test_lwpval64_rmi(i64 %a0, i32 *%p1) nounwind { +; X64-LABEL: test_lwpval64_rmi: +; X64: # BB#0: +; X64-NEXT: lwpval $305419896, (%rsi), %rdi # imm = 0x12345678 +; X64-NEXT: retq + %a1 = load i32, i32 *%p1 + tail call void @llvm.x86.lwpval64(i64 %a0, i32 %a1, i32 305419896) + ret void +} + +declare i8 @llvm.x86.lwpins64(i64, i32, i32) nounwind +declare void @llvm.x86.lwpval64(i64, i32, i32) nounwind Index: test/CodeGen/X86/lwp-intrinsics.ll =================================================================== --- test/CodeGen/X86/lwp-intrinsics.ll +++ test/CodeGen/X86/lwp-intrinsics.ll @@ -0,0 +1,121 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown -mattr=+lwp | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X64 + +define void @test_llwpcb(i8 *%a0) nounwind { +; X86-LABEL: test_llwpcb: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: llwpcb %eax +; X86-NEXT: retl +; +; X64-LABEL: test_llwpcb: +; X64: # BB#0: +; X64-NEXT: llwpcb %rdi +; X64-NEXT: retq + tail call void @llvm.x86.llwpcb(i8 *%a0) + ret void +} + +define i8* @test_slwpcb(i8 *%a0) nounwind { +; X86-LABEL: test_slwpcb: +; X86: # BB#0: +; X86-NEXT: slwpcb %eax +; X86-NEXT: retl +; +; X64-LABEL: test_slwpcb: +; X64: # BB#0: +; X64-NEXT: slwpcb %rax +; X64-NEXT: retq + %1 = tail call i8* @llvm.x86.slwpcb() + ret i8 *%1 +} + +define i8 @test_lwpins32_rri(i32 %a0, i32 %a1) nounwind { +; X86-LABEL: test_lwpins32_rri: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: addl %ecx, %ecx +; X86-NEXT: lwpins $-1985229329, %ecx, %eax # imm = 0x89ABCDEF +; X86-NEXT: setb %al +; X86-NEXT: retl +; +; X64-LABEL: test_lwpins32_rri: +; X64: # BB#0: +; X64-NEXT: addl %esi, %esi +; X64-NEXT: lwpins $-1985229329, %esi, %edi # imm = 0x89ABCDEF +; X64-NEXT: setb %al +; X64-NEXT: retq + %1 = add i32 %a1, %a1 + %2 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %1, i32 2309737967) + ret i8 %2 +} + +define i8 @test_lwpins32_rmi(i32 %a0, i32 *%p1) nounwind { +; X86-LABEL: test_lwpins32_rmi: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: lwpins $1985229328, (%eax), %ecx # imm = 0x76543210 +; X86-NEXT: setb %al +; X86-NEXT: retl +; +; X64-LABEL: test_lwpins32_rmi: +; X64: # BB#0: +; X64-NEXT: lwpins $1985229328, (%rsi), %edi # imm = 0x76543210 +; X64-NEXT: setb %al +; X64-NEXT: retq + %a1 = load i32, i32 *%p1 + %1 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %a1, i32 1985229328) + ret i8 %1 +} + +define void @test_lwpval32_rri(i32 %a0, i32 %a1) nounwind { +; X86-LABEL: test_lwpval32_rri: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: addl %ecx, %ecx +; X86-NEXT: lwpval $-19088744, %ecx, %eax # imm = 0xFEDCBA98 +; X86-NEXT: retl +; +; X64-LABEL: test_lwpval32_rri: +; X64: # BB#0: +; X64-NEXT: addl %esi, %esi +; X64-NEXT: lwpval $-19088744, %esi, %edi # imm = 0xFEDCBA98 +; X64-NEXT: retq + %1 = add i32 %a1, %a1 + tail call void @llvm.x86.lwpval32(i32 %a0, i32 %1, i32 4275878552) + ret void +} + +define void @test_lwpval32_rmi(i32 %a0, i32 *%p1) nounwind { +; X86-LABEL: test_lwpval32_rmi: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: lwpval $305419896, (%eax), %ecx # imm = 0x12345678 +; X86-NEXT: retl +; +; X64-LABEL: test_lwpval32_rmi: +; X64: # BB#0: +; X64-NEXT: lwpval $305419896, (%rsi), %edi # imm = 0x12345678 +; X64-NEXT: retq + %a1 = load i32, i32 *%p1 + tail call void @llvm.x86.lwpval32(i32 %a0, i32 %a1, i32 305419896) + ret void +} + +declare void @llvm.x86.llwpcb(i8*) nounwind +declare i8* @llvm.x86.slwpcb() nounwind +declare i8 @llvm.x86.lwpins32(i32, i32, i32) nounwind +declare void @llvm.x86.lwpval32(i32, i32, i32) nounwind Index: test/MC/Disassembler/X86/x86-32.txt =================================================================== --- test/MC/Disassembler/X86/x86-32.txt +++ test/MC/Disassembler/X86/x86-32.txt @@ -773,3 +773,21 @@ #CHECK: getsec 0x0f 0x37 + +#CHECK: llwpcb %ecx +0x8f 0xe9 0x78 0x12 0xc1 + +#CHECK: slwpcb %ecx +0x8f 0xe9 0x78 0x12 0xc9 + +# CHECK: lwpins $305419896, %ebx, %eax +0x8f 0xea 0x78 0x12 0xc3 0x78 0x56 0x34 0x12 + +# CHECK: lwpins $591751049, (%esp), %edx +0x8f 0xea 0x68 0x12 0x04 0x24 0x89 0x67 0x45 0x23 + +# CHECK: lwpval $1737075661, %ebx, %eax +0x8f 0xea 0x78 0x12 0xcb 0xcd 0xab 0x89 0x67 + +# CHECK: lwpval $2309737967, (%esp), %edx +0x8f 0xea 0x68 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89 Index: test/MC/Disassembler/X86/x86-64.txt =================================================================== --- test/MC/Disassembler/X86/x86-64.txt +++ test/MC/Disassembler/X86/x86-64.txt @@ -456,3 +456,27 @@ # CHECK: callq -32769 0xe8 0xff 0x7f 0xff 0xff + +# CHECK: llwpcb %rax +0x8f 0xe9 0xf8 0x12 0xc0 + +# CHECK: slwpcb %rax +0x8f 0xe9 0xf8 0x12 0xc8 + +# CHECK: lwpins $305419896, %ebx, %rax +0x8f 0xea 0xf8 0x12 0xc3 0x78 0x56 0x34 0x12 + +# CHECK: lwpins $591751049, (%rsp), %rdx +0x8f 0xea 0xe8 0x12 0x04 0x24 0x89 0x67 0x45 0x23 + +# CHECK: lwpins $591751049, (%esp), %edx +0x67 0x8f 0xea 0x68 0x12 0x04 0x24 0x89 0x67 0x45 0x23 + +# CHECK: lwpval $1737075661, %ebx, %rax +0x8f 0xea 0xf8 0x12 0xcb 0xcd 0xab 0x89 0x67 + +# CHECK: lwpval $2309737967, (%rsp), %rdx +0x8f 0xea 0xe8 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89 + +# CHECK: lwpval $2309737967, (%esp), %edx +0x67 0x8f 0xea 0x68 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89 Index: test/MC/X86/lwp-x86_64.s =================================================================== --- test/MC/X86/lwp-x86_64.s +++ test/MC/X86/lwp-x86_64.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s --check-prefix=CHECK + +llwpcb %rcx +# CHECK: llwpcb %rcx +# CHECK: encoding: [0x8f,0xe9,0xf8,0x12,0xc1] + +slwpcb %rax +# CHECK: slwpcb %rax +# CHECK: encoding: [0x8f,0xe9,0xf8,0x12,0xc8] + +lwpins $305419896, %ebx, %rax +# CHECK: lwpins $305419896, %ebx, %rax +# CHECK: encoding: [0x8f,0xea,0xf8,0x12,0xc3,0x78,0x56,0x34,0x12] + +lwpins $591751049, (%rsp), %rdx +# CHECK: lwpins $591751049, (%rsp), %rdx +# CHECK: encoding: [0x8f,0xea,0xe8,0x12,0x04,0x24,0x89,0x67,0x45,0x23] + +lwpval $1737075661, %ebx, %rax +# CHECK: lwpval $1737075661, %ebx, %rax +# CHECK: encoding: [0x8f,0xea,0xf8,0x12,0xcb,0xcd,0xab,0x89,0x67] + +lwpval $2309737967, (%rsp), %rdx +# CHECK: lwpval $2309737967, (%rsp), %rdx +# CHECK: encoding: [0x8f,0xea,0xe8,0x12,0x0c,0x24,0xef,0xcd,0xab,0x89] Index: test/MC/X86/lwp.s =================================================================== --- test/MC/X86/lwp.s +++ test/MC/X86/lwp.s @@ -0,0 +1,32 @@ +# RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-X86 +# RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-X64 + +llwpcb %ecx +# CHECK: llwpcb %ecx +# CHECK-X86: encoding: [0x8f,0xe9,0x78,0x12,0xc1] +# CHECK-X64: encoding: [0x8f,0xe9,0x78,0x12,0xc1] + +slwpcb %eax +# CHECK: slwpcb %eax +# CHECK-X86: encoding: [0x8f,0xe9,0x78,0x12,0xc8] +# CHECK-X64: encoding: [0x8f,0xe9,0x78,0x12,0xc8] + +lwpins $305419896, %ebx, %eax +# CHECK: lwpins $305419896, %ebx, %eax +# CHECK-X86: encoding: [0x8f,0xea,0x78,0x12,0xc3,0x78,0x56,0x34,0x12] +# CHECK-X64: encoding: [0x8f,0xea,0x78,0x12,0xc3,0x78,0x56,0x34,0x12] + +lwpins $591751049, (%esp), %edx +# CHECK: lwpins $591751049, (%esp), %edx +# CHECK-X86: encoding: [0x8f,0xea,0x68,0x12,0x04,0x24,0x89,0x67,0x45,0x23] +# CHECK-X64: encoding: [0x67,0x8f,0xea,0x68,0x12,0x04,0x24,0x89,0x67,0x45,0x23] + +lwpval $1737075661, %ebx, %eax +# CHECK: lwpval $1737075661, %ebx, %eax +# CHECK-X86: encoding: [0x8f,0xea,0x78,0x12,0xcb,0xcd,0xab,0x89,0x67] +# CHECK-X64: encoding: [0x8f,0xea,0x78,0x12,0xcb,0xcd,0xab,0x89,0x67] + +lwpval $2309737967, (%esp), %edx +# CHECK: lwpval $2309737967, (%esp), %edx +# CHECK-X86: encoding: [0x8f,0xea,0x68,0x12,0x0c,0x24,0xef,0xcd,0xab,0x89] +# CHECK-X64: encoding: [0x67,0x8f,0xea,0x68,0x12,0x0c,0x24,0xef,0xcd,0xab,0x89]