Index: lib/Target/Mips/MipsISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsISelLowering.cpp +++ lib/Target/Mips/MipsISelLowering.cpp @@ -245,11 +245,6 @@ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); - if (!TM.Options.NoNaNsFPMath) { - setOperationAction(ISD::FABS, MVT::f32, Custom); - setOperationAction(ISD::FABS, MVT::f64, Custom); - } - if (hasMips64()) { setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); setOperationAction(ISD::BlockAddress, MVT::i64, Custom); @@ -334,11 +329,6 @@ setOperationAction(ISD::FREM, MVT::f32, Expand); setOperationAction(ISD::FREM, MVT::f64, Expand); - if (!TM.Options.NoNaNsFPMath) { - setOperationAction(ISD::FNEG, MVT::f32, Expand); - setOperationAction(ISD::FNEG, MVT::f64, Expand); - } - setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); setOperationAction(ISD::VAARG, MVT::Other, Expand); @@ -779,7 +769,6 @@ case ISD::SETCC: return lowerSETCC(Op, DAG); case ISD::VASTART: return lowerVASTART(Op, DAG); case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); - case ISD::FABS: return lowerFABS(Op, DAG); case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); @@ -1771,65 +1760,6 @@ return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasExtractInsert()); } -static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, - bool HasExtractInsert) { - SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); - SDLoc DL(Op); - - // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it - // to i32. - SDValue X = (Op.getValueType() == MVT::f32) ? - DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : - DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), - Const1); - - // Clear MSB. - if (HasExtractInsert) - Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, - DAG.getRegister(Mips::ZERO, MVT::i32), - DAG.getConstant(31, MVT::i32), Const1, X); - else { - SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); - Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); - } - - if (Op.getValueType() == MVT::f32) - return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); - - SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, - Op.getOperand(0), DAG.getConstant(0, MVT::i32)); - return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); -} - -static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, - bool HasExtractInsert) { - SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); - SDLoc DL(Op); - - // Bitcast to integer node. - SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); - - // Clear MSB. - if (HasExtractInsert) - Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, - DAG.getRegister(Mips::ZERO_64, MVT::i64), - DAG.getConstant(63, MVT::i32), Const1, X); - else { - SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); - Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); - } - - return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); -} - -SDValue -MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { - if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) - return lowerFABS64(Op, DAG, Subtarget->hasExtractInsert()); - - return lowerFABS32(Op, DAG, Subtarget->hasExtractInsert()); -} - SDValue MipsTargetLowering:: lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { // check the depth Index: lib/Target/Mips/MipsInstrFPU.td =================================================================== --- lib/Target/Mips/MipsInstrFPU.td +++ lib/Target/Mips/MipsInstrFPU.td @@ -322,7 +322,7 @@ def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; } -let Predicates = [NoNaNsFPMath, HasStdEnc] in { +let Predicates = [HasStdEnc] in { def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, ABSS_FM<0x5, 16>; def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -176,8 +176,7 @@ AssemblerPredicate<"FeatureMips32">; def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, AssemblerPredicate<"FeatureMips32">; -def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, - AssemblerPredicate<"FeatureMips32">; +def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, AssemblerPredicate<"!FeatureMips16">; def NotDSP : Predicate<"!Subtarget.hasDSP()">; Index: test/CodeGen/Mips/fabs.ll =================================================================== --- test/CodeGen/Mips/fabs.ll +++ test/CodeGen/Mips/fabs.ll @@ -1,21 +1,20 @@ -; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s -check-prefix=32 -; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2 -; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64 -; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2 -; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=NO-NAN +; Check that abs.[ds] is selected and does not depend on -enable-no-nans-fp-math +; They obey the Has2008 and ABS2008 configuration bits which govern the +; conformance to IEEE 754 (1985) and IEEE 754 (2008). When these bits are not +; present, they confirm to 1985. +; In 1985 mode, abs.[ds] are arithmetic (i.e. they raise invalid operation +; exceptions when given NaN's). In 2008 mode, they are non-arithmetic (i.e. +; they are copies and don't raise any exceptions). + +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s define float @foo0(float %a) nounwind readnone { entry: -; 32: lui $[[T0:[0-9]+]], 32767 -; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 -; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] -; 32: mtc1 $[[AND]], $f0 - -; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1 -; 32R2: mtc1 $[[INS]], $f0 - -; NO-NAN: abs.s +; CHECK-LABEL: foo0 +; CHECK: abs.s %call = tail call float @fabsf(float %a) nounwind readnone ret float %call @@ -26,24 +25,8 @@ define double @foo1(double %a) nounwind readnone { entry: -; 32: lui $[[T0:[0-9]+]], 32767 -; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 -; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] -; 32: mtc1 $[[AND]], $f1 - -; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1 -; 32R2: mtc1 $[[INS]], $f1 - -; 64: daddiu $[[T0:[0-9]+]], $zero, 1 -; 64: dsll $[[T1:[0-9]+]], ${{[0-9]+}}, 63 -; 64: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1 -; 64: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] -; 64: dmtc1 $[[AND]], $f0 - -; 64R2: dins $[[INS:[0-9]+]], $zero, 63, 1 -; 64R2: dmtc1 $[[INS]], $f0 - -; NO-NAN: abs.d +; CHECK-LABEL: foo1: +; CHECK: abs.d %call = tail call double @fabs(double %a) nounwind readnone ret double %call Index: test/CodeGen/Mips/fmadd1.ll =================================================================== --- test/CodeGen/Mips/fmadd1.ll +++ test/CodeGen/Mips/fmadd1.ll @@ -1,3 +1,10 @@ +; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported +; correctly. +; The spec for nmadd.[ds], and nmsub.[ds] does not state that they obey the +; the Has2008 and ABS2008 configuration bits which govern the conformance to +; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only +; available when -enable-no-nans-fp-math is given. + ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefix=32R2 -check-prefix=CHECK ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=64R2 -check-prefix=CHECK ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2NAN -check-prefix=CHECK @@ -5,6 +12,7 @@ define float @FOO0float(float %a, float %b, float %c) nounwind readnone { entry: +; CHECK-LABEL: FOO0float: ; CHECK: madd.s %mul = fmul float %a, %b %add = fadd float %mul, %c @@ -14,6 +22,7 @@ define float @FOO1float(float %a, float %b, float %c) nounwind readnone { entry: +; CHECK-LABEL: FOO1float: ; CHECK: msub.s %mul = fmul float %a, %b %sub = fsub float %mul, %c @@ -23,6 +32,7 @@ define float @FOO2float(float %a, float %b, float %c) nounwind readnone { entry: +; CHECK-LABEL: FOO2float: ; 32R2: nmadd.s ; 64R2: nmadd.s ; 32R2NAN: madd.s @@ -35,6 +45,7 @@ define float @FOO3float(float %a, float %b, float %c) nounwind readnone { entry: +; CHECK-LABEL: FOO3float: ; 32R2: nmsub.s ; 64R2: nmsub.s ; 32R2NAN: msub.s @@ -47,6 +58,7 @@ define double @FOO10double(double %a, double %b, double %c) nounwind readnone { entry: +; CHECK-LABEL: FOO10double: ; CHECK: madd.d %mul = fmul double %a, %b %add = fadd double %mul, %c @@ -56,6 +68,7 @@ define double @FOO11double(double %a, double %b, double %c) nounwind readnone { entry: +; CHECK-LABEL: FOO11double: ; CHECK: msub.d %mul = fmul double %a, %b %sub = fsub double %mul, %c @@ -65,6 +78,7 @@ define double @FOO12double(double %a, double %b, double %c) nounwind readnone { entry: +; CHECK-LABEL: FOO12double: ; 32R2: nmadd.d ; 64R2: nmadd.d ; 32R2NAN: madd.d @@ -77,6 +91,7 @@ define double @FOO13double(double %a, double %b, double %c) nounwind readnone { entry: +; CHECK-LABEL: FOO13double: ; 32R2: nmsub.d ; 64R2: nmsub.d ; 32R2NAN: msub.d Index: test/CodeGen/Mips/fneg.ll =================================================================== --- test/CodeGen/Mips/fneg.ll +++ test/CodeGen/Mips/fneg.ll @@ -1,17 +1,27 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s +; Check that abs.[ds] is selected and does not depend on -enable-no-nans-fp-math +; They obey the Has2008 and ABS2008 configuration bits which govern the +; conformance to IEEE 754 (1985) and IEEE 754 (2008). When these bits are not +; present, they confirm to 1985. +; In 1985 mode, abs.[ds] are arithmetic (i.e. they raise invalid operation +; exceptions when given NaN's). In 2008 mode, they are non-arithmetic (i.e. +; they are copies and don't raise any exceptions). -define float @foo0(i32 %a, float %d) nounwind readnone { +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s + +define float @foo0(float %d) nounwind readnone { entry: -; CHECK-NOT: neg.s +; CHECK-LABEL: foo0: +; CHECK: neg.s %sub = fsub float -0.000000e+00, %d ret float %sub } -define double @foo1(i32 %a, double %d) nounwind readnone { +define double @foo1(double %d) nounwind readnone { entry: -; CHECK: foo1 -; CHECK-NOT: neg.d -; CHECK: jr +; CHECK-LABEL: foo1: +; CHECK: neg.d %sub = fsub double -0.000000e+00, %d ret double %sub }