Index: llvm/trunk/lib/Target/X86/X86InstrSSE.td =================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td @@ -6727,14 +6727,14 @@ loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>, VEX_4V, VEX_WIG; -let Predicates = [HasAVX2] in { +let Predicates = [HasAVX2, NoVLX] in defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256, loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>, VEX_4V, VEX_L, VEX_WIG; +let Predicates = [HasAVX2] in defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256, loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>, VEX_4V, VEX_L, VEX_WIG; -} let Constraints = "$src1 = $dst" in { defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128, Index: llvm/trunk/test/CodeGen/X86/avx-isa-check.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/avx-isa-check.ll +++ llvm/trunk/test/CodeGen/X86/avx-isa-check.ll @@ -680,3 +680,8 @@ %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer ret <4 x double> %c } + +define <8 x i32> @test_mul_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) #0 { + %ret = mul <8 x i32> %arg1, %arg2 + ret <8 x i32> %ret +} Index: llvm/trunk/test/CodeGen/X86/avx512vl-arith.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/avx512vl-arith.ll +++ llvm/trunk/test/CodeGen/X86/avx512vl-arith.ll @@ -176,7 +176,7 @@ define <8 x i32> @vpmulld256_test(<8 x i32> %i, <8 x i32> %j) { ; CHECK-LABEL: vpmulld256_test: ; CHECK: ## BB#0: -; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x40,0xc1] +; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x40,0xc1] ; CHECK-NEXT: retq ## encoding: [0xc3] %x = mul <8 x i32> %i, %j ret <8 x i32> %x