Index: include/llvm/Support/KnownBits.h =================================================================== --- include/llvm/Support/KnownBits.h +++ include/llvm/Support/KnownBits.h @@ -36,6 +36,20 @@ "Zero and One should have the same width!"); return Zero.getBitWidth(); } + + /// Clear all known bits. + void clearAll() { + Zero.clearAllBits(); + One.clearAllBits(); + } + + /// Set all known bits in both known and zero. + /// NOTE: This will place the known bits into a conflicted state. This should + /// only be used to prepare for intersecting with other known bits. + void setAll() { + Zero.setAllBits(); + One.setAllBits(); + } }; } // end namespace llvm Index: lib/Analysis/ValueTracking.cpp =================================================================== --- lib/Analysis/ValueTracking.cpp +++ lib/Analysis/ValueTracking.cpp @@ -342,7 +342,7 @@ // Also compute a conservative estimate for high known-0 bits. // More trickiness is possible, but this is sufficient for the // interesting case of alignment computation. - Known.One.clearAllBits(); + Known.clearAll(); unsigned TrailZ = Known.Zero.countTrailingOnes() + Known2.Zero.countTrailingOnes(); unsigned LeadZ = std::max(Known.Zero.countLeadingOnes() + @@ -351,7 +351,6 @@ TrailZ = std::min(TrailZ, BitWidth); LeadZ = std::min(LeadZ, BitWidth); - Known.Zero.clearAllBits(); Known.Zero.setLowBits(TrailZ); Known.Zero.setHighBits(LeadZ); @@ -372,8 +371,7 @@ unsigned NumRanges = Ranges.getNumOperands() / 2; assert(NumRanges >= 1); - Known.Zero.setAllBits(); - Known.One.setAllBits(); + Known.setAll(); for (unsigned i = 0; i < NumRanges; ++i) { ConstantInt *Lower = @@ -776,8 +774,7 @@ // behavior, or we might have a bug in the compiler. We can't assert/crash, so // clear out the known bits, try to warn the user, and hope for the best. if (Known.Zero.intersects(Known.One)) { - Known.Zero.clearAllBits(); - Known.One.clearAllBits(); + Known.clearAll(); if (Q.ORE) { auto *CxtI = const_cast(Q.CxtI); @@ -813,10 +810,8 @@ // If there is conflict between Known.Zero and Known.One, this must be an // overflowing left shift, so the shift result is undefined. Clear Known // bits so that other code could propagate this undef. - if ((Known.Zero & Known.One) != 0) { - Known.Zero.clearAllBits(); - Known.One.clearAllBits(); - } + if ((Known.Zero & Known.One) != 0) + Known.clearAll(); return; } @@ -826,8 +821,7 @@ // If the shift amount could be greater than or equal to the bit-width of the LHS, the // value could be undef, so we don't know anything about it. if ((~Known.Zero).uge(BitWidth)) { - Known.Zero.clearAllBits(); - Known.One.clearAllBits(); + Known.clearAll(); return; } @@ -839,8 +833,7 @@ // It would be more-clearly correct to use the two temporaries for this // calculation. Reusing the APInts here to prevent unnecessary allocations. - Known.Zero.clearAllBits(); - Known.One.clearAllBits(); + Known.clearAll(); // If we know the shifter operand is nonzero, we can sometimes infer more // known bits. However this is expensive to compute, so be lazy about it and @@ -857,8 +850,7 @@ computeKnownBits(I->getOperand(0), Known2, Depth + 1, Q); - Known.Zero.setAllBits(); - Known.One.setAllBits(); + Known.setAll(); for (unsigned ShiftAmt = 0; ShiftAmt < BitWidth; ++ShiftAmt) { // Combine the shifted known input bits only for those shift amounts // compatible with its known constraints. @@ -887,8 +879,7 @@ // stay disjoint (it should be better for some other code to actually // propagate the undef than to pick a value here using known bits). if (Known.Zero.intersects(Known.One)) { - Known.Zero.clearAllBits(); - Known.One.clearAllBits(); + Known.clearAll(); } } @@ -924,7 +915,7 @@ m_Value(Y))) || match(I->getOperand(1), m_Add(m_Specific(I->getOperand(0)), m_Value(Y))))) { - Known2.Zero.clearAllBits(); Known2.One.clearAllBits(); + Known2.clearAll(); computeKnownBits(Y, Known2, Depth + 1, Q); if (Known2.One.countTrailingOnes() > 0) Known.Zero.setBit(0); @@ -965,8 +956,7 @@ computeKnownBits(I->getOperand(0), Known2, Depth + 1, Q); unsigned LeadZ = Known2.Zero.countLeadingOnes(); - Known2.One.clearAllBits(); - Known2.Zero.clearAllBits(); + Known2.clearAll(); computeKnownBits(I->getOperand(1), Known2, Depth + 1, Q); unsigned RHSUnknownLeadingOnes = Known2.One.countLeadingZeros(); if (RHSUnknownLeadingOnes != BitWidth) @@ -1202,8 +1192,7 @@ unsigned Leaders = std::max(Known.Zero.countLeadingOnes(), Known2.Zero.countLeadingOnes()); - Known.One.clearAllBits(); - Known.Zero.clearAllBits(); + Known.clearAll(); Known.Zero.setHighBits(Leaders); break; } @@ -1357,8 +1346,7 @@ if (dyn_cast_or_null(P->hasConstantValue())) break; - Known.Zero.setAllBits(); - Known.One.setAllBits(); + Known.setAll(); for (Value *IncValue : P->incoming_values()) { // Skip direct self references. if (IncValue == P) continue; @@ -1513,7 +1501,7 @@ if (const ConstantDataSequential *CDS = dyn_cast(V)) { // We know that CDS must be a vector of integers. Take the intersection of // each element. - Known.Zero.setAllBits(); Known.One.setAllBits(); + Known.setAll(); APInt Elt(BitWidth, 0); for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { Elt = CDS->getElementAsInteger(i); @@ -1526,14 +1514,13 @@ if (const auto *CV = dyn_cast(V)) { // We know that CV must be a vector of integers. Take the intersection of // each element. - Known.Zero.setAllBits(); Known.One.setAllBits(); APInt Elt(BitWidth, 0); + Known.setAll(); for (unsigned i = 0, e = CV->getNumOperands(); i != e; ++i) { Constant *Element = CV->getAggregateElement(i); auto *ElementCI = dyn_cast_or_null(Element); if (!ElementCI) { - Known.Zero.clearAllBits(); - Known.One.clearAllBits(); + Known.clearAll(); return; } Elt = ElementCI->getValue(); @@ -1544,7 +1531,7 @@ } // Start out not knowing anything. - Known.Zero.clearAllBits(); Known.One.clearAllBits(); + Known.clearAll(); // We can't imply anything about undefs. if (isa(V)) Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2025,7 +2025,7 @@ // Collect the known bits that are shared by every demanded vector element. assert(NumElts == Op.getValueType().getVectorNumElements() && "Unexpected vector size"); - Known.Zero.setAllBits(); Known.One.setAllBits(); + Known.setAll(); for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) { if (!DemandedElts[i]) continue; @@ -2054,7 +2054,7 @@ // Collect the known bits that are shared by every vector element referenced // by the shuffle. APInt DemandedLHS(NumElts, 0), DemandedRHS(NumElts, 0); - Known.Zero.setAllBits(); Known.One.setAllBits(); + Known.setAll(); const ShuffleVectorSDNode *SVN = cast(Op); assert(NumElts == SVN->getMask().size() && "Unexpected vector size"); for (unsigned i = 0; i != NumElts; ++i) { @@ -2065,8 +2065,7 @@ if (M < 0) { // For UNDEF elements, we don't know anything about the common state of // the shuffle result. - Known.One.clearAllBits(); - Known.Zero.clearAllBits(); + Known.clearAll(); DemandedLHS.clearAllBits(); DemandedRHS.clearAllBits(); break; @@ -2097,7 +2096,7 @@ } case ISD::CONCAT_VECTORS: { // Split DemandedElts and test each of the demanded subvectors. - Known.Zero.setAllBits(); Known.One.setAllBits(); + Known.setAll(); EVT SubVectorVT = Op.getOperand(0).getValueType(); unsigned NumSubVectorElts = SubVectorVT.getVectorNumElements(); unsigned NumSubVectors = Op.getNumOperands(); @@ -2188,7 +2187,7 @@ computeKnownBits(N0, Known2, SubDemandedElts, Depth + 1); - Known.Zero.setAllBits(); Known.One.setAllBits(); + Known.setAll(); for (unsigned i = 0; i != NumElts; ++i) if (DemandedElts[i]) { unsigned Offset = (i % SubScale) * BitWidth; @@ -2239,14 +2238,13 @@ // Also compute a conservative estimate for high known-0 bits. // More trickiness is possible, but this is sufficient for the // interesting case of alignment computation. - Known.One.clearAllBits(); + Known.clearAll(); unsigned TrailZ = Known.Zero.countTrailingOnes() + Known2.Zero.countTrailingOnes(); unsigned LeadZ = std::max(Known.Zero.countLeadingOnes() + Known2.Zero.countLeadingOnes(), BitWidth) - BitWidth; - Known.Zero.clearAllBits(); Known.Zero.setLowBits(std::min(TrailZ, BitWidth)); Known.Zero.setHighBits(std::min(LeadZ, BitWidth)); break; @@ -2611,8 +2609,7 @@ uint32_t Leaders = std::max(Known.Zero.countLeadingOnes(), Known2.Zero.countLeadingOnes()); - Known.One.clearAllBits(); - Known.Zero.clearAllBits(); + Known.clearAll(); Known.Zero.setHighBits(Leaders); break; } Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp =================================================================== --- lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -548,7 +548,7 @@ return false; // Don't fall through, will infinitely loop. case ISD::BUILD_VECTOR: // Collect the known bits that are shared by every constant vector element. - Known.Zero.setAllBits(); Known.One.setAllBits(); + Known.setAll(); for (SDValue SrcOp : Op->ops()) { if (!isa(SrcOp)) { // We can only handle all constant values - bail out with no known bits. @@ -1314,7 +1314,7 @@ Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!"); - Known.Zero.clearAllBits(); Known.One.clearAllBits(); + Known.clearAll(); } /// This method can be implemented by targets that want to expose additional Index: lib/Target/AMDGPU/AMDGPUISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -3577,7 +3577,7 @@ const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const { - Known.Zero.clearAllBits(); Known.One.clearAllBits(); // Don't know anything. + Known.clearAll(); // Don't know anything. KnownBits Known2; unsigned Opc = Op.getOpcode(); Index: lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- lib/Target/ARM/ARMISelLowering.cpp +++ lib/Target/ARM/ARMISelLowering.cpp @@ -12602,7 +12602,7 @@ const SelectionDAG &DAG, unsigned Depth) const { unsigned BitWidth = Known.getBitWidth(); - Known.Zero.clearAllBits(); Known.One.clearAllBits(); + Known.clearAll(); switch (Op.getOpcode()) { default: break; case ARMISD::ADDC: Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp +++ lib/Target/PowerPC/PPCISelLowering.cpp @@ -12016,7 +12016,7 @@ const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const { - Known.Zero.clearAllBits(); Known.One.clearAllBits(); + Known.clearAll(); switch (Op.getOpcode()) { default: break; case PPCISD::LBRX: { Index: lib/Target/Sparc/SparcISelLowering.cpp =================================================================== --- lib/Target/Sparc/SparcISelLowering.cpp +++ lib/Target/Sparc/SparcISelLowering.cpp @@ -1881,7 +1881,7 @@ const SelectionDAG &DAG, unsigned Depth) const { KnownBits Known2; - Known.Zero.clearAllBits(); Known.One.clearAllBits(); + Known.clearAll(); switch (Op.getOpcode()) { default: break; Index: lib/Target/XCore/XCoreISelLowering.cpp =================================================================== --- lib/Target/XCore/XCoreISelLowering.cpp +++ lib/Target/XCore/XCoreISelLowering.cpp @@ -1825,7 +1825,7 @@ const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const { - Known.Zero.clearAllBits(); Known.One.clearAllBits(); + Known.clearAll(); switch (Op.getOpcode()) { default: break; case XCoreISD::LADD: Index: lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp =================================================================== --- lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -120,8 +120,7 @@ return nullptr; } - Known.Zero.clearAllBits(); - Known.One.clearAllBits(); + Known.clearAll(); if (DemandedMask == 0) // Not demanding any bits from V. return UndefValue::get(VTy);