Index: include/llvm/CodeGen/Passes.h =================================================================== --- include/llvm/CodeGen/Passes.h +++ include/llvm/CodeGen/Passes.h @@ -323,8 +323,9 @@ /// pointer or stack pointer index addressing. extern char &LocalStackSlotAllocationID; - /// ExpandISelPseudos - This pass expands pseudo-instructions. - extern char &ExpandISelPseudosID; + /// This pass expands pseudo-instructions, reserves registers and adjusts + /// machine frame information. + extern char &FinalizeISelID; /// UnpackMachineBundles - This pass unpack machine instruction bundles. extern char &UnpackMachineBundlesID; Index: include/llvm/InitializePasses.h =================================================================== --- include/llvm/InitializePasses.h +++ include/llvm/InitializePasses.h @@ -128,10 +128,10 @@ void initializeEdgeBundlesPass(PassRegistry&); void initializeEfficiencySanitizerPass(PassRegistry&); void initializeEliminateAvailableExternallyLegacyPassPass(PassRegistry&); -void initializeExpandISelPseudosPass(PassRegistry&); void initializeExpandPostRAPass(PassRegistry&); void initializeExternalAAWrapperPassPass(PassRegistry&); void initializeFEntryInserterPass(PassRegistry&); +void initializeFinalizeISelPass(PassRegistry&); void initializeFinalizeMachineBundlesPass(PassRegistry&); void initializeFlattenCFGPassPass(PassRegistry&); void initializeFloat2IntLegacyPassPass(PassRegistry&); Index: lib/CodeGen/CMakeLists.txt =================================================================== --- lib/CodeGen/CMakeLists.txt +++ lib/CodeGen/CMakeLists.txt @@ -21,10 +21,10 @@ EarlyIfConversion.cpp EdgeBundles.cpp ExecutionDepsFix.cpp - ExpandISelPseudos.cpp ExpandPostRAPseudos.cpp FaultMaps.cpp FEntryInserter.cpp + FinalizeISel.cpp FuncletLayout.cpp GCMetadata.cpp GCMetadataPrinter.cpp Index: lib/CodeGen/CodeGen.cpp =================================================================== --- lib/CodeGen/CodeGen.cpp +++ lib/CodeGen/CodeGen.cpp @@ -30,9 +30,9 @@ initializeDetectDeadLanesPass(Registry); initializeDwarfEHPreparePass(Registry); initializeEarlyIfConverterPass(Registry); - initializeExpandISelPseudosPass(Registry); initializeExpandPostRAPass(Registry); initializeFEntryInserterPass(Registry); + initializeFinalizeISelPass(Registry); initializeFinalizeMachineBundlesPass(Registry); initializeFuncletLayoutPass(Registry); initializeGCMachineCodeAnalysisPass(Registry); Index: lib/CodeGen/FinalizeISel.cpp =================================================================== --- lib/CodeGen/FinalizeISel.cpp +++ lib/CodeGen/FinalizeISel.cpp @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/ExpandISelPseudos.cpp ----------------------*- C++ -*-===// +//===-- llvm/CodeGen/FinalizeISel.cpp ---------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,10 +7,11 @@ // //===----------------------------------------------------------------------===// // -// Expand Pseudo-instructions produced by ISel. These are usually to allow -// the expansion to contain control flow, such as a conditional move -// implemented with a conditional branch and a phi, or an atomic operation -// implemented with a loop. +/// This pass expands Pseudo-instructions produced by ISel, fixes register +/// reservations and may do machine frame information adjustments. +/// The pseudo instructions are used to allow the expansion to contain control +/// flow, such as a conditional move implemented with a conditional branch and a +/// phi, or an atomic operation implemented with a loop. // //===----------------------------------------------------------------------===// @@ -22,13 +23,13 @@ #include "llvm/Target/TargetSubtargetInfo.h" using namespace llvm; -#define DEBUG_TYPE "expand-isel-pseudos" +#define DEBUG_TYPE "finalize-isel" namespace { - class ExpandISelPseudos : public MachineFunctionPass { + class FinalizeISel : public MachineFunctionPass { public: static char ID; // Pass identification, replacement for typeid - ExpandISelPseudos() : MachineFunctionPass(ID) {} + FinalizeISel() : MachineFunctionPass(ID) {} private: bool runOnMachineFunction(MachineFunction &MF) override; @@ -39,12 +40,12 @@ }; } // end anonymous namespace -char ExpandISelPseudos::ID = 0; -char &llvm::ExpandISelPseudosID = ExpandISelPseudos::ID; -INITIALIZE_PASS(ExpandISelPseudos, "expand-isel-pseudos", +char FinalizeISel::ID = 0; +char &llvm::FinalizeISelID = FinalizeISel::ID; +INITIALIZE_PASS(FinalizeISel, "finalize-isel", "Expand ISel Pseudo-instructions", false, false) -bool ExpandISelPseudos::runOnMachineFunction(MachineFunction &MF) { +bool FinalizeISel::runOnMachineFunction(MachineFunction &MF) { bool Changed = false; const TargetLowering *TLI = MF.getSubtarget().getTargetLowering(); @@ -70,5 +71,7 @@ } } + TLI->finalizeLowering(MF); + return Changed; } Index: lib/CodeGen/MachineVerifier.cpp =================================================================== --- lib/CodeGen/MachineVerifier.cpp +++ lib/CodeGen/MachineVerifier.cpp @@ -189,7 +189,8 @@ } bool isAllocatable(unsigned Reg) { - return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg); + return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) && + !regsReserved.test(Reg); } // Analysis information if available @@ -526,7 +527,8 @@ void MachineVerifier::visitMachineFunctionBefore() { lastIndex = SlotIndex(); - regsReserved = MRI->getReservedRegs(); + regsReserved = MRI->reservedRegsFrozen() + ? MRI->getReservedRegs() : TRI->getReservedRegs(*MF); if (!MF->empty()) markReachable(&MF->front()); Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -7369,7 +7369,7 @@ /// avoid constant materialization and register allocation. /// /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not -/// generate addess computation nodes, and so ExpandISelPseudo can convert the +/// generate addess computation nodes, and so FinalizeISel can convert the /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids /// address materialization and register allocation, but may also be required /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an Index: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -592,8 +592,6 @@ MRI.replaceRegWith(From, To); } - TLI->finalizeLowering(*MF); - // Release function-specific state. SDB and CurDAG are already cleared // at this point. FuncInfo->clear(); Index: lib/CodeGen/TargetPassConfig.cpp =================================================================== --- lib/CodeGen/TargetPassConfig.cpp +++ lib/CodeGen/TargetPassConfig.cpp @@ -596,7 +596,7 @@ addPass(createRegUsageInfoPropPass()); // Expand pseudo-instructions emitted by ISel. - addPass(&ExpandISelPseudosID); + addPass(&FinalizeISelID); // Add passes that optimize machine instructions in SSA form. if (getOptLevel() != CodeGenOpt::None) { Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp +++ lib/Target/X86/X86ISelLowering.cpp @@ -20375,7 +20375,7 @@ MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); MFI.setHasCopyImplyingStackAdjustment(true); // Don't do anything here, we will expand these intrinsics out later - // during ExpandISelPseudos in EmitInstrWithCustomInserter. + // during FinalizeISel in EmitInstrWithCustomInserter. return SDValue(); } return SDValue(); Index: test/CodeGen/ARM/Windows/dbzchk.ll =================================================================== --- test/CodeGen/ARM/Windows/dbzchk.ll +++ test/CodeGen/ARM/Windows/dbzchk.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV +; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV ; int f(int n, int d) { ; if (n / d) @@ -40,7 +40,7 @@ ; CHECK-DIV-DAG: Successors according to CFG: BB#3 ; CHECK-DIV-DAG: BB#3 -; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD +; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD ; int r; ; int g(int l, int m) { @@ -74,7 +74,7 @@ ; CHECK-MOD-DAG: Successors according to CFG: BB#2 ; CHECK-MOD-DAG: BB#2 -; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG +; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=finalize-isel -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG ; RUN: llc -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM ; unsigned c; Index: test/CodeGen/X86/MachineBranchProb.ll =================================================================== --- test/CodeGen/X86/MachineBranchProb.ll +++ test/CodeGen/X86/MachineBranchProb.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -print-machineinstrs=finalize-isel -o /dev/null 2>&1 | FileCheck %s ;; Make sure a transformation in SelectionDAGBuilder that converts "or + br" to ;; two branches correctly updates the branch probability.