Index: include/llvm/CodeGen/Passes.h
===================================================================
--- include/llvm/CodeGen/Passes.h
+++ include/llvm/CodeGen/Passes.h
@@ -345,8 +345,9 @@
   /// pointer or stack pointer index addressing.
   extern char &LocalStackSlotAllocationID;
 
-  /// ExpandISelPseudos - This pass expands pseudo-instructions.
-  extern char &ExpandISelPseudosID;
+  /// This pass expands pseudo-instructions, reserves registers and adjusts
+  /// machine frame information.
+  extern char &FinalizeISelID;
 
   /// UnpackMachineBundles - This pass unpack machine instruction bundles.
   extern char &UnpackMachineBundlesID;
Index: include/llvm/InitializePasses.h
===================================================================
--- include/llvm/InitializePasses.h
+++ include/llvm/InitializePasses.h
@@ -136,13 +136,13 @@
 void initializeEdgeBundlesPass(PassRegistry&);
 void initializeEliminateAvailableExternallyLegacyPassPass(PassRegistry&);
 void initializeEntryExitInstrumenterPass(PassRegistry&);
-void initializeExpandISelPseudosPass(PassRegistry&);
 void initializeExpandMemCmpPassPass(PassRegistry&);
 void initializeExpandPostRAPass(PassRegistry&);
 void initializeExpandReductionsPass(PassRegistry&);
 void initializeMakeGuardsExplicitLegacyPassPass(PassRegistry&);
 void initializeExternalAAWrapperPassPass(PassRegistry&);
 void initializeFEntryInserterPass(PassRegistry&);
+void initializeFinalizeISelPass(PassRegistry&);
 void initializeFinalizeMachineBundlesPass(PassRegistry&);
 void initializeFlattenCFGPassPass(PassRegistry&);
 void initializeFloat2IntLegacyPassPass(PassRegistry&);
Index: lib/CodeGen/CMakeLists.txt
===================================================================
--- lib/CodeGen/CMakeLists.txt
+++ lib/CodeGen/CMakeLists.txt
@@ -21,12 +21,12 @@
   EarlyIfConversion.cpp
   EdgeBundles.cpp
   ExecutionDomainFix.cpp
-  ExpandISelPseudos.cpp
   ExpandMemCmp.cpp
   ExpandPostRAPseudos.cpp
   ExpandReductions.cpp
   FaultMaps.cpp
   FEntryInserter.cpp
+  FinalizeISel.cpp
   FuncletLayout.cpp
   GCMetadata.cpp
   GCMetadataPrinter.cpp
Index: lib/CodeGen/CodeGen.cpp
===================================================================
--- lib/CodeGen/CodeGen.cpp
+++ lib/CodeGen/CodeGen.cpp
@@ -30,10 +30,10 @@
   initializeEarlyIfConverterPass(Registry);
   initializeEarlyMachineLICMPass(Registry);
   initializeEarlyTailDuplicatePass(Registry);
-  initializeExpandISelPseudosPass(Registry);
   initializeExpandMemCmpPassPass(Registry);
   initializeExpandPostRAPass(Registry);
   initializeFEntryInserterPass(Registry);
+  initializeFinalizeISelPass(Registry);
   initializeFinalizeMachineBundlesPass(Registry);
   initializeFuncletLayoutPass(Registry);
   initializeGCMachineCodeAnalysisPass(Registry);
Index: lib/CodeGen/FinalizeISel.cpp
===================================================================
--- lib/CodeGen/FinalizeISel.cpp
+++ lib/CodeGen/FinalizeISel.cpp
@@ -1,4 +1,4 @@
-//===-- llvm/CodeGen/ExpandISelPseudos.cpp ----------------------*- C++ -*-===//
+//===-- llvm/CodeGen/FinalizeISel.cpp ---------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,10 +6,11 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Expand Pseudo-instructions produced by ISel. These are usually to allow
-// the expansion to contain control flow, such as a conditional move
-// implemented with a conditional branch and a phi, or an atomic operation
-// implemented with a loop.
+/// This pass expands Pseudo-instructions produced by ISel, fixes register
+/// reservations and may do machine frame information adjustments.
+/// The pseudo instructions are used to allow the expansion to contain control
+/// flow, such as a conditional move implemented with a conditional branch and a
+/// phi, or an atomic operation implemented with a loop.
 //
 //===----------------------------------------------------------------------===//
 
@@ -21,13 +22,13 @@
 #include "llvm/Support/Debug.h"
 using namespace llvm;
 
-#define DEBUG_TYPE "expand-isel-pseudos"
+#define DEBUG_TYPE "finalize-isel"
 
 namespace {
-  class ExpandISelPseudos : public MachineFunctionPass {
+  class FinalizeISel : public MachineFunctionPass {
   public:
     static char ID; // Pass identification, replacement for typeid
-    ExpandISelPseudos() : MachineFunctionPass(ID) {}
+    FinalizeISel() : MachineFunctionPass(ID) {}
 
   private:
     bool runOnMachineFunction(MachineFunction &MF) override;
@@ -38,12 +39,12 @@
   };
 } // end anonymous namespace
 
-char ExpandISelPseudos::ID = 0;
-char &llvm::ExpandISelPseudosID = ExpandISelPseudos::ID;
-INITIALIZE_PASS(ExpandISelPseudos, DEBUG_TYPE,
-                "Expand ISel Pseudo-instructions", false, false)
+char FinalizeISel::ID = 0;
+char &llvm::FinalizeISelID = FinalizeISel::ID;
+INITIALIZE_PASS(FinalizeISel, DEBUG_TYPE,
+                "Finalize ISel and expand pseudo-instructions", false, false)
 
-bool ExpandISelPseudos::runOnMachineFunction(MachineFunction &MF) {
+bool FinalizeISel::runOnMachineFunction(MachineFunction &MF) {
   bool Changed = false;
   const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
 
@@ -69,5 +70,7 @@
     }
   }
 
+  TLI->finalizeLowering(MF);
+
   return Changed;
 }
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -218,7 +218,7 @@
 
     bool isAllocatable(unsigned Reg) const {
       return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
-        !regsReserved.test(Reg);
+             !regsReserved.test(Reg);
     }
 
     // Analysis information if available
Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -8560,7 +8560,7 @@
 /// avoid constant materialization and register allocation.
 ///
 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
-/// generate addess computation nodes, and so ExpandISelPseudo can convert the
+/// generate addess computation nodes, and so FinalizeISel can convert the
 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
 /// address materialization and register allocation, but may also be required
 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
Index: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -652,8 +652,6 @@
     MRI.replaceRegWith(From, To);
   }
 
-  TLI->finalizeLowering(*MF);
-
   // Release function-specific state. SDB and CurDAG are already cleared
   // at this point.
   FuncInfo->clear();
Index: lib/CodeGen/TargetPassConfig.cpp
===================================================================
--- lib/CodeGen/TargetPassConfig.cpp
+++ lib/CodeGen/TargetPassConfig.cpp
@@ -815,6 +815,13 @@
   } else if (addInstSelector())
     return true;
 
+  // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
+  // FinalizeISel.
+  addPass(&FinalizeISelID);
+
+  // Print the instruction selected machine code...
+  printAndVerify("After Instruction Selection");
+
   return false;
 }
 
@@ -874,12 +881,6 @@
     }
   }
 
-  // Print the instruction selected machine code...
-  printAndVerify("After Instruction Selection");
-
-  // Expand pseudo-instructions emitted by ISel.
-  addPass(&ExpandISelPseudosID);
-
   // Add passes that optimize machine instructions in SSA form.
   if (getOptLevel() != CodeGenOpt::None) {
     addMachineSSAOptimization();
Index: lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -744,7 +744,8 @@
 }
 
 bool AMDGPUPassConfig::addInstSelector() {
-  addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
+  // Defer the verifier until FinalizeISel.
+  addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
   return false;
 }
 
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -23248,7 +23248,7 @@
       MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
       MFI.setHasCopyImplyingStackAdjustment(true);
       // Don't do anything here, we will expand these intrinsics out later
-      // during ExpandISelPseudos in EmitInstrWithCustomInserter.
+      // during FinalizeISel in EmitInstrWithCustomInserter.
       return SDValue();
     }
     case Intrinsic::x86_lwpins32:
Index: test/CodeGen/AArch64/GlobalISel/gisel-commandline-option-fastisel.ll
===================================================================
--- test/CodeGen/AArch64/GlobalISel/gisel-commandline-option-fastisel.ll
+++ test/CodeGen/AArch64/GlobalISel/gisel-commandline-option-fastisel.ll
@@ -25,7 +25,7 @@
 ; DISABLED-NOT: IRTranslator
 
 ; DISABLED: AArch64 Instruction Selection
-; DISABLED: Expand ISel Pseudo-instructions
+; DISABLED: Finalize ISel and expand pseudo-instructions
 
 ; FASTISEL: Enabling fast-isel
 ; NOFASTISEL-NOT: Enabling fast-isel
Index: test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
===================================================================
--- test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
+++ test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
@@ -62,7 +62,7 @@
 ; DISABLED-NOT: IRTranslator
 
 ; DISABLED: AArch64 Instruction Selection
-; DISABLED: Expand ISel Pseudo-instructions
+; DISABLED: Finalize ISel and expand pseudo-instructions
 
 define void @empty() {
   ret void
Index: test/CodeGen/AArch64/O0-pipeline.ll
===================================================================
--- test/CodeGen/AArch64/O0-pipeline.ll
+++ test/CodeGen/AArch64/O0-pipeline.ll
@@ -42,7 +42,7 @@
 ; CHECK-NEXT:       InstructionSelect
 ; CHECK-NEXT:       ResetMachineFunction
 ; CHECK-NEXT:       AArch64 Instruction Selection
-; CHECK-NEXT:       Expand ISel Pseudo-instructions
+; CHECK-NEXT:       Finalize ISel and expand pseudo-instructions
 ; CHECK-NEXT:       Local Stack Slot Allocation
 ; CHECK-NEXT:       Eliminate PHI nodes for register allocation
 ; CHECK-NEXT:       Two-Address instruction pass
Index: test/CodeGen/AArch64/O3-pipeline.ll
===================================================================
--- test/CodeGen/AArch64/O3-pipeline.ll
+++ test/CodeGen/AArch64/O3-pipeline.ll
@@ -76,7 +76,7 @@
 ; CHECK-NEXT:       AArch64 Instruction Selection
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       AArch64 Local Dynamic TLS Access Clean-up
-; CHECK-NEXT:       Expand ISel Pseudo-instructions
+; CHECK-NEXT:       Finalize ISel and expand pseudo-instructions
 ; CHECK-NEXT:       Early Tail Duplication
 ; CHECK-NEXT:       Optimize machine instruction PHIs
 ; CHECK-NEXT:       Slot index numbering
Index: test/CodeGen/AArch64/apple-latest-cpu.ll
===================================================================
--- test/CodeGen/AArch64/apple-latest-cpu.ll
+++ test/CodeGen/AArch64/apple-latest-cpu.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm64-apple-ios -mcpu=apple-latest -stop-before=expand-isel-pseudos -o - 2>&1 < %s | FileCheck %s
+; RUN: llc -mtriple=arm64-apple-ios -mcpu=apple-latest -stop-before=finalize-isel -o - 2>&1 < %s | FileCheck %s
 
 ; CHECK-LABEL: @dummy
 ; CHECK: "target-cpu"="apple-latest"
Index: test/CodeGen/AArch64/arm64-fast-isel-rem.ll
===================================================================
--- test/CodeGen/AArch64/arm64-fast-isel-rem.ll
+++ test/CodeGen/AArch64/arm64-fast-isel-rem.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
-; RUN: llc %s -O0 -fast-isel -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
+; RUN: llc %s -O0 -fast-isel -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-after=finalize-isel -o /dev/null 2> %t
 ; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
 
 ; CHECK-SSA-LABEL: Machine code for function t1
Index: test/CodeGen/AArch64/fast-isel-dbg.ll
===================================================================
--- test/CodeGen/AArch64/fast-isel-dbg.ll
+++ test/CodeGen/AArch64/fast-isel-dbg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -o - %s -fast-isel -stop-before=expand-isel-pseudos | FileCheck %s
+; RUN: llc -o - %s -fast-isel -stop-before=finalize-isel | FileCheck %s
 ; Make sure fast-isel produces DBG_VALUE instructions even if no debug printer
 ; is scheduled because of -stop-before.
 target triple="aarch64--"
Index: test/CodeGen/AArch64/tail-call-unused-zext.ll
===================================================================
--- test/CodeGen/AArch64/tail-call-unused-zext.ll
+++ test/CodeGen/AArch64/tail-call-unused-zext.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm64--- -stop-after=expand-isel-pseudos -o - %s | FileCheck %s
+; RUN: llc -mtriple=arm64--- -stop-after=finalize-isel -o - %s | FileCheck %s
 
 ; Check that we ignore the zeroext attribute on the return type of the tail
 ; call, since the return value is unused. This happens during CodeGenPrepare in
Index: test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
===================================================================
--- test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
+++ test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
@@ -1,4 +1,4 @@
-; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos | FileCheck %s
+; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after finalize-isel | FileCheck %s
 ; This test verifies that the instruction selection will add the implicit
 ; register operands in the correct order when modifying the opcode of an
 ; instruction to V_ADD_I32_e32.
Index: test/CodeGen/ARM/GlobalISel/pr35375.ll
===================================================================
--- test/CodeGen/ARM/GlobalISel/pr35375.ll
+++ test/CodeGen/ARM/GlobalISel/pr35375.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -mtriple armv7-- -stop-before=expand-isel-pseudos < %s
-; RUN: llc -O0 -mtriple armv7-- -stop-before=expand-isel-pseudos -global-isel < %s
+; RUN: llc -O0 -mtriple armv7-- -stop-before=finalize-isel < %s
+; RUN: llc -O0 -mtriple armv7-- -stop-before=finalize-isel -global-isel < %s
 
 ; CHECK: PKHBT
 
Index: test/CodeGen/ARM/O3-pipeline.ll
===================================================================
--- test/CodeGen/ARM/O3-pipeline.ll
+++ test/CodeGen/ARM/O3-pipeline.ll
@@ -58,7 +58,7 @@
 ; CHECK-NEXT:      Natural Loop Information
 ; CHECK-NEXT:      Branch Probability Analysis
 ; CHECK-NEXT:      ARM Instruction Selection
-; CHECK-NEXT:      Expand ISel Pseudo-instructions
+; CHECK-NEXT:      Finalize ISel and expand pseudo-instructions
 ; CHECK-NEXT:      Early Tail Duplication
 ; CHECK-NEXT:      Optimize machine instruction PHIs
 ; CHECK-NEXT:      Slot index numbering
Index: test/CodeGen/ARM/Windows/dbzchk.ll
===================================================================
--- test/CodeGen/ARM/Windows/dbzchk.ll
+++ test/CodeGen/ARM/Windows/dbzchk.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV
+; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV
 
 ; int f(int n, int d) {
 ;   if (n / d)
@@ -40,7 +40,7 @@
 ; CHECK-DIV-DAG: successors: %bb.3
 ; CHECK-DIV-DAG: %bb.3
 
-; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD
+; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD
 
 ; int r;
 ; int g(int l, int m) {
@@ -74,7 +74,7 @@
 ; CHECK-MOD-DAG: successors: %bb.2
 ; CHECK-MOD-DAG: %bb.2
 
-; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG
+; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG
 ; RUN: llc -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM
 
 ; unsigned c;
Index: test/CodeGen/ARM/Windows/vla-cpsr.ll
===================================================================
--- test/CodeGen/ARM/Windows/vla-cpsr.ll
+++ test/CodeGen/ARM/Windows/vla-cpsr.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-machineinstrs=expand-isel-pseudos 2>&1 | FileCheck %s
+; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-after=finalize-isel 2>&1 | FileCheck %s
 
 declare arm_aapcs_vfpcc void @g(i8*) local_unnamed_addr
 
Index: test/CodeGen/ARM/copy-by-struct-i32.ll
===================================================================
--- test/CodeGen/ARM/copy-by-struct-i32.ll
+++ test/CodeGen/ARM/copy-by-struct-i32.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=armv7-unknown-linux < %s -stop-before=expand-isel-pseudos | FileCheck --check-prefix=BEFORE-EXPAND %s
+; RUN: llc -mtriple=armv7-unknown-linux < %s -stop-before=finalize-isel | FileCheck --check-prefix=BEFORE-EXPAND %s
 ; RUN: llc -mtriple=armv7-unknown-linux < %s | FileCheck --check-prefix=ASSEMBLY %s
 
 ; Check COPY_STRUCT_BYVAL_I32 has CPSR as operand.
Index: test/CodeGen/Generic/MachineBranchProb.ll
===================================================================
--- test/CodeGen/Generic/MachineBranchProb.ll
+++ test/CodeGen/Generic/MachineBranchProb.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
+; RUN: llc < %s -print-after=finalize-isel -o /dev/null 2>&1 | FileCheck %s
 
 ; Hexagon runs passes that renumber the basic blocks, causing this test
 ; to fail.
Index: test/CodeGen/Hexagon/call-v4.ll
===================================================================
--- test/CodeGen/Hexagon/call-v4.ll
+++ test/CodeGen/Hexagon/call-v4.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 < %s | FileCheck %s
+; RUN: llc -march=hexagon -print-after=finalize-isel -o /dev/null 2>&1 < %s | FileCheck %s
 ; REQUIRES: asserts
 
 ; CHECK: J2_call @f1
Index: test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
===================================================================
--- test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
+++ test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
@@ -2,7 +2,7 @@
 # RUN:     -verify-machineinstrs %s -o - | FileCheck %s
 #
 # RUN: llc -mtriple aarch64-- -global-isel=true -global-isel-abort=2 \
-# RUN:     -start-after=regbankselect -stop-before=expand-isel-pseudos \
+# RUN:     -start-after=regbankselect -stop-before=finalize-isel \
 # RUN:     -simplify-mir -verify-machineinstrs %s -o - 2>&1 \
 # RUN:    | FileCheck %s --check-prefix=FALLBACK
 
Index: test/CodeGen/MIR/AMDGPU/machine-function-info.ll
===================================================================
--- test/CodeGen/MIR/AMDGPU/machine-function-info.ll
+++ test/CodeGen/MIR/AMDGPU/machine-function-info.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after expand-isel-pseudos -o %t.mir %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s
 ; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s
 
 ; Test that SIMachineFunctionInfo can be round trip serialized through
Index: test/CodeGen/MIR/Generic/multiRunPass.mir
===================================================================
--- test/CodeGen/MIR/Generic/multiRunPass.mir
+++ test/CodeGen/MIR/Generic/multiRunPass.mir
@@ -1,15 +1,15 @@
-# RUN: llc -run-pass expand-isel-pseudos  -run-pass peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE
-# RUN: llc -run-pass expand-isel-pseudos,peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE
-# RUN: llc -run-pass peephole-opt -run-pass expand-isel-pseudos -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO
-# RUN: llc -run-pass peephole-opt,expand-isel-pseudos -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO
+# RUN: llc -run-pass finalize-isel  -run-pass peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE
+# RUN: llc -run-pass finalize-isel,peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE
+# RUN: llc -run-pass peephole-opt -run-pass finalize-isel -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO
+# RUN: llc -run-pass peephole-opt,finalize-isel -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO
 # REQUIRES: asserts
 
 # This test ensures that the command line accepts
 # several run passes on the same command line and
 # actually create the proper pipeline for it.
-# PSEUDO_PEEPHOLE: -expand-isel-pseudos
+# PSEUDO_PEEPHOLE: -finalize-isel
 # PSEUDO_PEEPHOLE-SAME: {{(-machineverifier )?}}-peephole-opt
-# PEEPHOLE_PSEUDO: -peephole-opt {{(-machineverifier )?}}-expand-isel-pseudos
+# PEEPHOLE_PSEUDO: -peephole-opt {{(-machineverifier )?}}-finalize-isel
 
 # Make sure there are no other passes happening after what we asked.
 # CHECK-NEXT: --- |
Index: test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll
===================================================================
--- test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll
+++ test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll
@@ -1,16 +1,16 @@
 ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
 ; RUN:     -mcpu=mips32 -mattr=+fpxx \
-; RUN:     -stop-after=expand-isel-pseudos | \
+; RUN:     -stop-after=finalize-isel | \
 ; RUN:     FileCheck %s -check-prefix=FPXX-IMPLICIT-SP
 
 ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
 ; RUN:     -mcpu=mips32r6 -mattr=+fp64,+nooddspreg \
-; RUN:     -stop-after=expand-isel-pseudos | \
+; RUN:     -stop-after=finalize-isel | \
 ; RUN:     FileCheck %s -check-prefix=FP64-IMPLICIT-SP
 
 ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
 ; RUN:     -mcpu=mips32r2 -mattr=+fpxx \
-; RUN:     -stop-after=expand-isel-pseudos | \
+; RUN:     -stop-after=finalize-isel | \
 ; RUN:     FileCheck %s -check-prefix=NO-IMPLICIT-SP
 
 define double @foo2(i32 signext %v1, double %d1) {
Index: test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir
===================================================================
--- test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir
+++ test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir
@@ -1,5 +1,5 @@
 # RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \
-# RUN:         -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN:         -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \
 # RUN:   | FileCheck %s
 
Index: test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir
===================================================================
--- test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir
+++ test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir
@@ -1,5 +1,5 @@
 # RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \
-# RUN:         -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN:         -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \
 # RUN:   | FileCheck %s
 
Index: test/CodeGen/Mips/instverify/dext-pos.mir
===================================================================
--- test/CodeGen/Mips/instverify/dext-pos.mir
+++ test/CodeGen/Mips/instverify/dext-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position operand is out of range!
Index: test/CodeGen/Mips/instverify/dext-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/dext-size.mir
+++ test/CodeGen/Mips/instverify/dext-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Size operand is out of range!
Index: test/CodeGen/Mips/instverify/dextm-pos-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/dextm-pos-size.mir
+++ test/CodeGen/Mips/instverify/dextm-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position + Size is out of range!
Index: test/CodeGen/Mips/instverify/dextm-pos.mir
===================================================================
--- test/CodeGen/Mips/instverify/dextm-pos.mir
+++ test/CodeGen/Mips/instverify/dextm-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position operand is out of range!
Index: test/CodeGen/Mips/instverify/dextm-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/dextm-size.mir
+++ test/CodeGen/Mips/instverify/dextm-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Size operand is out of range!
Index: test/CodeGen/Mips/instverify/dextu-pos-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/dextu-pos-size.mir
+++ test/CodeGen/Mips/instverify/dextu-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position + Size is out of range!
Index: test/CodeGen/Mips/instverify/dextu-pos.mir
===================================================================
--- test/CodeGen/Mips/instverify/dextu-pos.mir
+++ test/CodeGen/Mips/instverify/dextu-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position operand is out of range!
Index: test/CodeGen/Mips/instverify/dextu-size-valid.mir
===================================================================
--- test/CodeGen/Mips/instverify/dextu-size-valid.mir
+++ test/CodeGen/Mips/instverify/dextu-size-valid.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:     -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK-NOT: Size operand is out of range!
Index: test/CodeGen/Mips/instverify/dextu-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/dextu-size.mir
+++ test/CodeGen/Mips/instverify/dextu-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Size operand is out of range!
Index: test/CodeGen/Mips/instverify/dins-pos-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/dins-pos-size.mir
+++ test/CodeGen/Mips/instverify/dins-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position + Size is out of range!
Index: test/CodeGen/Mips/instverify/dins-pos.mir
===================================================================
--- test/CodeGen/Mips/instverify/dins-pos.mir
+++ test/CodeGen/Mips/instverify/dins-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position operand is out of range!
Index: test/CodeGen/Mips/instverify/dins-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/dins-size.mir
+++ test/CodeGen/Mips/instverify/dins-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Size operand is out of range!
Index: test/CodeGen/Mips/instverify/dinsm-pos-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/dinsm-pos-size.mir
+++ test/CodeGen/Mips/instverify/dinsm-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position + Size is out of range!
Index: test/CodeGen/Mips/instverify/dinsm-pos.mir
===================================================================
--- test/CodeGen/Mips/instverify/dinsm-pos.mir
+++ test/CodeGen/Mips/instverify/dinsm-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position operand is out of range!
Index: test/CodeGen/Mips/instverify/dinsm-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/dinsm-size.mir
+++ test/CodeGen/Mips/instverify/dinsm-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Size operand is out of range!
Index: test/CodeGen/Mips/instverify/dinsu-pos-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/dinsu-pos-size.mir
+++ test/CodeGen/Mips/instverify/dinsu-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position + Size is out of range!
Index: test/CodeGen/Mips/instverify/dinsu-pos.mir
===================================================================
--- test/CodeGen/Mips/instverify/dinsu-pos.mir
+++ test/CodeGen/Mips/instverify/dinsu-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position operand is out of range!
Index: test/CodeGen/Mips/instverify/dinsu-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/dinsu-size.mir
+++ test/CodeGen/Mips/instverify/dinsu-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Size operand is out of range!
Index: test/CodeGen/Mips/instverify/ext-pos-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/ext-pos-size.mir
+++ test/CodeGen/Mips/instverify/ext-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position + Size is out of range!
Index: test/CodeGen/Mips/instverify/ext-pos.mir
===================================================================
--- test/CodeGen/Mips/instverify/ext-pos.mir
+++ test/CodeGen/Mips/instverify/ext-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position operand is out of range!
Index: test/CodeGen/Mips/instverify/ext-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/ext-size.mir
+++ test/CodeGen/Mips/instverify/ext-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Size operand is out of range!
Index: test/CodeGen/Mips/instverify/ins-pos-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/ins-pos-size.mir
+++ test/CodeGen/Mips/instverify/ins-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position + Size is out of range!
Index: test/CodeGen/Mips/instverify/ins-pos.mir
===================================================================
--- test/CodeGen/Mips/instverify/ins-pos.mir
+++ test/CodeGen/Mips/instverify/ins-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Position operand is out of range!
Index: test/CodeGen/Mips/instverify/ins-size.mir
===================================================================
--- test/CodeGen/Mips/instverify/ins-size.mir
+++ test/CodeGen/Mips/instverify/ins-size.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
+# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
 # RUN:         -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 # CHECK: Size operand is out of range!
Index: test/CodeGen/Mips/micromips-eva.mir
===================================================================
--- test/CodeGen/Mips/micromips-eva.mir
+++ test/CodeGen/Mips/micromips-eva.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \
+# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
 # RUN:     -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
 
 --- |
Index: test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll
===================================================================
--- test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll
+++ test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips -stop-after=expand-isel-pseudos < %s | FileCheck %s
+; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips -stop-after=finalize-isel < %s | FileCheck %s
 
 ; CHECK: JAL_MM
 ; CHECK-NOT: JALR16_MM
Index: test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
===================================================================
--- test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
+++ test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
@@ -1,5 +1,5 @@
-# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \
-# RUN:     -stop-after=expand-isel-pseudos -relocation-model=pic -mxgot \
+# RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
+# RUN:     -stop-after=finalize-isel -relocation-model=pic -mxgot \
 # RUN:     -o /dev/null %s
 
 # A simple test to show that we can parse the target specific flags: gpoff-hi,
Index: test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
===================================================================
--- test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
+++ test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
@@ -1,5 +1,5 @@
-# RUN: llc -march=mips -start-before=expand-isel-pseudos \
-# RUN:     -stop-after=expand-isel-pseudos -relocation-model=pic \
+# RUN: llc -march=mips -start-before=finalize-isel \
+# RUN:     -stop-after=finalize-isel -relocation-model=pic \
 # RUN:     -o /dev/null %s
 
 # A simple test to show that we can parse the target specific flags: got-call,
Index: test/CodeGen/Mips/mirparser/target-flags-pic.mir
===================================================================
--- test/CodeGen/Mips/mirparser/target-flags-pic.mir
+++ test/CodeGen/Mips/mirparser/target-flags-pic.mir
@@ -1,5 +1,5 @@
-# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \
-# RUN:     -stop-after=expand-isel-pseudos -relocation-model=pic \
+# RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
+# RUN:     -stop-after=finalize-isel -relocation-model=pic \
 # RUN:     -o /dev/null %s
 
 # A simple test to show that we can parse the target specific flags: gpoff-hi,
Index: test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
===================================================================
--- test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
+++ test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
@@ -1,5 +1,5 @@
-# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \
-# RUN:     -stop-after=expand-isel-pseudos -relocation-model=static  -o /dev/null %s
+# RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
+# RUN:     -stop-after=finalize-isel -relocation-model=static  -o /dev/null %s
 
 # A simple test to show that we can parse the target specific flags: highest,
 # higher, hi, lo, tprel-lo, tprel-hi, gpoff-hi, gpoff-lo, gottprel.
Index: test/CodeGen/Mips/unaligned-memops-mapping.mir
===================================================================
--- test/CodeGen/Mips/unaligned-memops-mapping.mir
+++ test/CodeGen/Mips/unaligned-memops-mapping.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \
+# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
 # RUN:     -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
 
 # Test that MIPS unaligned load/store instructions can be mapped to their
Index: test/CodeGen/Mips/unaligned-memops.ll
===================================================================
--- test/CodeGen/Mips/unaligned-memops.ll
+++ test/CodeGen/Mips/unaligned-memops.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MIPS
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MICROMIPS
+; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MIPS
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MICROMIPS
 
 ; Test that the correct ISA version of the unaligned memory operations is
 ; selected up front.
Index: test/CodeGen/PowerPC/debuginfo-split-int.ll
===================================================================
--- test/CodeGen/PowerPC/debuginfo-split-int.ll
+++ test/CodeGen/PowerPC/debuginfo-split-int.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -stop-before=expand-isel-pseudos -o - | FileCheck %s
+; RUN: llc < %s -stop-before=finalize-isel -o - | FileCheck %s
 
 source_filename = "foo.c"
 target datalayout = "E-m:e-p:32:32-i64:64-n32"
Index: test/CodeGen/SystemZ/cc-liveness.ll
===================================================================
--- test/CodeGen/SystemZ/cc-liveness.ll
+++ test/CodeGen/SystemZ/cc-liveness.ll
@@ -2,7 +2,7 @@
 ; not be placed betwen two compare and load-on-condition instructions.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -pre-RA-sched=list-ilp \
-; RUN:   -print-after=expand-isel-pseudos 2>&1 | FileCheck %s
+; RUN:   -print-after=finalize-isel 2>&1 | FileCheck %s
 ;
 ; CHECK-LABEL: bb.0.bb:
 ; CHECK: CLI
Index: test/CodeGen/SystemZ/debuginstr-02.mir
===================================================================
--- test/CodeGen/SystemZ/debuginstr-02.mir
+++ test/CodeGen/SystemZ/debuginstr-02.mir
@@ -2,7 +2,7 @@
 # the presence of DEBUG_VALUE machine instructions.
 #
 # RUN: llc %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \
-# RUN:   -start-before=expand-isel-pseudos -o - 2>&1 | FileCheck %s
+# RUN:   -start-before=finalize-isel -o - 2>&1 | FileCheck %s
 #
 # CHECK-LABEL: %bb.1:
 # CHECK:       ldr
Index: test/CodeGen/X86/MachineBranchProb.ll
===================================================================
--- test/CodeGen/X86/MachineBranchProb.ll
+++ test/CodeGen/X86/MachineBranchProb.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -print-after=finalize-isel -o /dev/null 2>&1 | FileCheck %s
 
 ;; Make sure a transformation in SelectionDAGBuilder that converts "or + br" to
 ;; two branches correctly updates the branch probability.
Index: test/CodeGen/X86/O0-pipeline.ll
===================================================================
--- test/CodeGen/X86/O0-pipeline.ll
+++ test/CodeGen/X86/O0-pipeline.ll
@@ -38,7 +38,7 @@
 ; CHECK-NEXT:       Module Verifier
 ; CHECK-NEXT:       X86 DAG->DAG Instruction Selection
 ; CHECK-NEXT:       X86 PIC Global Base Reg Initialization
-; CHECK-NEXT:       Expand ISel Pseudo-instructions
+; CHECK-NEXT:       Finalize ISel and expand pseudo-instructions
 ; CHECK-NEXT:       Local Stack Slot Allocation
 ; CHECK-NEXT:       X86 speculative load hardening
 ; CHECK-NEXT:       MachineDominator Tree Construction
Index: test/CodeGen/X86/O3-pipeline.ll
===================================================================
--- test/CodeGen/X86/O3-pipeline.ll
+++ test/CodeGen/X86/O3-pipeline.ll
@@ -67,7 +67,7 @@
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       Local Dynamic TLS Access Clean-up
 ; CHECK-NEXT:       X86 PIC Global Base Reg Initialization
-; CHECK-NEXT:       Expand ISel Pseudo-instructions
+; CHECK-NEXT:        Finalize ISel and expand pseudo-instructions
 ; CHECK-NEXT:       X86 Domain Reassignment Pass
 ; CHECK-NEXT:       Early Tail Duplication
 ; CHECK-NEXT:       Optimize machine instruction PHIs
Index: test/CodeGen/X86/catchpad-weight.ll
===================================================================
--- test/CodeGen/X86/catchpad-weight.ll
+++ test/CodeGen/X86/catchpad-weight.ll
@@ -1,4 +1,4 @@
-; RUN: llc -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s
+; RUN: llc -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s
 
 ; Check if the edge weight to the catchpad is calculated correctly.
 
Index: test/CodeGen/X86/fast-isel-fneg-kill.ll
===================================================================
--- test/CodeGen/X86/fast-isel-fneg-kill.ll
+++ test/CodeGen/X86/fast-isel-fneg-kill.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 -stop-after=expand-isel-pseudos | FileCheck %s
+; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 -stop-after=finalize-isel | FileCheck %s
 
 ; Make sure we output the right kill flag for the xor conversion.
 
Index: test/CodeGen/X86/fixed-stack-di-mir.ll
===================================================================
--- test/CodeGen/X86/fixed-stack-di-mir.ll
+++ test/CodeGen/X86/fixed-stack-di-mir.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-apple-unknown -stop-before=expand-isel-pseudos %s -o - -simplify-mir | FileCheck %s
+; RUN: llc -mtriple=x86_64-apple-unknown -stop-before=finalize-isel %s -o - -simplify-mir | FileCheck %s
 ; The byval argument of the function will be allocated a fixed stack slot. Test
 ; that we serialize the fixed slot correctly.
 
Index: test/CodeGen/X86/i16lshr8pat.ll
===================================================================
--- test/CodeGen/X86/i16lshr8pat.ll
+++ test/CodeGen/X86/i16lshr8pat.ll
@@ -1,4 +1,4 @@
-; RUN: llc -stop-after expand-isel-pseudos < %s 2>&1 | FileCheck %s
+; RUN: llc -stop-after finalize-isel < %s 2>&1 | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
 target triple = "i386-unknown-linux-gnu"
Index: test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
===================================================================
--- test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
+++ test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=expand-isel-pseudos | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=finalize-isel | FileCheck %s
 
 ; CHECK: %[[REG1:.*]]:vr512_0_15 = COPY %1
 ; CHECK: %[[REG2:.*]]:vr512_0_15 = COPY %2
Index: test/CodeGen/X86/inline-asm-default-clobbers.ll
===================================================================
--- test/CodeGen/X86/inline-asm-default-clobbers.ll
+++ test/CodeGen/X86/inline-asm-default-clobbers.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i686 -stop-after=expand-isel-pseudos | FileCheck %s
+; RUN: llc < %s -mtriple=i686 -stop-after=finalize-isel | FileCheck %s
 
 ; CHECK: INLINEASM &"", 1, 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
 define void @foo() {
Index: test/CodeGen/X86/pr39896.ll
===================================================================
--- test/CodeGen/X86/pr39896.ll
+++ test/CodeGen/X86/pr39896.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -start-after=codegenprepare -stop-after=expand-isel-pseudos -o - | FileCheck %s
+; RUN: llc %s -start-after=codegenprepare -stop-after=finalize-isel -o - | FileCheck %s
 
 ; PR39896: When code such as %conv below is dropped by SelectionDAG for having
 ; no users, don't just drop the dbg.value record associated with it. Instead,
Index: test/CodeGen/X86/sjlj-shadow-stack-liveness.mir
===================================================================
--- test/CodeGen/X86/sjlj-shadow-stack-liveness.mir
+++ test/CodeGen/X86/sjlj-shadow-stack-liveness.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=x86_64-- -run-pass=expand-isel-pseudos -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64-- -run-pass=finalize-isel -verify-machineinstrs -o - %s | FileCheck %s
 # Check that we're not copying the kill flags with the operands from the pseudo
 # instruction.
 --- |
Index: test/CodeGen/X86/sqrt-fastmath-mir.ll
===================================================================
--- test/CodeGen/X86/sqrt-fastmath-mir.ll
+++ test/CodeGen/X86/sqrt-fastmath-mir.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=expand-isel-pseudos 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=finalize-isel 2>&1 | FileCheck %s
 
 declare float @llvm.sqrt.f32(float) #0
 
Index: test/CodeGen/X86/stack-protector-weight.ll
===================================================================
--- test/CodeGen/X86/stack-protector-weight.ll
+++ test/CodeGen/X86/stack-protector-weight.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-SELDAG
-; RUN: llc -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-IR
-; RUN: llc -mtriple=i386-pc-windows-msvc -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-SELDAG
-; RUN: llc -mtriple=i386-pc-windows-msvc -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-IR
+; RUN: llc -mtriple=x86_64-apple-darwin -print-after=finalize-isel -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-SELDAG
+; RUN: llc -mtriple=x86_64-apple-darwin -print-after=finalize-isel -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-IR
+; RUN: llc -mtriple=i386-pc-windows-msvc -print-after=finalize-isel -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-SELDAG
+; RUN: llc -mtriple=i386-pc-windows-msvc -print-after=finalize-isel -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-IR
 
 ; DARWIN-SELDAG: # Machine code for function test_branch_weights:
 ; DARWIN-SELDAG: successors: %bb.[[SUCCESS:[0-9]+]](0x7ffff800), %bb.[[FAILURE:[0-9]+]]
Index: test/CodeGen/X86/switch-edge-weight.ll
===================================================================
--- test/CodeGen/X86/switch-edge-weight.ll
+++ test/CodeGen/X86/switch-edge-weight.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-- -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s
+; RUN: llc -mtriple=x86_64-- -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s
 
 declare void @foo(i32)
 
@@ -276,6 +276,6 @@
 ; CHECK: successors: %bb.8(0x20000001), %bb.9(0x5fffffff)
 }
 
-!1 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} 
-!2 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} 
-!3 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} 
+!1 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}
+!2 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}
+!3 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10}
Index: test/CodeGen/X86/switch-jump-table.ll
===================================================================
--- test/CodeGen/X86/switch-jump-table.ll
+++ test/CodeGen/X86/switch-jump-table.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=i686-pc-gnu-linux < %s | FileCheck %s
-; RUN: llc -mtriple=i686-pc-gnu-linux -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-JT-PROB
+; RUN: llc -mtriple=i686-pc-gnu-linux -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-JT-PROB
 
 
 ; An unreachable default destination is ignored and no compare and branch
Index: test/CodeGen/X86/switch-lower-peel-top-case.ll
===================================================================
--- test/CodeGen/X86/switch-lower-peel-top-case.ll
+++ test/CodeGen/X86/switch-lower-peel-top-case.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-linux-gnu -stop-after=expand-isel-pseudos < %s  | FileCheck %s
+; RUN: llc -mtriple=x86_64-linux-gnu -stop-after=finalize-isel < %s  | FileCheck %s
 
 define i32 @foo(i32 %n) !prof !1 {
 entry:
Index: test/CodeGen/X86/vecloadextract.ll
===================================================================
--- test/CodeGen/X86/vecloadextract.ll
+++ test/CodeGen/X86/vecloadextract.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-;RUN: llc < %s -mtriple=i686 -mattr=sse4.1 -stop-after=expand-isel-pseudos 2>&1 | FileCheck %s
+;RUN: llc < %s -mtriple=i686 -mattr=sse4.1 -stop-after=finalize-isel 2>&1 | FileCheck %s
 
 ; This test makes sure we discard pointer info when we combine a vector load
 ; and a variable extractelement into a scalar load using an index. There's also
Index: test/CodeGen/X86/vmaskmov-offset.ll
===================================================================
--- test/CodeGen/X86/vmaskmov-offset.ll
+++ test/CodeGen/X86/vmaskmov-offset.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 -stop-after expand-isel-pseudos -o - %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 -stop-after finalize-isel -o - %s | FileCheck %s
 
 declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
 declare <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
Index: test/CodeGen/X86/xor-combine-debugloc.ll
===================================================================
--- test/CodeGen/X86/xor-combine-debugloc.ll
+++ test/CodeGen/X86/xor-combine-debugloc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -stop-after=expand-isel-pseudos < %s | FileCheck %s
+; RUN: llc -stop-after=finalize-isel < %s | FileCheck %s
 ;
 ; Make sure that when the entry block of IR below is lowered, an instruction
 ; that implictly defines $eflags has a same debug location with the icmp
Index: test/DebugInfo/ARM/float-stack-arg.ll
===================================================================
--- test/DebugInfo/ARM/float-stack-arg.ll
+++ test/DebugInfo/ARM/float-stack-arg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=armv4t-unknown-unknown -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s
+; RUN: llc -mtriple=armv4t-unknown-unknown -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s
 
 ; Verify that a stack-referencing DBG_VALUE is emitted for p5 at the start of
 ; the function.
Index: test/DebugInfo/Generic/linear-dbg-value.ll
===================================================================
--- test/DebugInfo/Generic/linear-dbg-value.ll
+++ test/DebugInfo/Generic/linear-dbg-value.ll
@@ -1,5 +1,5 @@
 ; FIXME: Fix machine verifier issues and remove -verify-machineinstrs=0. PR39452.
-; RUN: llc -stop-before=expand-isel-pseudos -pre-RA-sched=linearize -verify-machineinstrs=0 < %s | FileCheck %s
+; RUN: llc -stop-before=finalize-isel -pre-RA-sched=linearize -verify-machineinstrs=0 < %s | FileCheck %s
 source_filename = "linear-dbg-value.ll"
 
 ; Function Attrs: nounwind readonly uwtable
Index: test/DebugInfo/X86/dbg-value-arg-movement.ll
===================================================================
--- test/DebugInfo/X86/dbg-value-arg-movement.ll
+++ test/DebugInfo/X86/dbg-value-arg-movement.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before=expand-isel-pseudos %s -o - | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before=finalize-isel %s -o - | FileCheck %s
 
 ; Test the movement of dbg.values of arguments. SelectionDAG tries to be
 ; helpful and places DBG_VALUEs of Arguments at the start of functions.
Index: test/DebugInfo/X86/dbg-value-frame-index-2.ll
===================================================================
--- test/DebugInfo/X86/dbg-value-frame-index-2.ll
+++ test/DebugInfo/X86/dbg-value-frame-index-2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -start-after=codegenprepare -stop-before=expand-isel-pseudos < %s -o - | FileCheck %s
+; RUN: llc -start-after=codegenprepare -stop-before=finalize-isel < %s -o - | FileCheck %s
 
 ; Test that stack frame dbg.values are lowered to DBG_VALUEs, in blocks that
 ; are local to the alloca, and elsewhere. Differs from dbg-value-frame-index.ll
Index: test/DebugInfo/X86/dbg-value-funcarg.ll
===================================================================
--- test/DebugInfo/X86/dbg-value-funcarg.ll
+++ test/DebugInfo/X86/dbg-value-funcarg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s
 
 ; Input to this test looked like this and was compiled using: clang -g -O1 -mllvm -stop-after=codegenprepare -S
 ;
Index: test/DebugInfo/X86/dbg-value-funcarg2.ll
===================================================================
--- test/DebugInfo/X86/dbg-value-funcarg2.ll
+++ test/DebugInfo/X86/dbg-value-funcarg2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s
 
 ; Test case was generated from the following C code,
 ; using: clang -g -O1 -S -emit-llvm s.c -o s.ll
Index: test/DebugInfo/X86/pr40427.ll
===================================================================
--- test/DebugInfo/X86/pr40427.ll
+++ test/DebugInfo/X86/pr40427.ll
@@ -1,4 +1,4 @@
-; RUN: llc -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - < %s | FileCheck %s
+; RUN: llc -start-after=codegenprepare -stop-before=finalize-isel -o - < %s | FileCheck %s
 ; Test for correct placement of DBG_VALUE, which in PR40427 is placed before
 ; the load instruction it refers to. The circumstance replicated here is where
 ; two instructions in a row, trunc and add, begin with no-op Copy{To,From}Reg
Index: test/DebugInfo/X86/safestack-byval.ll
===================================================================
--- test/DebugInfo/X86/safestack-byval.ll
+++ test/DebugInfo/X86/safestack-byval.ll
@@ -1,7 +1,7 @@
 ; Test dwarf codegen for DILocalVariable of a byval function argument that
 ; points to neither an argument nor an alloca. This kind of IR is generated by
 ; SafeStack for unsafe byval arguments.
-; RUN: llc -mtriple=x86_64-unknown-unknown -stop-after expand-isel-pseudos %s -o - | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -stop-after finalize-isel %s -o - | FileCheck %s
 
 ; This was built by compiling the following source with SafeStack and
 ; simplifying the result a little.
Index: test/DebugInfo/X86/sdag-dangling-dbgvalue.ll
===================================================================
--- test/DebugInfo/X86/sdag-dangling-dbgvalue.ll
+++ test/DebugInfo/X86/sdag-dangling-dbgvalue.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -stop-before expand-isel-pseudos -o - | FileCheck %s
+; RUN: llc %s -stop-before finalize-isel -o - | FileCheck %s
 
 ;--------------------------------------------------------------------
 ; This test case is basically generated from the following C code.
Index: test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll
===================================================================
--- test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll
+++ test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s
+; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
 
 ; This test case was generated from the following debug.c program,
 ; using: clang debug.c -g -O1 -S -o dbg_value_phi_isel1.ll -emit-llvm
Index: test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll
===================================================================
--- test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll
+++ test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s
+; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
 
 ; This test case is a modified version of dbg_value_phi_isel1.ll
 ; where the llvm.dbg.value nodes in for.body has been moved.
Index: test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll
===================================================================
--- test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll
+++ test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll
@@ -1,4 +1,4 @@
-; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s
+; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
 
 ; This test case was generated from the following phi-split.c program,
 ; using: clang phi-split.c -g -O1 -S -o - --target=i386 -emit-llvm
Index: test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll
===================================================================
--- test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll
+++ test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll
@@ -1,4 +1,4 @@
-; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s
+; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
 
 ; This is a reproducer based on the test case from PR37321.
 
Index: test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll
===================================================================
--- test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll
+++ test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s
+; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s
 
 ; Test that dbg.values of an SSA variable that's not used in a basic block,
 ; is converted to a DBG_VALUE in that same basic block. We know that %1 is
Index: test/DebugInfo/X86/sdag-ir-salvage.ll
===================================================================
--- test/DebugInfo/X86/sdag-ir-salvage.ll
+++ test/DebugInfo/X86/sdag-ir-salvage.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before expand-isel-pseudos %s -o -  | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before finalize-isel %s -o -  | FileCheck %s
 
 ; Test that the dbg.value for %baz, which doesn't exist in the 'next' bb,
 ; can be salvaged back to the underlying argument vreg.