Index: include/llvm/CodeGen/MIRYamlMapping.h =================================================================== --- include/llvm/CodeGen/MIRYamlMapping.h +++ include/llvm/CodeGen/MIRYamlMapping.h @@ -72,6 +72,9 @@ struct BlockStringValue { StringValue Value; + bool operator==(const BlockStringValue &Other) const { + return Value == Other.Value; + } }; template <> struct BlockScalarTraits { @@ -146,6 +149,10 @@ StringValue Class; StringValue PreferredRegister; // TODO: Serialize the target specific register hints. + bool operator==(const VirtualRegisterDefinition &Other) const { + return ID == Other.ID && Class == Other.Class && + PreferredRegister == Other.PreferredRegister; + } }; template <> struct MappingTraits { @@ -162,6 +169,10 @@ struct MachineFunctionLiveIn { StringValue Register; StringValue VirtualRegister; + bool operator==(const MachineFunctionLiveIn &Other) const { + return Register == Other.Register && + VirtualRegister == Other.VirtualRegister; + } }; template <> struct MappingTraits { @@ -196,6 +207,14 @@ StringValue DebugVar; StringValue DebugExpr; StringValue DebugLoc; + bool operator==(const MachineStackObject &Other) const { + return ID == Other.ID && Name == Other.Name && Type == Other.Type && + Offset == Other.Offset && Size == Other.Size && + Alignment == Other.Alignment && + CalleeSavedRegister == Other.CalleeSavedRegister && + LocalOffset == Other.LocalOffset && DebugVar == Other.DebugVar && + DebugExpr == Other.DebugExpr && DebugLoc == Other.DebugLoc; + } }; template <> struct ScalarEnumerationTraits { @@ -214,13 +233,13 @@ YamlIO.mapOptional( "type", Object.Type, MachineStackObject::DefaultType); // Don't print the default type. - YamlIO.mapOptional("offset", Object.Offset); + YamlIO.mapOptional("offset", Object.Offset, (int64_t)0); if (Object.Type != MachineStackObject::VariableSized) YamlIO.mapRequired("size", Object.Size); - YamlIO.mapOptional("alignment", Object.Alignment); + YamlIO.mapOptional("alignment", Object.Alignment, (unsigned)0); YamlIO.mapOptional("callee-saved-register", Object.CalleeSavedRegister, StringValue()); // Don't print it out when it's empty. - YamlIO.mapOptional("local-offset", Object.LocalOffset); + YamlIO.mapOptional("local-offset", Object.LocalOffset, Optional()); YamlIO.mapOptional("di-variable", Object.DebugVar, StringValue()); // Don't print it out when it's empty. YamlIO.mapOptional("di-expression", Object.DebugExpr, @@ -244,6 +263,12 @@ bool IsImmutable = false; bool IsAliased = false; StringValue CalleeSavedRegister; + bool operator==(const FixedMachineStackObject &Other) const { + return ID == Other.ID && Type == Other.Type && Offset == Other.Offset && + Size == Other.Size && Alignment == Other.Alignment && + IsImmutable == Other.IsImmutable && IsAliased == Other.IsAliased && + CalleeSavedRegister == Other.CalleeSavedRegister; + } }; template <> @@ -261,12 +286,12 @@ YamlIO.mapOptional( "type", Object.Type, FixedMachineStackObject::DefaultType); // Don't print the default type. - YamlIO.mapOptional("offset", Object.Offset); - YamlIO.mapOptional("size", Object.Size); - YamlIO.mapOptional("alignment", Object.Alignment); + YamlIO.mapOptional("offset", Object.Offset, (int64_t)0); + YamlIO.mapOptional("size", Object.Size, (uint64_t)0); + YamlIO.mapOptional("alignment", Object.Alignment, (unsigned)0); if (Object.Type != FixedMachineStackObject::SpillSlot) { - YamlIO.mapOptional("isImmutable", Object.IsImmutable); - YamlIO.mapOptional("isAliased", Object.IsAliased); + YamlIO.mapOptional("isImmutable", Object.IsImmutable, false); + YamlIO.mapOptional("isAliased", Object.IsAliased, false); } YamlIO.mapOptional("callee-saved-register", Object.CalleeSavedRegister, StringValue()); // Don't print it out when it's empty. @@ -279,13 +304,17 @@ UnsignedValue ID; StringValue Value; unsigned Alignment = 0; + bool operator==(const MachineConstantPoolValue &Other) const { + return ID == Other.ID && Value == Other.Value && + Alignment == Other.Alignment; + } }; template <> struct MappingTraits { static void mapping(IO &YamlIO, MachineConstantPoolValue &Constant) { YamlIO.mapRequired("id", Constant.ID); - YamlIO.mapOptional("value", Constant.Value); - YamlIO.mapOptional("alignment", Constant.Alignment); + YamlIO.mapOptional("value", Constant.Value, StringValue()); + YamlIO.mapOptional("alignment", Constant.Alignment, (unsigned)0); } }; @@ -293,16 +322,22 @@ struct Entry { UnsignedValue ID; std::vector Blocks; + bool operator==(const Entry &Other) const { + return ID == Other.ID && Blocks == Other.Blocks; + } }; MachineJumpTableInfo::JTEntryKind Kind = MachineJumpTableInfo::EK_Custom32; std::vector Entries; + bool operator==(const MachineJumpTable &Other) const { + return Kind == Other.Kind && Entries == Other.Entries; + } }; template <> struct MappingTraits { static void mapping(IO &YamlIO, MachineJumpTable::Entry &Entry) { YamlIO.mapRequired("id", Entry.ID); - YamlIO.mapOptional("blocks", Entry.Blocks); + YamlIO.mapOptional("blocks", Entry.Blocks, std::vector()); } }; @@ -322,7 +357,8 @@ template <> struct MappingTraits { static void mapping(IO &YamlIO, MachineJumpTable &JT) { YamlIO.mapRequired("kind", JT.Kind); - YamlIO.mapOptional("entries", JT.Entries); + YamlIO.mapOptional("entries", JT.Entries, + std::vector()); } }; @@ -351,25 +387,43 @@ bool HasMustTailInVarArgFunc = false; StringValue SavePoint; StringValue RestorePoint; + bool operator==(const MachineFrameInfo &Other) const { + return IsFrameAddressTaken == Other.IsFrameAddressTaken && + IsReturnAddressTaken == Other.IsReturnAddressTaken && + HasStackMap == Other.HasStackMap && + HasPatchPoint == Other.HasPatchPoint && + StackSize == Other.StackSize && + OffsetAdjustment == Other.OffsetAdjustment && + MaxAlignment == Other.MaxAlignment && + AdjustsStack == Other.AdjustsStack && HasCalls == Other.HasCalls && + StackProtector == Other.StackProtector && + MaxCallFrameSize == Other.MaxCallFrameSize && + HasOpaqueSPAdjustment == Other.HasOpaqueSPAdjustment && + HasVAStart == Other.HasVAStart && + HasMustTailInVarArgFunc == Other.HasMustTailInVarArgFunc && + SavePoint == Other.SavePoint && RestorePoint == Other.RestorePoint; + } }; template <> struct MappingTraits { static void mapping(IO &YamlIO, MachineFrameInfo &MFI) { - YamlIO.mapOptional("isFrameAddressTaken", MFI.IsFrameAddressTaken); - YamlIO.mapOptional("isReturnAddressTaken", MFI.IsReturnAddressTaken); - YamlIO.mapOptional("hasStackMap", MFI.HasStackMap); - YamlIO.mapOptional("hasPatchPoint", MFI.HasPatchPoint); - YamlIO.mapOptional("stackSize", MFI.StackSize); - YamlIO.mapOptional("offsetAdjustment", MFI.OffsetAdjustment); - YamlIO.mapOptional("maxAlignment", MFI.MaxAlignment); - YamlIO.mapOptional("adjustsStack", MFI.AdjustsStack); - YamlIO.mapOptional("hasCalls", MFI.HasCalls); + YamlIO.mapOptional("isFrameAddressTaken", MFI.IsFrameAddressTaken, false); + YamlIO.mapOptional("isReturnAddressTaken", MFI.IsReturnAddressTaken, false); + YamlIO.mapOptional("hasStackMap", MFI.HasStackMap, false); + YamlIO.mapOptional("hasPatchPoint", MFI.HasPatchPoint, false); + YamlIO.mapOptional("stackSize", MFI.StackSize, (uint64_t)0); + YamlIO.mapOptional("offsetAdjustment", MFI.OffsetAdjustment, (int)0); + YamlIO.mapOptional("maxAlignment", MFI.MaxAlignment, (unsigned)0); + YamlIO.mapOptional("adjustsStack", MFI.AdjustsStack, false); + YamlIO.mapOptional("hasCalls", MFI.HasCalls, false); YamlIO.mapOptional("stackProtector", MFI.StackProtector, StringValue()); // Don't print it out when it's empty. - YamlIO.mapOptional("maxCallFrameSize", MFI.MaxCallFrameSize, ~0u); - YamlIO.mapOptional("hasOpaqueSPAdjustment", MFI.HasOpaqueSPAdjustment); - YamlIO.mapOptional("hasVAStart", MFI.HasVAStart); - YamlIO.mapOptional("hasMustTailInVarArgFunc", MFI.HasMustTailInVarArgFunc); + YamlIO.mapOptional("maxCallFrameSize", MFI.MaxCallFrameSize, (unsigned)~0); + YamlIO.mapOptional("hasOpaqueSPAdjustment", MFI.HasOpaqueSPAdjustment, + false); + YamlIO.mapOptional("hasVAStart", MFI.HasVAStart, false); + YamlIO.mapOptional("hasMustTailInVarArgFunc", MFI.HasMustTailInVarArgFunc, + false); YamlIO.mapOptional("savePoint", MFI.SavePoint, StringValue()); // Don't print it out when it's empty. YamlIO.mapOptional("restorePoint", MFI.RestorePoint, @@ -404,23 +458,29 @@ template <> struct MappingTraits { static void mapping(IO &YamlIO, MachineFunction &MF) { YamlIO.mapRequired("name", MF.Name); - YamlIO.mapOptional("alignment", MF.Alignment); - YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice); + YamlIO.mapOptional("alignment", MF.Alignment, (unsigned)0); + YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice, false); YamlIO.mapOptional("noVRegs", MF.NoVRegs); - YamlIO.mapOptional("legalized", MF.Legalized); - YamlIO.mapOptional("regBankSelected", MF.RegBankSelected); - YamlIO.mapOptional("selected", MF.Selected); - YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness); - YamlIO.mapOptional("registers", MF.VirtualRegisters); - YamlIO.mapOptional("liveins", MF.LiveIns); - YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters); - YamlIO.mapOptional("frameInfo", MF.FrameInfo); - YamlIO.mapOptional("fixedStack", MF.FixedStackObjects); - YamlIO.mapOptional("stack", MF.StackObjects); - YamlIO.mapOptional("constants", MF.Constants); + YamlIO.mapOptional("legalized", MF.Legalized, false); + YamlIO.mapOptional("regBankSelected", MF.RegBankSelected, false); + YamlIO.mapOptional("selected", MF.Selected, false); + YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness, false); + YamlIO.mapOptional("registers", MF.VirtualRegisters, + std::vector()); + YamlIO.mapOptional("liveins", MF.LiveIns, + std::vector()); + YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters, + Optional>()); + YamlIO.mapOptional("frameInfo", MF.FrameInfo, MachineFrameInfo()); + YamlIO.mapOptional("fixedStack", MF.FixedStackObjects, + std::vector()); + YamlIO.mapOptional("stack", MF.StackObjects, + std::vector()); + YamlIO.mapOptional("constants", MF.Constants, + std::vector()); if (!YamlIO.outputting() || !MF.JumpTableInfo.Entries.empty()) - YamlIO.mapOptional("jumpTable", MF.JumpTableInfo); - YamlIO.mapOptional("body", MF.Body); + YamlIO.mapOptional("jumpTable", MF.JumpTableInfo, MachineJumpTable()); + YamlIO.mapOptional("body", MF.Body, BlockStringValue()); } }; Index: lib/CodeGen/MIRPrinter.cpp =================================================================== --- lib/CodeGen/MIRPrinter.cpp +++ lib/CodeGen/MIRPrinter.cpp @@ -212,6 +212,8 @@ } StrOS.flush(); yaml::Output Out(OS); + if (!SimplifyMIR) + Out.setWriteDefaultValues(true); Out << YamlMF; } Index: test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll =================================================================== --- test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll +++ test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll @@ -1,10 +1,10 @@ -; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios %s -stop-after=irtranslator -o - -global-isel | FileCheck %s +; RUN: llc -simplify-mir -verify-machineinstrs -mtriple=aarch64-apple-ios %s -stop-after=irtranslator -o - -global-isel | FileCheck %s ; CHECK: name: test_stack_guard ; CHECK: stack: -; CHECK: - { id: 0, name: StackGuardSlot, offset: 0, size: 8, alignment: 8 } +; CHECK: - { id: 0, name: StackGuardSlot, size: 8, alignment: 8 } ; CHECK-NOT: id: 1 ; CHECK: [[GUARD_SLOT:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.StackGuardSlot Index: test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll =================================================================== --- test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -31,10 +31,13 @@ ; Tests for alloca ; CHECK-LABEL: name: allocai64 ; CHECK: stack: -; CHECK-NEXT: - { id: 0, name: ptr1, offset: 0, size: 8, alignment: 8 } -; CHECK-NEXT: - { id: 1, name: ptr2, offset: 0, size: 8, alignment: 1 } -; CHECK-NEXT: - { id: 2, name: ptr3, offset: 0, size: 128, alignment: 8 } -; CHECK-NEXT: - { id: 3, name: ptr4, offset: 0, size: 1, alignment: 8 } +; CHECK-NEXT: - { id: 0, name: ptr1, type: default, offset: 0, size: 8, alignment: 8, +; CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } +; CHECK-NEXT: - { id: 1, name: ptr2, type: default, offset: 0, size: 8, alignment: 1, +; CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } +; CHECK-NEXT: - { id: 2, name: ptr3, type: default, offset: 0, size: 128, alignment: 8, +; CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' } +; CHECK-NEXT: - { id: 3, name: ptr4, type: default, offset: 0, size: 1, alignment: 8, ; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.0.ptr1 ; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.1.ptr2 ; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.2.ptr3 Index: test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir +++ test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir @@ -1,5 +1,5 @@ -# RUN: llc -O0 -run-pass=regbankselect -global-isel %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=FAST -# RUN: llc -O0 -run-pass=regbankselect -global-isel %s -regbankselect-greedy -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY +# RUN: llc -simplify-mir -O0 -run-pass=regbankselect -global-isel %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=FAST +# RUN: llc -simplify-mir -O0 -run-pass=regbankselect -global-isel %s -regbankselect-greedy -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY --- | ; ModuleID = 'generic-virtual-registers-type-error.mir' Index: test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll =================================================================== --- test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll +++ test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll @@ -1,9 +1,9 @@ -; RUN: llc -mtriple=aarch64-apple-ios -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s +; RUN: llc -simplify-mir -mtriple=aarch64-apple-ios -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s ; CHECK-LABEL: name: test_stack_slots ; CHECK: fixedStack: -; CHECK-DAG: - { id: [[STACK0:[0-9]+]], offset: 0, size: 1 +; CHECK-DAG: - { id: [[STACK0:[0-9]+]], size: 1 ; CHECK-DAG: - { id: [[STACK8:[0-9]+]], offset: 1, size: 1 ; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ; CHECK: [[LHS:%[0-9]+]](s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0) Index: test/CodeGen/AArch64/GlobalISel/call-translator.ll =================================================================== --- test/CodeGen/AArch64/GlobalISel/call-translator.ll +++ test/CodeGen/AArch64/GlobalISel/call-translator.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s +; RUN: llc -simplify-mir -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s ; CHECK-LABEL: name: test_trivial_call ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def %sp, implicit %sp @@ -165,7 +165,7 @@ ; CHECK-LABEL: name: test_stack_slots ; CHECK: fixedStack: -; CHECK-DAG: - { id: [[STACK0:[0-9]+]], offset: 0, size: 8 +; CHECK-DAG: - { id: [[STACK0:[0-9]+]], size: 8 ; CHECK-DAG: - { id: [[STACK8:[0-9]+]], offset: 8, size: 8 ; CHECK-DAG: - { id: [[STACK16:[0-9]+]], offset: 16, size: 8 ; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] @@ -208,7 +208,7 @@ ; CHECK-LABEL: name: test_mem_i1 ; CHECK: fixedStack: -; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false } +; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], size: 1, alignment: 16, isImmutable: true } ; CHECK: [[ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]] ; CHECK: {{%[0-9]+}}(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0) define void @test_mem_i1([8 x i64], i1 %in) { Index: test/CodeGen/AArch64/GlobalISel/debug-insts.ll =================================================================== --- test/CodeGen/AArch64/GlobalISel/debug-insts.ll +++ test/CodeGen/AArch64/GlobalISel/debug-insts.ll @@ -1,9 +1,9 @@ -; RUN: llc -global-isel -mtriple=aarch64 %s -stop-after=irtranslator -o - | FileCheck %s -; RUN: llc -mtriple=aarch64 -global-isel --global-isel-abort=0 -o /dev/null +; RUN: llc -simplify-mir -global-isel -mtriple=aarch64 %s -stop-after=irtranslator -o - | FileCheck %s +; RUN: llc -simplify-mir -mtriple=aarch64 -global-isel --global-isel-abort=0 -o /dev/null ; CHECK-LABEL: name: debug_declare ; CHECK: stack: -; CHECK: - { id: {{.*}}, name: in.addr, offset: {{.*}}, size: {{.*}}, alignment: {{.*}}, di-variable: '!11', +; CHECK: - { id: {{.*}}, name: in.addr, size: {{.*}}, alignment: {{.*}}, di-variable: '!11', ; CHECK-NEXT: di-expression: '!12', di-location: '!13' } ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !12, debug-location !13 define void @debug_declare(i32 %in) #0 !dbg !7 { Index: test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir +++ test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -O0 -mtriple arm64-- -run-pass=regbankselect -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir +++ test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -O0 -mtriple arm64-- -run-pass=regbankselect -global-isel %s -o - | FileCheck %s # Check the default mappings for various instructions. Index: test/CodeGen/AArch64/GlobalISel/select-binop.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-binop.mir +++ test/CodeGen/AArch64/GlobalISel/select-binop.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/select-bitcast.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-bitcast.mir +++ test/CodeGen/AArch64/GlobalISel/select-bitcast.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir +++ test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/select-int-ext.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-int-ext.mir +++ test/CodeGen/AArch64/GlobalISel/select-int-ext.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir +++ test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/select-load.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-load.mir +++ test/CodeGen/AArch64/GlobalISel/select-load.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/select-muladd.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-muladd.mir +++ test/CodeGen/AArch64/GlobalISel/select-muladd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/select-store.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-store.mir +++ test/CodeGen/AArch64/GlobalISel/select-store.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/select-trunc.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-trunc.mir +++ test/CodeGen/AArch64/GlobalISel/select-trunc.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/select-xor.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-xor.mir +++ test/CodeGen/AArch64/GlobalISel/select-xor.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s +# RUN: llc -simplify-mir -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/select.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select.mir +++ test/CodeGen/AArch64/GlobalISel/select.mir @@ -1,6 +1,6 @@ -# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=IOS -# RUN: llc -O0 -mtriple=aarch64-linux-gnu -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-DEFAULT -# RUN: llc -O0 -mtriple=aarch64-linux-gnu -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-PIC +# RUN: llc -simplify-mir -O0 -mtriple=aarch64-apple-ios -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=IOS +# RUN: llc -simplify-mir -O0 -mtriple=aarch64-linux-gnu -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-DEFAULT +# RUN: llc -simplify-mir -O0 -mtriple=aarch64-linux-gnu -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-PIC --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" Index: test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll =================================================================== --- test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll +++ test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-apple-ios -stop-after=instruction-select -global-isel -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -simplify-mir -mtriple=aarch64-apple-ios -stop-after=instruction-select -global-isel -verify-machineinstrs %s -o - | FileCheck %s define void @test_varargs_sentinel(i8* %list, i64, i64, i64, i64, i64, i64, i64, i32, ...) { Index: test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir =================================================================== --- test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir +++ test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -simplify-mir -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - | FileCheck %s # REQUIRES: global-isel Index: test/CodeGen/AMDGPU/limit-coalesce.mir =================================================================== --- test/CodeGen/AMDGPU/limit-coalesce.mir +++ test/CodeGen/AMDGPU/limit-coalesce.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s +# RUN: llc -simplify-mir -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s # Check that coalescer does not create wider register tuple than in source Index: test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir =================================================================== --- test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -simplify-mir -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_zext_s1() { ret void } define void @test_sext_s1() { ret void } @@ -802,7 +802,7 @@ - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false } - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } -# CHECK-DAG: id: [[FI1:[0-9]+]], offset: 0 +# CHECK-DAG: id: [[FI1:[0-9]+]], size: 1 # CHECK-DAG: id: [[FI32:[0-9]+]], offset: 8 body: | bb.0: Index: test/CodeGen/ARM/GlobalISel/arm-legalizer.mir =================================================================== --- test/CodeGen/ARM/GlobalISel/arm-legalizer.mir +++ test/CodeGen/ARM/GlobalISel/arm-legalizer.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple arm-- -global-isel -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -simplify-mir -mtriple arm-- -global-isel -run-pass=legalizer %s -o - | FileCheck %s --- | define void @test_sext_s8() { ret void } define void @test_zext_s16() { ret void } Index: test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir =================================================================== --- test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple arm-- -global-isel -run-pass=regbankselect %s -o - | FileCheck %s +# RUN: llc -simplify-mir -mtriple arm-- -global-isel -run-pass=regbankselect %s -o - | FileCheck %s --- | define void @test_add_s32() { ret void } define void @test_add_s16() { ret void } Index: test/CodeGen/ARM/invalidated-save-point.ll =================================================================== --- test/CodeGen/ARM/invalidated-save-point.ll +++ test/CodeGen/ARM/invalidated-save-point.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple thumbv7 -stop-after=if-converter < %s 2>&1 | FileCheck %s +; RUN: llc -simplify-mir -mtriple thumbv7 -stop-after=if-converter < %s 2>&1 | FileCheck %s ; Make sure the save point and restore point are dropped from MFI at ; this point. Notably, if it isn't is will be invalid and reference a Index: test/CodeGen/MIR/AArch64/register-operand-bank.mir =================================================================== --- test/CodeGen/MIR/AArch64/register-operand-bank.mir +++ test/CodeGen/MIR/AArch64/register-operand-bank.mir @@ -1,4 +1,4 @@ -# RUN: llc -o - %s -mtriple=aarch64-- -run-pass=none | FileCheck %s +# RUN: llc -simplify-mir -o - %s -mtriple=aarch64-- -run-pass=none | FileCheck %s # REQUIRES: global-isel # Test various aspects of register bank specification on machine operands. --- | Index: test/CodeGen/MIR/AArch64/stack-object-local-offset.mir =================================================================== --- test/CodeGen/MIR/AArch64/stack-object-local-offset.mir +++ test/CodeGen/MIR/AArch64/stack-object-local-offset.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s +# RUN: llc -simplify-mir -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s --- | @var = global i64 0 @@ -25,7 +25,7 @@ maxAlignment: 8 # CHECK-LABEL: stack_local # CHECK: stack: -# CHECK-NEXT: { id: 0, name: local_var, offset: 0, size: 8, alignment: 8, local-offset: -8 } +# CHECK-NEXT: { id: 0, name: local_var, size: 8, alignment: 8, local-offset: -8 } stack: - { id: 0,name: local_var,offset: 0,size: 8,alignment: 8, local-offset: -8 } body: | Index: test/CodeGen/MIR/Generic/frame-info.mir =================================================================== --- test/CodeGen/MIR/Generic/frame-info.mir +++ test/CodeGen/MIR/Generic/frame-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -run-pass none -o - %s | FileCheck %s +# RUN: llc -simplify-mir -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses machine frame info properties # correctly. @@ -26,19 +26,7 @@ tracksRegLiveness: true # CHECK: frameInfo: -# CHECK-NEXT: isFrameAddressTaken: false -# CHECK-NEXT: isReturnAddressTaken: false -# CHECK-NEXT: hasStackMap: false -# CHECK-NEXT: hasPatchPoint: false -# CHECK-NEXT: stackSize: 0 -# CHECK-NEXT: offsetAdjustment: 0 -# Note: max alignment can be target specific when printed. # CHECK-NEXT: maxAlignment: -# CHECK-NEXT: adjustsStack: false -# CHECK-NEXT: hasCalls: false -# CHECK-NEXT: hasOpaqueSPAdjustment: false -# CHECK-NEXT: hasVAStart: false -# CHECK-NEXT: hasMustTailInVarArgFunc: false # CHECK: body frameInfo: maxAlignment: 4 Index: test/CodeGen/MIR/X86/callee-saved-info.mir =================================================================== --- test/CodeGen/MIR/X86/callee-saved-info.mir +++ test/CodeGen/MIR/X86/callee-saved-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -simplify-mir -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses callee saved information in the # stack objects correctly. Index: test/CodeGen/MIR/X86/fixed-stack-objects.mir =================================================================== --- test/CodeGen/MIR/X86/fixed-stack-objects.mir +++ test/CodeGen/MIR/X86/fixed-stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86 -run-pass none -o - %s | FileCheck %s +# RUN: llc -simplify-mir -march=x86 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses fixed stack objects correctly. --- | @@ -20,7 +20,7 @@ stackSize: 4 maxAlignment: 4 # CHECK: fixedStack: -# CHECK-NEXT: - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false } +# CHECK-NEXT: - { id: 0, size: 4, alignment: 4, isImmutable: true } fixedStack: - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false } stack: Index: test/CodeGen/MIR/X86/generic-instr-type.mir =================================================================== --- test/CodeGen/MIR/X86/generic-instr-type.mir +++ test/CodeGen/MIR/X86/generic-instr-type.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -simplify-mir -march=x86-64 -run-pass none -o - %s | FileCheck %s # REQUIRES: global-isel # Test that the MIR parser parses types on generic instructions correctly. Index: test/CodeGen/MIR/X86/register-operand-class.mir =================================================================== --- test/CodeGen/MIR/X86/register-operand-class.mir +++ test/CodeGen/MIR/X86/register-operand-class.mir @@ -1,4 +1,4 @@ -# RUN: llc -o - %s -march=x86-64 -run-pass none | FileCheck %s +# RUN: llc -simplify-mir -o - %s -march=x86-64 -run-pass none | FileCheck %s # Test various aspects of register class specification on machine operands. --- | define void @func() { ret void } Index: test/CodeGen/MIR/X86/simple-register-allocation-hints.mir =================================================================== --- test/CodeGen/MIR/X86/simple-register-allocation-hints.mir +++ test/CodeGen/MIR/X86/simple-register-allocation-hints.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -simplify-mir -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses simple register allocation hints # correctly. Index: test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir =================================================================== --- test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir +++ test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -simplify-mir -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses fixed stack objects correctly. --- | @@ -19,7 +19,7 @@ frameInfo: maxAlignment: 4 # CHECK: fixedStack: -# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 } +# CHECK-NEXT: - { id: 0, type: spill-slot, size: 4, alignment: 4 } fixedStack: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 } stack: Index: test/CodeGen/MIR/X86/stack-object-debug-info.mir =================================================================== --- test/CodeGen/MIR/X86/stack-object-debug-info.mir +++ test/CodeGen/MIR/X86/stack-object-debug-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -simplify-mir -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the stack object's debug info # correctly. --- | @@ -51,8 +51,8 @@ maxAlignment: 16 # CHECK-LABEL: foo # CHECK: stack: -# CHECK: - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4', -# CHECK-NEXT: di-expression: '!10', di-location: '!11' } +# CHECK: - { id: 0, name: y.i, size: 256, alignment: 16, di-variable: '!4', di-expression: '!10' +# CHECK-NEXT: di-location: '!11' } stack: - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4', di-expression: '!7', di-location: '!8' } Index: test/CodeGen/MIR/X86/stack-objects.mir =================================================================== --- test/CodeGen/MIR/X86/stack-objects.mir +++ test/CodeGen/MIR/X86/stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -simplify-mir -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses stack objects correctly. --- | Index: test/CodeGen/MIR/X86/variable-sized-stack-objects.mir =================================================================== --- test/CodeGen/MIR/X86/variable-sized-stack-objects.mir +++ test/CodeGen/MIR/X86/variable-sized-stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -simplify-mir -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses variable sized stack objects # correctly. Index: test/CodeGen/MIR/X86/virtual-registers.mir =================================================================== --- test/CodeGen/MIR/X86/virtual-registers.mir +++ test/CodeGen/MIR/X86/virtual-registers.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -march=x86-64 -simplify-mir -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses virtual register definitions and # references correctly. Index: test/CodeGen/X86/GlobalISel/irtranslator-call.ll =================================================================== --- test/CodeGen/X86/GlobalISel/irtranslator-call.ll +++ test/CodeGen/X86/GlobalISel/irtranslator-call.ll @@ -1,28 +1,11 @@ -; RUN: llc -mtriple i386 -global-isel -stop-after=irtranslator %s -o - | FileCheck %s -; RUN: llc -mtriple x86_64 -global-isel -stop-after=irtranslator %s -o - | FileCheck %s +; RUN: llc -simplify-mir -mtriple i386 -global-isel -stop-after=irtranslator %s -o - | FileCheck %s +; RUN: llc -simplify-mir -mtriple x86_64 -global-isel -stop-after=irtranslator %s -o - | FileCheck %s define void @test_void_return() { ; CHECK-LABEL: name: test_void_return ; CHECK: alignment: 4 -; CHECK-NEXT: exposesReturnsTwice: false ; CHECK-NEXT: noVRegs: false -; CHECK-NEXT: legalized: false -; CHECK-NEXT: regBankSelected: false -; CHECK-NEXT: selected: false ; CHECK-NEXT: tracksRegLiveness: true -; CHECK-NEXT: frameInfo: -; CHECK-NEXT: isFrameAddressTaken: false -; CHECK-NEXT: isReturnAddressTaken: false -; CHECK-NEXT: hasStackMap: false -; CHECK-NEXT: hasPatchPoint: false -; CHECK-NEXT: stackSize: 0 -; CHECK-NEXT: offsetAdjustment: 0 -; CHECK-NEXT: maxAlignment: 0 -; CHECK-NEXT: adjustsStack: false -; CHECK-NEXT: hasCalls: false -; CHECK-NEXT: hasOpaqueSPAdjustment: false -; CHECK-NEXT: hasVAStart: false -; CHECK-NEXT: hasMustTailInVarArgFunc: false ; CHECK-NEXT: body: ; CHECK-NEXT: bb.1.entry: ; CHECK-NEXT: RET 0 Index: test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll =================================================================== --- test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll +++ test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=i386-linux-gnu -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 -; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 +; RUN: llc -simplify-mir -mtriple=i386-linux-gnu -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 +; RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 @a1_8bit = external global i8 @a7_8bit = external global i8 @@ -11,8 +11,8 @@ ; ALL-LABEL: name: test_i8_args_8 ; X64: fixedStack: -; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 1, alignment: 8, isImmutable: true, isAliased: false -; X64: id: [[STACK0:[0-9]+]], offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false +; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 1, alignment: 8, isImmutable: true +; X64: id: [[STACK0:[0-9]+]], size: 1, alignment: 16, isImmutable: true ; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d ; X64: [[ARG1:%[0-9]+]](s8) = COPY %edi ; X64-NEXT: %{{[0-9]+}}(s8) = COPY %esi @@ -26,14 +26,14 @@ ; X64-NEXT: [[ARG8:%[0-9]+]](s8) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0) ; X32: fixedStack: -; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 1, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 1, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 1, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 1, alignment: 16, isImmutable: true, isAliased: false } -; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 1, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 1, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 1, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false } +; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 1, alignment: 4, isImmutable: true } +; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 1, alignment: 8, isImmutable: true } +; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 1, alignment: 4, isImmutable: true } +; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 1, alignment: 16, isImmutable: true } +; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 1, alignment: 4, isImmutable: true } +; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 1, alignment: 8, isImmutable: true } +; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 1, alignment: 4, isImmutable: true } +; X32: id: [[STACK0:[0-9]+]], size: 1, alignment: 16, isImmutable: true } ; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ; X32-NEXT: [[ARG1:%[0-9]+]](s8) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0) ; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] @@ -77,8 +77,8 @@ ; ALL-LABEL: name: test_i32_args_8 ; X64: fixedStack: -; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false -; X64: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false +; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true +; X64: id: [[STACK0:[0-9]+]], size: 4, alignment: 16, isImmutable: true ; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d ; X64: [[ARG1:%[0-9]+]](s32) = COPY %edi ; X64-NEXT: %{{[0-9]+}}(s32) = COPY %esi @@ -92,14 +92,14 @@ ; X64-NEXT: [[ARG8:%[0-9]+]](s32) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0) ; X32: fixedStack: -; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 4, alignment: 16, isImmutable: true, isAliased: false } -; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 4, alignment: 8, isImmutable: true } +; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 4, alignment: 16, isImmutable: true } +; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true } +; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK0:[0-9]+]], size: 4, alignment: 16, isImmutable: true } ; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ; X32-NEXT: [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) ; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] @@ -142,8 +142,8 @@ ; ALL-LABEL: name: test_i64_args_8 ; X64: fixedStack: -; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 8, alignment: 8, isImmutable: true, isAliased: false -; X64: id: [[STACK0:[0-9]+]], offset: 0, size: 8, alignment: 16, isImmutable: true, isAliased: false +; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 8, alignment: 8, isImmutable: true +; X64: id: [[STACK0:[0-9]+]], size: 8, alignment: 16, isImmutable: true ; X64: liveins: %rcx, %rdi, %rdx, %rsi, %r8, %r9 ; X64: [[ARG1:%[0-9]+]](s64) = COPY %rdi ; X64-NEXT: %{{[0-9]+}}(s64) = COPY %rsi @@ -157,22 +157,22 @@ ; X64-NEXT: [[ARG8:%[0-9]+]](s64) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0) ; X32: fixedStack: -; X32: id: [[STACK60:[0-9]+]], offset: 60, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK56:[0-9]+]], offset: 56, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK52:[0-9]+]], offset: 52, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK48:[0-9]+]], offset: 48, size: 4, alignment: 16, isImmutable: true, isAliased: false } -; X32: id: [[STACK44:[0-9]+]], offset: 44, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK40:[0-9]+]], offset: 40, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK36:[0-9]+]], offset: 36, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK32:[0-9]+]], offset: 32, size: 4, alignment: 16, isImmutable: true, isAliased: false } -; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 4, alignment: 16, isImmutable: true, isAliased: false } -; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +; X32: id: [[STACK60:[0-9]+]], offset: 60, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK56:[0-9]+]], offset: 56, size: 4, alignment: 8, isImmutable: true } +; X32: id: [[STACK52:[0-9]+]], offset: 52, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK48:[0-9]+]], offset: 48, size: 4, alignment: 16, isImmutable: true } +; X32: id: [[STACK44:[0-9]+]], offset: 44, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK40:[0-9]+]], offset: 40, size: 4, alignment: 8, isImmutable: true } +; X32: id: [[STACK36:[0-9]+]], offset: 36, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK32:[0-9]+]], offset: 32, size: 4, alignment: 16, isImmutable: true } +; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 4, alignment: 8, isImmutable: true } +; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 4, alignment: 16, isImmutable: true } +; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true } +; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK0:[0-9]+]], size: 4, alignment: 16, isImmutable: true } ; X32: [[ARG1L_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ; X32-NEXT: [[ARG1L:%[0-9]+]](s32) = G_LOAD [[ARG1L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) @@ -249,8 +249,8 @@ ; X64-NEXT: RET 0, implicit %xmm0 ; X32: fixedStack: -; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true } +; X32: id: [[STACK0:[0-9]+]], size: 4, alignment: 16, isImmutable: true } ; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ; X32-NEXT: [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) ; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] @@ -270,8 +270,8 @@ ; X64-NEXT: RET 0, implicit %xmm0 ; X32: fixedStack: -; X32: id: [[STACK4:[0-9]+]], offset: 8, size: 8, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 8, alignment: 16, isImmutable: true, isAliased: false } +; X32: id: [[STACK4:[0-9]+]], offset: 8, size: 8, alignment: 8, isImmutable: true } +; X32: id: [[STACK0:[0-9]+]], size: 8, alignment: 16, isImmutable: true } ; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ; X32-NEXT: [[ARG1:%[0-9]+]](s64) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0) ; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] @@ -290,11 +290,11 @@ ;X64-NEXT: RET 0, implicit %rax ;X32: fixedStack: -;X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +;X32: id: [[STACK0:[0-9]+]], size: 4, alignment: 16, isImmutable: true } ;X32: %1(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ;X32-NEXT: %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) ;X32-NEXT: %eax = COPY %0(p0) ;X32-NEXT: RET 0, implicit %eax ret i32 * %p1; -} \ No newline at end of file +} Index: test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir +++ test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --- | define i16 @test_mul_i16(i16 %arg1, i16 %arg2) { Index: test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir =================================================================== --- test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir +++ test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --- | define <8 x i16> @test_mul_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) #0 { %ret = mul <8 x i16> %arg1, %arg2 Index: test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir =================================================================== --- test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir +++ test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --- | define <16 x i16> @test_mul_v16i16(<16 x i16> %arg1, <16 x i16> %arg2) #0 { %ret = mul <16 x i16> %arg1, %arg2 Index: test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir =================================================================== --- test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir +++ test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --- | define <32 x i16> @test_mul_v32i16(<32 x i16> %arg1, <32 x i16> %arg2) #0 { Index: test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir =================================================================== --- test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir +++ test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY --- | define void @test_mul_vec256() { Index: test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir =================================================================== --- test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir +++ test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY --- | Index: test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir =================================================================== --- test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir +++ test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY --- | define i8 @test_add_i8(i8 %arg1, i8 %arg2) { Index: test/CodeGen/X86/GlobalISel/select-add.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-add.mir +++ test/CodeGen/X86/GlobalISel/select-add.mir @@ -1,7 +1,7 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL --- | define i64 @test_add_i64(i64 %arg1, i64 %arg2) { Index: test/CodeGen/X86/GlobalISel/select-cmp.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-cmp.mir +++ test/CodeGen/X86/GlobalISel/select-cmp.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK --- | define i32 @test_icmp_eq_i8(i8 %a, i8 %b) { Index: test/CodeGen/X86/GlobalISel/select-constant.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-constant.mir +++ test/CodeGen/X86/GlobalISel/select-constant.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK --- | define i8 @const_i8() { Index: test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir +++ test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 --- | define i64 @test_zext_i1(i8 %a) { Index: test/CodeGen/X86/GlobalISel/select-ext.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-ext.mir +++ test/CodeGen/X86/GlobalISel/select-ext.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 +# RUN: llc -simplify-mir -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 --- | define i32 @test_zext_i1(i1 %a) { Index: test/CodeGen/X86/GlobalISel/select-gep.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-gep.mir +++ test/CodeGen/X86/GlobalISel/select-gep.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK --- | define i32* @test_gep_i32(i32* %arr) { Index: test/CodeGen/X86/GlobalISel/select-inc.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-inc.mir +++ test/CodeGen/X86/GlobalISel/select-inc.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,INC -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+slow-incdec -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,ADD +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,INC +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+slow-incdec -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,ADD --- | define i8 @test_add_i8(i8 %arg1) { Index: test/CodeGen/X86/GlobalISel/select-memop-x32.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-memop-x32.mir +++ test/CodeGen/X86/GlobalISel/select-memop-x32.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL +# RUN: llc -simplify-mir -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --- | define i8 @test_load_i8(i8* %p1) { Index: test/CodeGen/X86/GlobalISel/select-memop.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-memop.mir +++ test/CodeGen/X86/GlobalISel/select-memop.mir @@ -1,7 +1,7 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL --- | define i8 @test_load_i8(i8* %p1) { Index: test/CodeGen/X86/GlobalISel/select-mul-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-mul-scalar.mir +++ test/CodeGen/X86/GlobalISel/select-mul-scalar.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --- | define i16 @test_mul_i16(i16 %arg1, i16 %arg2) { Index: test/CodeGen/X86/GlobalISel/select-mul-vec.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-mul-vec.mir +++ test/CodeGen/X86/GlobalISel/select-mul-vec.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define <8 x i16> @test_mul_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) #0 { Index: test/CodeGen/X86/GlobalISel/select-sub.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-sub.mir +++ test/CodeGen/X86/GlobalISel/select-sub.mir @@ -1,7 +1,7 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F -# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL --- | define i64 @test_sub_i64(i64 %arg1, i64 %arg2) { Index: test/CodeGen/X86/GlobalISel/select-trunc.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-trunc.mir +++ test/CodeGen/X86/GlobalISel/select-trunc.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK +# RUN: llc -simplify-mir -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK --- | define i1 @trunc_i32toi1(i32 %a) { %r = trunc i32 %a to i1 Index: test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll =================================================================== --- test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll +++ test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=x86_64-unknown-unknown -o - -stop-after machine-scheduler %s | FileCheck %s --check-prefix=PRE-RA -; RUN: llc -mtriple=x86_64-unknown-unknown -o - -stop-after prologepilog %s | FileCheck %s --check-prefix=POST-RA +; RUN: llc -simplify-mir -mtriple=x86_64-unknown-unknown -o - -stop-after machine-scheduler %s | FileCheck %s --check-prefix=PRE-RA +; RUN: llc -simplify-mir -mtriple=x86_64-unknown-unknown -o - -stop-after prologepilog %s | FileCheck %s --check-prefix=POST-RA ; This test verifies that the virtual register references in machine function's ; liveins are cleared after register allocation.