Index: include/llvm/Support/AArch64TargetParser.def =================================================================== --- include/llvm/Support/AArch64TargetParser.def +++ include/llvm/Support/AArch64TargetParser.def @@ -54,13 +54,19 @@ AARCH64_CPU_NAME("cortex-a35", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO)) AARCH64_CPU_NAME("cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true, - ( AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO)) + (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO)) AARCH64_CPU_NAME("cortex-a57", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO)) +AARCH64_CPU_NAME("cortex-a57.cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO)) AARCH64_CPU_NAME("cortex-a72", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO)) +AARCH64_CPU_NAME("cortex-a72.cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO)) AARCH64_CPU_NAME("cortex-a73", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO)) +AARCH64_CPU_NAME("cortex-a73.cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, + (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO)) AARCH64_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_SIMD | AArch64::AEK_CRYPTO)) AARCH64_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, Index: include/llvm/Support/ARMTargetParser.def =================================================================== --- include/llvm/Support/ARMTargetParser.def +++ include/llvm/Support/ARMTargetParser.def @@ -238,8 +238,11 @@ ARM_CPU_NAME("cortex-a35", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true, ARM::AEK_CRC) ARM_CPU_NAME("cortex-a57", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) +ARM_CPU_NAME("cortex-a57.cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("cortex-a72", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) +ARM_CPU_NAME("cortex-a72.cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("cortex-a73", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) +ARM_CPU_NAME("cortex-a73.cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("exynos-m2", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) Index: lib/Target/AArch64/AArch64.td =================================================================== --- lib/Target/AArch64/AArch64.td +++ lib/Target/AArch64/AArch64.td @@ -211,6 +211,20 @@ FeaturePredictableSelectIsExpensive ]>; +def ProcA57A53 : SubtargetFeature<"a57a53", "ARMProcFamily", "CortexA57A53", + "Cortex-A57.Cortex-A53 ARM processors", [ + FeatureBalanceFPOps, + FeatureCRC, + FeatureCrypto, + FeatureCustomCheapAsMoveHandling, + FeatureFPARMv8, + FeatureNEON, + FeaturePerfMon, + FeaturePostRAScheduler, + FeatureUseAA + ]>; + + def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", "Cortex-A72 ARM processors", [ FeatureCRC, @@ -220,6 +234,20 @@ FeaturePerfMon ]>; +def ProcA72A53 : SubtargetFeature<"a72a53", "ARMProcFamily", "CortexA72A53", + "Cortex-A72.Cortex-A53 ARM processors", [ + FeatureBalanceFPOps, + FeatureCRC, + FeatureCrypto, + FeatureCustomCheapAsMoveHandling, + FeatureFPARMv8, + FeatureNEON, + FeaturePerfMon, + FeaturePostRAScheduler, + FeatureUseAA + ]>; + + def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", "Cortex-A73 ARM processors", [ FeatureCRC, @@ -229,6 +257,20 @@ FeaturePerfMon ]>; +def ProcA73A53 : SubtargetFeature<"a73a53", "ARMProcFamily", "CortexA73A53", + "Cortex-A73.Cortex-A53 ARM processors", [ + FeatureBalanceFPOps, + FeatureCRC, + FeatureCrypto, + FeatureCustomCheapAsMoveHandling, + FeatureFPARMv8, + FeatureNEON, + FeaturePerfMon, + FeaturePostRAScheduler, + FeatureUseAA + ]>; + + def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone", "Cyclone", [ FeatureAlternateSExtLoadCVTF32Pattern, @@ -372,6 +414,10 @@ // FIXME: Cortex-A72 and Cortex-A73 are currently modeled as a Cortex-A57. def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>; def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>; +// FIXME: big.LITTLE configurations are currently modeled as the little core. +def : ProcessorModel<"cortex-a57.cortex-a53", CortexA53Model, [ProcA57A53]>; +def : ProcessorModel<"cortex-a72.cortex-a53", CortexA53Model, [ProcA72A53]>; +def : ProcessorModel<"cortex-a73.cortex-a53", CortexA53Model, [ProcA73A53]>; def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>; def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>; def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>; Index: lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- lib/Target/AArch64/AArch64Subtarget.h +++ lib/Target/AArch64/AArch64Subtarget.h @@ -39,8 +39,11 @@ CortexA35, CortexA53, CortexA57, + CortexA57A53, CortexA72, + CortexA72A53, CortexA73, + CortexA73A53, Cyclone, ExynosM1, Falkor, Index: lib/Target/AArch64/AArch64Subtarget.cpp =================================================================== --- lib/Target/AArch64/AArch64Subtarget.cpp +++ lib/Target/AArch64/AArch64Subtarget.cpp @@ -100,8 +100,11 @@ break; case CortexA35: break; case CortexA53: break; + case CortexA57A53: break; case CortexA72: break; + case CortexA72A53: break; case CortexA73: break; + case CortexA73A53: break; case Others: break; } } Index: lib/Target/ARM/ARM.td =================================================================== --- lib/Target/ARM/ARM.td +++ lib/Target/ARM/ARM.td @@ -339,10 +339,16 @@ "Cortex-A53 ARM processors", []>; def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", "Cortex-A57 ARM processors", []>; +def ProcA57A53 : SubtargetFeature<"a57a53", "ARMProcFamily", "CortexA57A53", + "Cortex-A57.Cortex-A53 ARM Processors">; def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", "Cortex-A72 ARM processors", []>; +def ProcA72A53 : SubtargetFeature<"a72a53", "ARMProcFamily", "CortexA72A53", + "Cortex-A72.Cortex-A53 ARM Processors">; def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", "Cortex-A73 ARM processors", []>; +def ProcA73A53 : SubtargetFeature<"a73a53", "ARMProcFamily", "CortexA73A53", + "Cortex-A73.Cortex-A53 ARM Processors">; def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", "Qualcomm Krait processors", []>; @@ -793,18 +799,39 @@ FeatureCRC, FeatureFPAO]>; +def : ProcNoItin<"cortex-a57.cortex-a53", [ARMv8a, ProcA57A53, + FeatureHWDiv, + FeatureHWDivARM, + FeatureCrypto, + FeatureCRC, + FeatureFPAO]>; + def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, FeatureHWDiv, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; +def : ProcNoItin<"cortex-a72.cortex-a53", [ARMv8a, ProcA72A53, + FeatureHWDiv, + FeatureHWDivARM, + FeatureCrypto, + FeatureCRC, + FeatureFPAO]>; + def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, FeatureHWDiv, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; +def : ProcNoItin<"cortex-a73.cortex-a53", [ARMv8a, ProcA73A53, + FeatureHWDiv, + FeatureHWDivARM, + FeatureCrypto, + FeatureCRC, + FeatureFPAO]>; + // Cyclone is very similar to swift def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, FeatureHasRetAddrStack, Index: lib/Target/ARM/ARMSubtarget.h =================================================================== --- lib/Target/ARM/ARMSubtarget.h +++ lib/Target/ARM/ARMSubtarget.h @@ -51,9 +51,12 @@ CortexA5, CortexA53, CortexA57, + CortexA57A53, CortexA7, CortexA72, + CortexA72A53, CortexA73, + CortexA73A53, CortexA8, CortexA9, CortexM3, Index: lib/Target/ARM/ARMSubtarget.cpp =================================================================== --- lib/Target/ARM/ARMSubtarget.cpp +++ lib/Target/ARM/ARMSubtarget.cpp @@ -267,8 +267,11 @@ case CortexA35: case CortexA53: case CortexA57: + case CortexA57A53: case CortexA72: + case CortexA72A53: case CortexA73: + case CortexA73A53: case CortexR4: case CortexR4F: case CortexR5: Index: test/CodeGen/AArch64/cpus.ll =================================================================== --- test/CodeGen/AArch64/cpus.ll +++ test/CodeGen/AArch64/cpus.ll @@ -5,8 +5,11 @@ ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a35 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57.cortex-a53 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72.cortex-a53 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a73 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a73.cortex-a53 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m1 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m2 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s Index: test/CodeGen/ARM/cpus.ll =================================================================== --- /dev/null +++ test/CodeGen/ARM/cpus.ll @@ -0,0 +1,25 @@ +; This tests that llc accepts valid ARM CPUs + + +; RUN: llc < %s -mtriple=arm-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv7-unknown-unknown -mcpu=cortex-a7 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv7-unknown-unknown -mcpu=cortex-a9 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv7-unknown-unknown -mcpu=cortex-a15 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv8-unknown-unknown -mcpu=cortex-a35 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv8-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv8-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv8-unknown-unknown -mcpu=cortex-a57.cortex-a53 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv8-unknown-unknown -mcpu=cortex-a72 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv8-unknown-unknown -mcpu=cortex-a72.cortex-a53 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv8-unknown-unknown -mcpu=cortex-a73 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv8-unknown-unknown -mcpu=cortex-a73.cortex-a53 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=armv8-unknown-unknown -mcpu=kryo 2>&1 | FileCheck %s + +; RUN: llc < %s -mtriple=arm-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID + +; CHECK-NOT: {{.*}} is not a recognized processor for this target +; INVALID: {{.*}} is not a recognized processor for this target + +define i32 @f(i64 %z) { + ret i32 0 +}