Index: include/llvm/Support/ELFRelocs/AArch64.def =================================================================== --- include/llvm/Support/ELFRelocs/AArch64.def +++ include/llvm/Support/ELFRelocs/AArch64.def @@ -109,8 +109,8 @@ ELF_RELOC(R_AARCH64_TLSDESC_LD_PREL19, 0x230) ELF_RELOC(R_AARCH64_TLSDESC_ADR_PREL21, 0x231) ELF_RELOC(R_AARCH64_TLSDESC_ADR_PAGE21, 0x232) -ELF_RELOC(R_AARCH64_TLSDESC_LD64_LO12_NC, 0x233) -ELF_RELOC(R_AARCH64_TLSDESC_ADD_LO12_NC, 0x234) +ELF_RELOC(R_AARCH64_TLSDESC_LD64_LO12, 0x233) +ELF_RELOC(R_AARCH64_TLSDESC_ADD_LO12, 0x234) ELF_RELOC(R_AARCH64_TLSDESC_OFF_G1, 0x235) ELF_RELOC(R_AARCH64_TLSDESC_OFF_G0_NC, 0x236) ELF_RELOC(R_AARCH64_TLSDESC_LDR, 0x237) @@ -144,21 +144,28 @@ ELF_RELOC(R_AARCH64_P32_ADR_PREL_PG_HI21, 0x00b) ELF_RELOC(R_AARCH64_P32_ADD_ABS_LO12_NC, 0x00c) ELF_RELOC(R_AARCH64_P32_LDST8_ABS_LO12_NC, 0x00d) +ELF_RELOC(R_AARCH64_P32_LDST16_ABS_LO12_NC, 0x00e) +ELF_RELOC(R_AARCH64_P32_LDST32_ABS_LO12_NC, 0x00f) +ELF_RELOC(R_AARCH64_P32_LDST64_ABS_LO12_NC, 0x010) +ELF_RELOC(R_AARCH64_P32_LDST128_ABS_LO12_NC, 0x011) ELF_RELOC(R_AARCH64_P32_TSTBR14, 0x012) ELF_RELOC(R_AARCH64_P32_CONDBR19, 0x013) ELF_RELOC(R_AARCH64_P32_JUMP26, 0x014) ELF_RELOC(R_AARCH64_P32_CALL26, 0x015) -ELF_RELOC(R_AARCH64_P32_LDST16_ABS_LO12_NC, 0x00e) -ELF_RELOC(R_AARCH64_P32_LDST32_ABS_LO12_NC, 0x00f) -ELF_RELOC(R_AARCH64_P32_LDST64_ABS_LO12_NC, 0x010) ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G0, 0x016) ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G0_NC, 0x017) ELF_RELOC(R_AARCH64_P32_MOVW_PREL_G1, 0x018) -ELF_RELOC(R_AARCH64_P32_LDST128_ABS_LO12_NC, 0x011) ELF_RELOC(R_AARCH64_P32_GOT_LD_PREL19, 0x019) ELF_RELOC(R_AARCH64_P32_ADR_GOT_PAGE, 0x01a) -ELF_RELOC(R_AARCH64_P32_LD64_GOT_LO12_NC, 0x01b) +ELF_RELOC(R_AARCH64_P32_LD32_GOT_LO12_NC, 0x01b) ELF_RELOC(R_AARCH64_P32_LD32_GOTPAGE_LO14, 0x01c) +ELF_RELOC(R_AARCH64_P32_TLSGD_ADR_PREL21, 0x050) +ELF_RELOC(R_AARCH64_P32_TLSGD_ADR_PAGE21, 0x051) +ELF_RELOC(R_AARCH64_P32_TLSGD_ADD_LO12_NC, 0x052) +ELF_RELOC(R_AARCH64_P32_TLSLD_ADR_PREL21, 0x053) +ELF_RELOC(R_AARCH64_P32_TLSLD_ADR_PAGE21, 0x054) +ELF_RELOC(R_AARCH64_P32_TLSLD_ADD_LO12_NC, 0x055) +ELF_RELOC(R_AARCH64_P32_TLSLD_LD_PREL19, 0x056) ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1, 0x057) ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0, 0x058) ELF_RELOC(R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC, 0x059) @@ -173,6 +180,8 @@ ELF_RELOC(R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC, 0x062) ELF_RELOC(R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12, 0x063) ELF_RELOC(R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC, 0x064) +ELF_RELOC(R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12, 0x065) +ELF_RELOC(R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC,0x066) ELF_RELOC(R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21, 0x067) ELF_RELOC(R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC, 0x068) ELF_RELOC(R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19, 0x069) @@ -190,12 +199,20 @@ ELF_RELOC(R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC, 0x075) ELF_RELOC(R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12, 0x076) ELF_RELOC(R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC, 0x077) -ELF_RELOC(R_AARCH64_P32_TLSDESC_ADR_PAGE21, 0x051) -ELF_RELOC(R_AARCH64_P32_TLSDESC_LD32_LO12_NC, 0x07d) -ELF_RELOC(R_AARCH64_P32_TLSDESC_ADD_LO12_NC, 0x034) +ELF_RELOC(R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12, 0x078) +ELF_RELOC(R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC, 0x079) +ELF_RELOC(R_AARCH64_P32_TLSDESC_LD_PREL19, 0x07a) +ELF_RELOC(R_AARCH64_P32_TLSDESC_ADR_PREL21, 0x07b) +ELF_RELOC(R_AARCH64_P32_TLSDESC_ADR_PAGE21, 0x07c) +ELF_RELOC(R_AARCH64_P32_TLSDESC_LD32_LO12, 0x07d) +ELF_RELOC(R_AARCH64_P32_TLSDESC_ADD_LO12, 0x07e) ELF_RELOC(R_AARCH64_P32_TLSDESC_CALL, 0x07f) ELF_RELOC(R_AARCH64_P32_COPY, 0x0b4) ELF_RELOC(R_AARCH64_P32_GLOB_DAT, 0x0b5) ELF_RELOC(R_AARCH64_P32_JUMP_SLOT, 0x0b6) ELF_RELOC(R_AARCH64_P32_RELATIVE, 0x0b7) +ELF_RELOC(R_AARCH64_P32_TLS_DTPREL, 0x0b8) +ELF_RELOC(R_AARCH64_P32_TLS_DTPMOD, 0x0b9) +ELF_RELOC(R_AARCH64_P32_TLS_TPREL, 0x0ba) +ELF_RELOC(R_AARCH64_P32_TLSDESC, 0x0bb) ELF_RELOC(R_AARCH64_P32_IRELATIVE, 0x0bc) Index: lib/Target/AArch64/AArch64AsmPrinter.cpp =================================================================== --- lib/Target/AArch64/AArch64AsmPrinter.cpp +++ lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -580,8 +580,7 @@ const MachineOperand &MO_Sym = MI->getOperand(0); MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym); MCOperand Sym, SymTLSDescLo12, SymTLSDesc; - MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | - AArch64II::MO_NC); + MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF); MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE); MCInstLowering.lowerOperand(MO_Sym, Sym); MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12); Index: lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp @@ -19,6 +19,7 @@ #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCFixup.h" #include "llvm/MC/MCValue.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" #include @@ -69,34 +70,34 @@ return true; case AArch64MCExpr::VK_ABS_G2_S: Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2)); - return ELF::R_AARCH64_NONE; + return true; case AArch64MCExpr::VK_ABS_G2_NC: Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC)); - return ELF::R_AARCH64_NONE; + return true; case AArch64MCExpr::VK_ABS_G1_S: Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1)); - return ELF::R_AARCH64_NONE; + return true; case AArch64MCExpr::VK_ABS_G1_NC: Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC)); - return ELF::R_AARCH64_NONE; + return true; case AArch64MCExpr::VK_DTPREL_G2: Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2)); - return ELF::R_AARCH64_NONE; + return true; case AArch64MCExpr::VK_DTPREL_G1_NC: Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC)); - return ELF::R_AARCH64_NONE; + return true; case AArch64MCExpr::VK_TPREL_G2: Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2)); - return ELF::R_AARCH64_NONE; + return true; case AArch64MCExpr::VK_TPREL_G1_NC: Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC)); - return ELF::R_AARCH64_NONE; + return true; case AArch64MCExpr::VK_GOTTPREL_G1: Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1)); - return ELF::R_AARCH64_NONE; + return true; case AArch64MCExpr::VK_GOTTPREL_G0_NC: Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC)); - return ELF::R_AARCH64_NONE; + return true; default: return false; } return false; @@ -141,6 +142,16 @@ case AArch64::fixup_aarch64_pcrel_adrp_imm21: if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC) return R_CLS(ADR_PREL_PG_HI21); + if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) { + if (IsILP32) { + Ctx.reportError(Fixup.getLoc(), + "invalid fixup for 32-bit pcrel ADRP instruction " + "VK_ABS VK_NC"); + return ELF::R_AARCH64_NONE; + } else { + return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC; + } + } if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) return R_CLS(ADR_GOT_PAGE); if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC) @@ -179,7 +190,8 @@ return R_CLS(ABS32); case FK_Data_8: if (IsILP32) { - Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(ABS64)); + Ctx.reportError(Fixup.getLoc(), "ILP32 8 byte absolute data " + "relocation not supported (LP64 eqv: ABS64)"); return ELF::R_AARCH64_NONE; } else return ELF::R_AARCH64_ABS64; @@ -197,7 +209,7 @@ if (RefKind == AArch64MCExpr::VK_TPREL_LO12) return R_CLS(TLSLE_ADD_TPREL_LO12); if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12) - return R_CLS(TLSDESC_ADD_LO12_NC); + return R_CLS(TLSDESC_ADD_LO12); if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) return R_CLS(ADD_ABS_LO12_NC); @@ -245,15 +257,67 @@ return R_CLS(TLSLE_LDST32_TPREL_LO12); if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) return R_CLS(TLSLE_LDST32_TPREL_LO12_NC); + if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) { + if (IsILP32) { + return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC; + } else { + Ctx.reportError(Fixup.getLoc(), + "LP64 4 byte unchecked GOT load/store relocation " + "not supported (ILP32 eqv: LD32_GOT_LO12_NC"); + return ELF::R_AARCH64_NONE; + } + } + if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) { + if (IsILP32) { + Ctx.reportError(Fixup.getLoc(), + "ILP32 4 byte checked GOT load/store relocation " + "not supported (unchecked eqv: LD32_GOT_LO12_NC)"); + } else { + Ctx.reportError(Fixup.getLoc(), + "LP64 4 byte checked GOT load/store relocation " + "not supported (unchecked/ILP32 eqv: " + "LD32_GOT_LO12_NC)"); + } + return ELF::R_AARCH64_NONE; + } + if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) { + if (IsILP32) { + return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC; + } else { + Ctx.reportError(Fixup.getLoc(), "LP64 32-bit load/store " + "relocation not supported (ILP32 eqv: " + "TLSIE_LD32_GOTTPREL_LO12_NC)"); + return ELF::R_AARCH64_NONE; + } + } + if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) { + if (IsILP32) { + return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12; + } else { + Ctx.reportError(Fixup.getLoc(), + "LP64 4 byte TLSDESC load/store relocation " + "not supported (ILP32 eqv: TLSDESC_LD64_LO12)"); + return ELF::R_AARCH64_NONE; + } + } Ctx.reportError(Fixup.getLoc(), - "invalid fixup for 32-bit load/store instruction"); + "invalid fixup for 32-bit load/store instruction " + "fixup_aarch64_ldst_imm12_scale4"); return ELF::R_AARCH64_NONE; case AArch64::fixup_aarch64_ldst_imm12_scale8: if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) return R_CLS(LDST64_ABS_LO12_NC); - if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) - return R_CLS(LD64_GOT_LO12_NC); + if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) { + if (!IsILP32) { + return ELF::R_AARCH64_LD64_GOT_LO12_NC; + } else { + Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " + "relocation not supported (LP64 eqv: " + "LD64_GOT_LO12_NC)"); + return ELF::R_AARCH64_NONE; + } + } if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) return R_CLS(TLSLD_LDST64_DTPREL_LO12); if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) @@ -262,19 +326,40 @@ return R_CLS(TLSLE_LDST64_TPREL_LO12); if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) return R_CLS(TLSLE_LDST64_TPREL_LO12_NC); - if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) - return IsILP32 ? ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC - : ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; - if (SymLoc == AArch64MCExpr::VK_TLSDESC && IsNC) - return IsILP32 ? ELF::R_AARCH64_P32_TLSDESC_LD32_LO12_NC - : ELF::R_AARCH64_TLSDESC_LD64_LO12_NC; - + if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) { + if (!IsILP32) { + return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; + } else { + Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " + "relocation not supported (LP64 eqv: " + "TLSIE_LD64_GOTTPREL_LO12_NC)"); + return ELF::R_AARCH64_NONE; + } + } + if (SymLoc == AArch64MCExpr::VK_TLSDESC) { + if (!IsILP32) { + return ELF::R_AARCH64_TLSDESC_LD64_LO12; + } else { + Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " + "relocation not supported (LP64 eqv: " + "TLSDESC_LD64_LO12)"); + return ELF::R_AARCH64_NONE; + } + } Ctx.reportError(Fixup.getLoc(), "invalid fixup for 64-bit load/store instruction"); return ELF::R_AARCH64_NONE; case AArch64::fixup_aarch64_ldst_imm12_scale16: if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) return R_CLS(LDST128_ABS_LO12_NC); + if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) + return R_CLS(TLSLD_LDST128_DTPREL_LO12); + if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC) + return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC); + if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC) + return R_CLS(TLSLE_LDST128_TPREL_LO12); + if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) + return R_CLS(TLSLE_LDST128_TPREL_LO12_NC); Ctx.reportError(Fixup.getLoc(), "invalid fixup for 128-bit load/store instruction"); Index: lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h +++ lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h @@ -62,6 +62,7 @@ // since a user would write ":lo12:"). VK_CALL = VK_ABS, VK_ABS_PAGE = VK_ABS | VK_PAGE, + VK_ABS_PAGE_NC = VK_ABS | VK_PAGE | VK_NC, VK_ABS_G3 = VK_ABS | VK_G3, VK_ABS_G2 = VK_ABS | VK_G2, VK_ABS_G2_S = VK_SABS | VK_G2, @@ -95,7 +96,7 @@ VK_TPREL_HI12 = VK_TPREL | VK_HI12, VK_TPREL_LO12 = VK_TPREL | VK_PAGEOFF, VK_TPREL_LO12_NC = VK_TPREL | VK_PAGEOFF | VK_NC, - VK_TLSDESC_LO12 = VK_TLSDESC | VK_PAGEOFF | VK_NC, + VK_TLSDESC_LO12 = VK_TLSDESC | VK_PAGEOFF, VK_TLSDESC_PAGE = VK_TLSDESC | VK_PAGE, VK_INVALID = 0xfff Index: lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp @@ -62,6 +62,7 @@ case VK_TPREL_LO12_NC: return ":tprel_lo12_nc:"; case VK_TLSDESC_LO12: return ":tlsdesc_lo12:"; case VK_ABS_PAGE: return ""; + case VK_ABS_PAGE_NC: return ":pg_hi21_nc:"; case VK_GOT_PAGE: return ":got:"; case VK_GOT_LO12: return ":got_lo12:"; case VK_GOTTPREL_PAGE: return ":gottprel:"; Index: test/CodeGen/AArch64/arm64-tls-dynamics.ll =================================================================== --- test/CodeGen/AArch64/arm64-tls-dynamics.ll +++ test/CodeGen/AArch64/arm64-tls-dynamics.ll @@ -30,13 +30,13 @@ ; CHECK-NOLD: ldr w0, [x[[TP]], x0] ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL } @@ -56,13 +56,13 @@ ; CHECK: add x0, [[TP]], x0 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL } @@ -95,15 +95,15 @@ ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12 ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL } @@ -131,15 +131,15 @@ ret i32* @local_dynamic_var ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12 ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL } Index: test/MC/AArch64/adrp-relocation.s =================================================================== --- test/MC/AArch64/adrp-relocation.s +++ test/MC/AArch64/adrp-relocation.s @@ -1,4 +1,6 @@ // RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s| llvm-readobj -r - | FileCheck %s +// RUN: llvm-mc -target-abi=ilp32 -triple=aarch64-linux-gnu -filetype=obj \ +// RUN: -o - %s| llvm-readobj -r - | FileCheck -check-prefix=CHECK-ILP32 %s .text // These should produce an ADRP/ADD pair to calculate the address of // testfn. The important point is that LLVM shouldn't think it can deal with the @@ -16,3 +18,7 @@ // CHECK: R_AARCH64_ADR_GOT_PAGE sym // CHECK: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym // CHECK: R_AARCH64_TLSDESC_ADR_PAGE21 sym +// CHECK-ILP32: R_AARCH64_P32_ADR_PREL_PG_HI21 sym +// CHECK-ILP32: R_AARCH64_P32_ADR_GOT_PAGE sym +// CHECK-ILP32: R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym +// CHECK-ILP32: R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym Index: test/MC/AArch64/arm32-elf-relocs.s =================================================================== --- test/MC/AArch64/arm32-elf-relocs.s +++ test/MC/AArch64/arm32-elf-relocs.s @@ -25,7 +25,7 @@ add x5, x0, #:tlsdesc_lo12:sym // CHECK: add x5, x0, :tlsdesc_lo12:sym -// CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym +// CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12 sym add x0, x2, #:lo12:sym+8 // CHECK: add x0, x2, :lo12:sym @@ -49,33 +49,33 @@ add x5, x0, #:tlsdesc_lo12:sym+70 // CHECK: add x5, x0, :tlsdesc_lo12:sym+70 -// CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym+70 +// CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12 sym+70 .hword sym + 4 - . // CHECK-OBJ-ILP32: 30 R_AARCH64_P32_PREL16 sym+4 .word sym - . + 8 -// CHECK-OBJ-ILP32 32 R_AARCH64_P32_PREL32 sym+8 +// CHECK-OBJ-ILP32: 32 R_AARCH64_P32_PREL32 sym+8 .hword sym -// CHECK-OBJ-ILP32 3e R_AARCH64_P32_ABS16 sym +// CHECK-OBJ-ILP32: 36 R_AARCH64_P32_ABS16 sym .word sym+1 -// CHECK-OBJ-ILP32 40 R_AARCH64_P32_ABS32 sym+1 +// CHECK-OBJ-ILP32: 38 R_AARCH64_P32_ABS32 sym+1 adrp x0, sym // CHECK: adrp x0, sym -// CHECK-OBJ-ILP32 4c R_AARCH64_P32_ADR_PREL_PG_HI21 sym +// CHECK-OBJ-ILP32: 3c R_AARCH64_P32_ADR_PREL_PG_HI21 sym adrp x15, :got:sym // CHECK: adrp x15, :got:sym -// CHECK-OBJ-ILP32 50 R_AARCH64_P32_ADR_GOT_PAGE sym +// CHECK-OBJ-ILP32: 40 R_AARCH64_P32_ADR_GOT_PAGE sym adrp x29, :gottprel:sym // CHECK: adrp x29, :gottprel:sym -// CHECK-OBJ-ILP32 54 R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym +// CHECK-OBJ-ILP32: 44 R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym adrp x2, :tlsdesc:sym // CHECK: adrp x2, :tlsdesc:sym -// CHECK-OBJ-ILP32 58 R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym +// CHECK-OBJ-ILP32: 48 R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym // LLVM is not competent enough to do this relocation because the // page boundary could occur anywhere after linking. A relocation @@ -84,7 +84,7 @@ .global trickQuestion trickQuestion: // CHECK: adrp x3, trickQuestion -// CHECK-OBJ-ILP32 5c R_AARCH64_P32_ADR_PREL_PG_HI21 trickQuestion +// CHECK-OBJ-ILP32: 4c R_AARCH64_P32_ADR_PREL_PG_HI21 trickQuestion ldrb w2, [x3, :lo12:sym] ldrsb w5, [x7, #:lo12:sym] @@ -94,10 +94,10 @@ // CHECK: ldrsb w5, [x7, :lo12:sym] // CHECK: ldrsb x11, [x13, :lo12:sym] // CHECK: ldr b17, [x19, :lo12:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym ldrb w23, [x29, #:dtprel_lo12_nc:sym] ldrsb w23, [x19, #:dtprel_lo12:sym] @@ -107,10 +107,10 @@ // CHECK: ldrsb w23, [x19, :dtprel_lo12:sym] // CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym] // CHECK: ldr b11, [x7, :dtprel_lo12:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym ldrb w1, [x2, :tprel_lo12:sym] ldrsb w3, [x4, #:tprel_lo12_nc:sym] @@ -120,10 +120,10 @@ // CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym] // CHECK: ldrsb x5, [x6, :tprel_lo12:sym] // CHECK: ldr b7, [x8, :tprel_lo12_nc:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym ldrh w2, [x3, #:lo12:sym] ldrsh w5, [x7, :lo12:sym] @@ -133,10 +133,10 @@ // CHECK: ldrsh w5, [x7, :lo12:sym] // CHECK: ldrsh x11, [x13, :lo12:sym] // CHECK: ldr h17, [x19, :lo12:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym ldrh w23, [x29, #:dtprel_lo12_nc:sym] ldrsh w23, [x19, :dtprel_lo12:sym] @@ -146,10 +146,10 @@ // CHECK: ldrsh w23, [x19, :dtprel_lo12:sym] // CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym] // CHECK: ldr h11, [x7, :dtprel_lo12:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym ldrh w1, [x2, :tprel_lo12:sym] ldrsh w3, [x4, #:tprel_lo12_nc:sym] @@ -159,10 +159,10 @@ // CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym] // CHECK: ldrsh x5, [x6, :tprel_lo12:sym] // CHECK: ldr h7, [x8, :tprel_lo12_nc:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym ldr w1, [x2, #:lo12:sym] ldrsw x3, [x4, #:lo12:sym] @@ -170,9 +170,9 @@ // CHECK: ldr w1, [x2, :lo12:sym] // CHECK: ldrsw x3, [x4, :lo12:sym] // CHECK: ldr s4, [x5, :lo12:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym ldr w1, [x2, :dtprel_lo12:sym] ldrsw x3, [x4, #:dtprel_lo12_nc:sym] @@ -180,9 +180,9 @@ // CHECK: ldr w1, [x2, :dtprel_lo12:sym] // CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym] // CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym ldr w1, [x2, #:tprel_lo12:sym] @@ -191,53 +191,65 @@ // CHECK: ldr w1, [x2, :tprel_lo12:sym] // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym] // CHECK: ldr s4, [x5, :tprel_lo12_nc:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym ldr x28, [x27, :lo12:sym] - ldr d26, [x25, #:lo12:sym] + ldr d26, [x25, :lo12:sym] // CHECK: ldr x28, [x27, :lo12:sym] // CHECK: ldr d26, [x25, :lo12:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST64_ABS_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST64_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym - ldr x24, [x23, #:got_lo12:sym] - ldr d22, [x21, :got_lo12:sym] -// CHECK: ldr x24, [x23, :got_lo12:sym] -// CHECK: ldr d22, [x21, :got_lo12:sym] -// CHECK-OBJ-ILP32 R_AARCH64_LD32_GOT_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_LD32_GOT_LO12_NC sym + ldr w24, [x23, :got_lo12:sym] + ldr s22, [x21, :got_lo12:sym] +// CHECK: ldr w24, [x23, :got_lo12:sym] +// CHECK: ldr s22, [x21, :got_lo12:sym] +// CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym ldr x24, [x23, :dtprel_lo12_nc:sym] - ldr d22, [x21, #:dtprel_lo12:sym] + ldr d22, [x21, :dtprel_lo12:sym] // CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym] // CHECK: ldr d22, [x21, :dtprel_lo12:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 sym - ldr x24, [x23, #:tprel_lo12:sym] + ldr q24, [x23, :dtprel_lo12_nc:sym] + ldr q22, [x21, :dtprel_lo12:sym] +// CHECK: ldr q24, [x23, :dtprel_lo12_nc:sym] +// CHECK: ldr q22, [x21, :dtprel_lo12:sym] +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12 sym + + ldr x24, [x23, :tprel_lo12:sym] ldr d22, [x21, :tprel_lo12_nc:sym] // CHECK: ldr x24, [x23, :tprel_lo12:sym] // CHECK: ldr d22, [x21, :tprel_lo12_nc:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym - -# ldr x24, [x23, :gottprel_lo12:sym] -# ldr d22, [x21, #:gottprel_lo12:sym] +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym - ldr x24, [x23, #:tlsdesc_lo12:sym] - ldr d22, [x21, :tlsdesc_lo12:sym] -// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym] -// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym] -// Why is there a "_NC" at the end? "ELF for the ARM 64-bit architecture -// (AArch64) beta" doesn't have that. -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD32_LO12_NC sym -// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD64_LO12_NC sym + ldr q24, [x23, :tprel_lo12:sym] + ldr q22, [x21, :tprel_lo12_nc:sym] +// CHECK: ldr q24, [x23, :tprel_lo12:sym] +// CHECK: ldr q22, [x21, :tprel_lo12_nc:sym] +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC sym + + ldr w24, [x23, :gottprel_lo12:sym] + ldr s22, [x21, :gottprel_lo12:sym] + + ldr w24, [x23, :tlsdesc_lo12:sym] + ldr s22, [x21, :tlsdesc_lo12:sym] +// CHECK: ldr w24, [x23, :tlsdesc_lo12:sym] +// CHECK: ldr s22, [x21, :tlsdesc_lo12:sym] +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym ldr q20, [x19, #:lo12:sym] // CHECK: ldr q20, [x19, :lo12:sym] -// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST128_ABS_LO12_NC sym +// CHECK-OBJ-ILP32: R_AARCH64_P32_LDST128_ABS_LO12_NC sym // Since relocated instructions print without a '#', that syntax should // certainly be accepted when assembling. Index: test/MC/AArch64/arm32-large-relocs.s =================================================================== --- test/MC/AArch64/arm32-large-relocs.s +++ test/MC/AArch64/arm32-large-relocs.s @@ -0,0 +1,31 @@ +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -show-encoding -o - \ +// RUN: %s \ +// RUN: | FileCheck %s +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -show-encoding \ +// RUN: -filetype=obj -o - %s \ +// RUN: | llvm-objdump -r - \ +// RUN: | FileCheck --check-prefix=CHECK-OBJ %s + + movz x2, #:abs_g0:sym + movk w3, #:abs_g0_nc:sym + movz x13, #:abs_g0_s:sym + movn x17, #:abs_g0_s:sym +// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_aarch64_movw +// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_aarch64_movw +// CHECK: movz x13, #:abs_g0_s:sym // encoding: [0bAAA01101,A,0b100AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw +// CHECK: movn x17, #:abs_g0_s:sym // encoding: [0bAAA10001,A,0b100AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw + +// CHECK-OBJ: 0 R_AARCH64_P32_MOVW_UABS_G0 sym +// CHECK-OBJ: 4 R_AARCH64_P32_MOVW_UABS_G0_NC sym +// CHECK-OBJ: 8 R_AARCH64_P32_MOVW_SABS_G0 sym +// CHECK-OBJ: c R_AARCH64_P32_MOVW_SABS_G0 sym + + movz x4, #:abs_g1:sym +// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_aarch64_movw + +// CHECK-OBJ: 10 R_AARCH64_P32_MOVW_UABS_G1 sym Index: test/MC/AArch64/arm32-tls-relocs.s =================================================================== --- test/MC/AArch64/arm32-tls-relocs.s +++ test/MC/AArch64/arm32-tls-relocs.s @@ -0,0 +1,280 @@ +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-none-linux-gnu \ +// RUN: -show-encoding < %s | FileCheck --check-prefix=CHECK-ILP32 %s +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-none-linux-gnu \ +// RUN: -filetype=obj < %s -o - | \ +// RUN: llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF-ILP32 %s + +//////////////////////////////////////////////////////////////////////////////// +// TLS initial-exec forms +//////////////////////////////////////////////////////////////////////////////// + + adrp x11, :gottprel:var + ldr w10, [x0, #:gottprel_lo12:var] + ldr w9, :gottprel:var +// CHECK-ILP32: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A'] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_pcrel_adrp_imm21 +// CHECK-ILP32: ldr w10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xb9] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK-ILP32: ldr w9, :gottprel:var // encoding: [0bAAA01001,A,A,0x18] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_ldr_pcrel_imm19 + +// CHECK-ELF-ILP32: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM:[^ ]+]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19 [[VARSYM]] + + +//////////////////////////////////////////////////////////////////////////////// +// TLS local-exec forms +//////////////////////////////////////////////////////////////////////////////// + + movz x5, #:tprel_g1:var + movn x6, #:tprel_g1:var + movz w7, #:tprel_g1:var +// CHECK-ILP32: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw +// CHECK-ILP32: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw +// CHECK-ILP32: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw + +// CHECK-ELF-ILP32: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G1 [[VARSYM]] +// CHECK-ELF-ILP32: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G1 [[VARSYM]] +// CHECK-ELF-ILP32: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G1 [[VARSYM]] + + + movz x11, #:tprel_g0:var + movn x12, #:tprel_g0:var + movz w13, #:tprel_g0:var +// CHECK-ILP32: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw +// CHECK-ILP32: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw +// CHECK-ILP32: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G0 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G0 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G0 [[VARSYM]] + + + movk w15, #:tprel_g0_nc:var + movk w16, #:tprel_g0_nc:var +// CHECK-ILP32: movk w15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0x72] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw +// CHECK-ILP32: movk w16, #:tprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] + + + add x21, x22, #:tprel_lo12:var +// CHECK-ILP32: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 [[VARSYM]] + + + add x25, x26, #:tprel_lo12_nc:var +// CHECK-ILP32: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]] + + + ldrb w29, [x30, #:tprel_lo12:var] + ldrsb x29, [x28, #:tprel_lo12_nc:var] +// CHECK-ILP32: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK-ILP32: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]] + + + strh w27, [x26, #:tprel_lo12:var] + ldrsh x25, [x24, #:tprel_lo12_nc:var] +// CHECK-ILP32: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2 +// CHECK-ILP32: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]] + + + ldr w23, [x22, #:tprel_lo12:var] + ldrsw x21, [x20, #:tprel_lo12_nc:var] +// CHECK-ILP32: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK-ILP32: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]] + + ldr x19, [x18, #:tprel_lo12:var] + str x17, [x16, #:tprel_lo12_nc:var] +// CHECK-ILP32: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK-ILP32: str x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]] + + + ldr q24, [x23, :tprel_lo12:var] + str q22, [x21, :tprel_lo12_nc:var] +// CHECK-ILP32: ldr q24, [x23, :tprel_lo12:var] // encoding: [0xf8,0bAAAAAA10,0b11AAAAAA,0x3d] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale16 +// CHECK-ILP32: str q22, [x21, :tprel_lo12_nc:var] // encoding: [0xb6,0bAAAAAA10,0b10AAAAAA,0x3d] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale16 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC [[VARSYM]] + +//////////////////////////////////////////////////////////////////////////////// +// TLS local-dynamic forms +//////////////////////////////////////////////////////////////////////////////// + + movz x5, #:dtprel_g1:var + movn x6, #:dtprel_g1:var + movz w7, #:dtprel_g1:var +// CHECK-ILP32: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw +// CHECK-ILP32: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw +// CHECK-ILP32: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] + + + movz x11, #:dtprel_g0:var + movn x12, #:dtprel_g0:var + movz w13, #:dtprel_g0:var +// CHECK-ILP32: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw +// CHECK-ILP32: movn x12, #:dtprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw +// CHECK-ILP32: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] + + + movk x15, #:dtprel_g0_nc:var + movk w16, #:dtprel_g0_nc:var +// CHECK-ILP32: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw +// CHECK-ILP32: movk w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] + + + add x21, x22, #:dtprel_lo12:var +// CHECK-ILP32: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 [[VARSYM]] + + + add x25, x26, #:dtprel_lo12_nc:var +// CHECK-ILP32: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]] + + + add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12 + add x0, x0, #:tprel_hi12:var_tlsle, lsl #12 + +// CHECK-ELF-ILP32: R_AARCH64_P32_TLSLD_ADD_DTPREL_HI12 var_tlsld +// CHECK-ELF-ILP32: R_AARCH64_P32_TLSLE_ADD_TPREL_HI12 var_tlsle + + + ldrb w29, [x30, #:dtprel_lo12:var] + ldrsb x29, [x28, #:dtprel_lo12_nc:var] +// CHECK-ILP32: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK-ILP32: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]] + + + strh w27, [x26, #:dtprel_lo12:var] + ldrsh x25, [x24, #:dtprel_lo12_nc:var] +// CHECK-ILP32: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2 +// CHECK-ILP32: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]] + + + ldr w23, [x22, #:dtprel_lo12:var] + ldrsw x21, [x20, #:dtprel_lo12_nc:var] +// CHECK-ILP32: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK-ILP32: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]] + + ldr x19, [x18, #:dtprel_lo12:var] + str x17, [x16, #:dtprel_lo12_nc:var] +// CHECK-ILP32: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK-ILP32: str x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8 + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]] + +//////////////////////////////////////////////////////////////////////////////// +// TLS descriptor forms +//////////////////////////////////////////////////////////////////////////////// + + adrp x8, :tlsdesc:var + ldr w7, [x6, #:tlsdesc_lo12:var] + add x5, x4, #:tlsdesc_lo12:var + .tlsdesccall var + blr x3 + +// CHECK-ILP32: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A'] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_aarch64_pcrel_adrp_imm21 +// CHECK-ILP32: ldr w7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xb9] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK-ILP32: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_add_imm12 +// CHECK-ILP32: .tlsdesccall var // encoding: [] +// CHECK-ILP32-NEXT: // fixup A - offset: 0, value: var, kind: fixup_aarch64_tlsdesc_call +// CHECK-ILP32: blr x3 // encoding: [0x60,0x00,0x3f,0xd6] + + +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSDESC_ADR_PAGE21 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSDESC_LD32_LO12 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSDESC_ADD_LO12 [[VARSYM]] +// CHECK-ELF-ILP32-NEXT: {{0x[0-9A-F]+}} R_AARCH64_P32_TLSDESC_CALL [[VARSYM]] + + // Make sure symbol 5 has type STT_TLS: + +// CHECK-ELF-ILP32: Symbols [ +// CHECK-ELF-ILP32: Symbol { +// CHECK-ELF-ILP32: Name: var +// CHECK-ELF-ILP32-NEXT: Value: +// CHECK-ELF-ILP32-NEXT: Size: +// CHECK-ELF-ILP32-NEXT: Binding: Global +// CHECK-ELF-ILP32-NEXT: Type: TLS Index: test/MC/AArch64/arm64-elf-reloc-condbr.s =================================================================== --- test/MC/AArch64/arm64-elf-reloc-condbr.s +++ test/MC/AArch64/arm64-elf-reloc-condbr.s @@ -1,5 +1,8 @@ // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-none-linux-gnu -filetype=obj \ +// RUN: %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ-ILP32 %s b.eq somewhere @@ -8,3 +11,9 @@ // OBJ-NEXT: 0x0 R_AARCH64_CONDBR19 somewhere 0x0 // OBJ-NEXT: } // OBJ-NEXT: ] + +// OBJ-ILP32: Relocations [ +// OBJ-ILP32-NEXT: Section {{.*}} .rela.text { +// OBJ-ILP32-NEXT: 0x0 R_AARCH64_P32_CONDBR19 somewhere 0x0 +// OBJ-ILP32-NEXT: } +// OBJ-ILP32-NEXT: ] Index: test/MC/AArch64/arm64-elf-relocs.s =================================================================== --- test/MC/AArch64/arm64-elf-relocs.s +++ test/MC/AArch64/arm64-elf-relocs.s @@ -25,7 +25,7 @@ add x5, x0, #:tlsdesc_lo12:sym // CHECK: add x5, x0, :tlsdesc_lo12:sym -// CHECK-OBJ-LP64: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym +// CHECK-OBJ-LP64: 14 R_AARCH64_TLSDESC_ADD_LO12 sym add x0, x2, #:lo12:sym+8 // CHECK: add x0, x2, :lo12:sym @@ -49,7 +49,7 @@ add x5, x0, #:tlsdesc_lo12:sym+70 // CHECK: add x5, x0, :tlsdesc_lo12:sym+70 -// CHECK-OBJ-LP64: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70 +// CHECK-OBJ-LP64: 2c R_AARCH64_TLSDESC_ADD_LO12 sym+70 .hword sym + 4 - . // CHECK-OBJ-LP64: 30 R_AARCH64_PREL16 sym+4 @@ -220,6 +220,13 @@ // CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym // CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym + ldr q24, [x23, :dtprel_lo12_nc:sym] + ldr q22, [x21, #:dtprel_lo12:sym] +// CHECK: ldr q24, [x23, :dtprel_lo12_nc:sym] +// CHECK: ldr q22, [x21, :dtprel_lo12:sym] +// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC sym +// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST128_DTPREL_LO12 sym + ldr x24, [x23, #:tprel_lo12:sym] ldr d22, [x21, :tprel_lo12_nc:sym] // CHECK: ldr x24, [x23, :tprel_lo12:sym] @@ -227,6 +234,13 @@ // CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym // CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym + ldr q24, [x23, #:tprel_lo12:sym] + ldr q22, [x21, :tprel_lo12_nc:sym] +// CHECK: ldr q24, [x23, :tprel_lo12:sym] +// CHECK: ldr q22, [x21, :tprel_lo12_nc:sym] +// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST128_TPREL_LO12 sym +// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC sym + ldr x24, [x23, :gottprel_lo12:sym] ldr d22, [x21, #:gottprel_lo12:sym] // CHECK: ldr x24, [x23, :gottprel_lo12:sym] @@ -238,8 +252,8 @@ ldr d22, [x21, :tlsdesc_lo12:sym] // CHECK: ldr x24, [x23, :tlsdesc_lo12:sym] // CHECK: ldr d22, [x21, :tlsdesc_lo12:sym] -// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12_NC sym -// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12_NC sym +// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12 sym +// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12 sym ldr q20, [x19, #:lo12:sym] // CHECK: ldr q20, [x19, :lo12:sym] Index: test/MC/AArch64/arm64-tls-relocs.s =================================================================== --- test/MC/AArch64/arm64-tls-relocs.s +++ test/MC/AArch64/arm64-tls-relocs.s @@ -2,7 +2,6 @@ // RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s -o - | \ // RUN: llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF %s - //////////////////////////////////////////////////////////////////////////////// // TLS initial-exec forms //////////////////////////////////////////////////////////////////////////////// @@ -305,8 +304,8 @@ // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADR_PAGE21 [[VARSYM]] -// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]] -// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADD_LO12_NC [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_LD64_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADD_LO12 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_CALL [[VARSYM]] // Make sure symbol 5 has type STT_TLS: Index: test/MC/AArch64/elf-reloc-ldrlit.s =================================================================== --- test/MC/AArch64/elf-reloc-ldrlit.s +++ test/MC/AArch64/elf-reloc-ldrlit.s @@ -1,5 +1,8 @@ // RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -target-abi=ilp32 -triple=aarch64-none-linux-gnu \ +// RUN: -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ-ILP32 %s ldr x0, some_label ldr w3, some_label @@ -14,3 +17,12 @@ // OBJ-NEXT: 0xC R_AARCH64_LD_PREL_LO19 some_label 0x0 // OBJ-NEXT: } // OBJ-NEXT: ] + +// OBJ-ILP32: Relocations [ +// OBJ-ILP32-NEXT: Section {{.*}} .rela.text { +// OBJ-ILP32-NEXT: 0x0 R_AARCH64_P32_LD_PREL_LO19 some_label 0x0 +// OBJ-ILP32-NEXT: 0x4 R_AARCH64_P32_LD_PREL_LO19 some_label 0x0 +// OBJ-ILP32-NEXT: 0x8 R_AARCH64_P32_LD_PREL_LO19 some_label 0x0 +// OBJ-ILP32-NEXT: 0xC R_AARCH64_P32_LD_PREL_LO19 some_label 0x0 +// OBJ-ILP32-NEXT: } +// OBJ-ILP32-NEXT: ] Index: test/MC/AArch64/elf-reloc-pcreladdressing-ilp32.s =================================================================== --- test/MC/AArch64/elf-reloc-pcreladdressing-ilp32.s +++ test/MC/AArch64/elf-reloc-pcreladdressing-ilp32.s @@ -0,0 +1,17 @@ +// RUN: llvm-mc -target-abi=ilp32 -triple=aarch64-none-linux-gnu \ +// RUN: -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ-ILP32 %s + adr x2, some_label + adrp x5, some_label + + adrp x5, :got:some_label + ldr w0, [x5, #:got_lo12:some_label] + +// OBJ-ILP32: Relocations [ +// OBJ-ILP32-NEXT: Section {{.*}} .rela.text { +// OBJ-ILP32-NEXT: 0x0 R_AARCH64_P32_ADR_PREL_LO21 some_label 0x0 +// OBJ-ILP32-NEXT: 0x4 R_AARCH64_P32_ADR_PREL_PG_HI21 some_label 0x0 +// OBJ-ILP32-NEXT: 0x8 R_AARCH64_P32_ADR_GOT_PAGE some_label 0x0 +// OBJ-ILP32-NEXT: 0xC R_AARCH64_P32_LD32_GOT_LO12_NC some_label 0x0 +// OBJ-ILP32-NEXT: } +// OBJ-ILP32-NEXT: ] Index: test/MC/AArch64/elf-reloc-tstb.s =================================================================== --- test/MC/AArch64/elf-reloc-tstb.s +++ test/MC/AArch64/elf-reloc-tstb.s @@ -1,5 +1,8 @@ // RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -target-abi=ilp32 -triple=aarch64-none-linux-gnu \ +// RUN: -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ-ILP32 %s tbz x6, #45, somewhere tbnz w3, #15, somewhere @@ -10,3 +13,10 @@ // OBJ-NEXT: 0x4 R_AARCH64_TSTBR14 somewhere 0x0 // OBJ-NEXT: } // OBJ-NEXT: ] + +// OBJ-ILP32: Relocations [ +// OBJ-ILP32-NEXT: Section {{.*}} .rela.text { +// OBJ-ILP32-NEXT: 0x0 R_AARCH64_P32_TSTBR14 somewhere 0x0 +// OBJ-ILP32-NEXT: 0x4 R_AARCH64_P32_TSTBR14 somewhere 0x0 +// OBJ-ILP32-NEXT: } +// OBJ-ILP32-NEXT: ] Index: test/MC/AArch64/elf-reloc-uncondbrimm.s =================================================================== --- test/MC/AArch64/elf-reloc-uncondbrimm.s +++ test/MC/AArch64/elf-reloc-uncondbrimm.s @@ -1,5 +1,8 @@ // RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -target-abi=ilp32 -triple=aarch64-none-linux-gnu \ +// RUN: -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ-ILP32 %s b somewhere bl somewhere @@ -10,3 +13,10 @@ // OBJ-NEXT: 0x4 R_AARCH64_CALL26 somewhere 0x0 // OBJ-NEXT: } // OBJ-NEXT: ] + +// OBJ-ILP32: Relocations [ +// OBJ-ILP32-NEXT: Section {{.*}} .rela.text { +// OBJ-ILP32-NEXT: 0x0 R_AARCH64_P32_JUMP26 somewhere 0x0 +// OBJ-ILP32-NEXT: 0x4 R_AARCH64_P32_CALL26 somewhere 0x0 +// OBJ-ILP32-NEXT: } +// OBJ-ILP32-NEXT: ] Index: test/MC/AArch64/error-location.s =================================================================== --- test/MC/AArch64/error-location.s +++ test/MC/AArch64/error-location.s @@ -31,7 +31,7 @@ // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid fixup for 16-bit load/store instruction ldrh w0, [x1, :gottprel_lo12:undef] -// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid fixup for 32-bit load/store instruction +// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: LP64 32-bit load/store relocation not supported (ILP32 eqv: TLSIE_LD32_GOTTPREL_LO12_NC) ldr w0, [x1, :gottprel_lo12:undef] Index: test/MC/AArch64/ilp32-diagnostics.s =================================================================== --- test/MC/AArch64/ilp32-diagnostics.s +++ test/MC/AArch64/ilp32-diagnostics.s @@ -1,11 +1,15 @@ // RUN: not llvm-mc -triple aarch64-none-linux-gnu -target-abi=ilp32 \ -// RUN: < %s 2> %t2 -filetype=obj +// RUN: < %s 2> %t2 -filetype=obj >/dev/null // RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t2 .xword sym-. // CHECK-ERROR: error: ILP32 8 byte PC relative data relocation not supported (LP64 eqv: PREL64) // CHECK-ERROR: ^ + .xword sym+16 +// CHECK-ERROR: error: ILP32 8 byte absolute data relocation not supported (LP64 eqv: ABS64) +// CHECK-ERROR: ^ + movz x7, #:abs_g3:some_label // CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_UABS_G3) // CHECK-ERROR: movz x7, #:abs_g3:some_label @@ -65,3 +69,29 @@ // CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSIE_MOVW_GOTTPREL_G0_NC) // CHECK-ERROR: movk x13, #:gottprel_g0_nc:var // CHECK-ERROR: ^ + + ldr x10, [x0, #:gottprel_lo12:var] +// CHECK-ERROR: error: ILP32 64-bit load/store relocation not supported (LP64 eqv: TLSIE_LD64_GOTTPREL_LO12_NC) +// CHECK-ERROR: ldr x10, [x0, #:gottprel_lo12:var] +// CHECK-ERROR: ^ + + ldr x24, [x23, #:got_lo12:sym] +// CHECK-ERROR: error: ILP32 64-bit load/store relocation not supported (LP64 eqv: LD64_GOT_LO12_NC) +// CHECK-ERROR: ^ + + ldr x24, [x23, :gottprel_lo12:sym] +// CHECK-ERROR: error: ILP32 64-bit load/store relocation not supported (LP64 eqv: TLSIE_LD64_GOTTPREL_LO12_NC) +// CHECK-ERROR: ^ + + ldr x10, [x0, #:gottprel_lo12:var] +// CHECK-ERROR: error: ILP32 64-bit load/store relocation not supported (LP64 eqv: TLSIE_LD64_GOTTPREL_LO12_NC) +// CHECK-ERROR: ldr x10, [x0, #:gottprel_lo12:var] +// CHECK-ERROR: ^ + + ldr x24, [x23, #:got_lo12:sym] +// CHECK-ERROR: error: ILP32 64-bit load/store relocation not supported (LP64 eqv: LD64_GOT_LO12_NC) +// CHECK-ERROR: ^ + + ldr x24, [x23, :gottprel_lo12:sym] +// CHECK-ERROR: error: ILP32 64-bit load/store relocation not supported (LP64 eqv: TLSIE_LD64_GOTTPREL_LO12_NC) +// CHECK-ERROR: ^ Index: test/MC/AArch64/inline-asm-modifiers.s =================================================================== --- test/MC/AArch64/inline-asm-modifiers.s +++ test/MC/AArch64/inline-asm-modifiers.s @@ -30,7 +30,7 @@ // CHECK: R_AARCH64_ADD_ABS_LO12_NC var_simple // CHECK: R_AARCH64_LD64_GOT_LO12_NC var_got -// CHECK: R_AARCH64_TLSDESC_ADD_LO12_NC var_tlsgd +// CHECK: R_AARCH64_TLSDESC_ADD_LO12 var_tlsgd // CHECK: R_AARCH64_TLSLD_ADD_DTPREL_LO12 var_tlsld // CHECK: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC var_tlsie // CHECK: R_AARCH64_TLSLE_ADD_TPREL_LO12 var_tlsle Index: test/MC/AArch64/lp64-diagnostics.s =================================================================== --- test/MC/AArch64/lp64-diagnostics.s +++ test/MC/AArch64/lp64-diagnostics.s @@ -0,0 +1,13 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t2 -filetype=obj \ +// RUN: >/dev/null +// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t2 + + ldr w24, [x23, :tlsdesc_lo12:sym] + ldr s22, [x21, :tlsdesc_lo12:sym] + +// CHECK-ERROR: error: LP64 4 byte TLSDESC load/store relocation not supported (ILP32 eqv: TLSDESC_LD64_LO12) +// CHECK-ERROR: ldr w24, [x23, :tlsdesc_lo12:sym] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: LP64 4 byte TLSDESC load/store relocation not supported (ILP32 eqv: TLSDESC_LD64_LO12) +// CHECK-ERROR: ldr s22, [x21, :tlsdesc_lo12:sym] +// CHECK-ERROR: ^ Index: test/MC/AArch64/tls-relocs.s =================================================================== --- test/MC/AArch64/tls-relocs.s +++ test/MC/AArch64/tls-relocs.s @@ -392,8 +392,8 @@ // CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6] // CHECK-ELF-NEXT: 0x104 R_AARCH64_TLSDESC_ADR_PAGE21 [[VARSYM]] -// CHECK-ELF-NEXT: 0x108 R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]] -// CHECK-ELF-NEXT: 0x10C R_AARCH64_TLSDESC_ADD_LO12_NC [[VARSYM]] +// CHECK-ELF-NEXT: 0x108 R_AARCH64_TLSDESC_LD64_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: 0x10C R_AARCH64_TLSDESC_ADD_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x110 R_AARCH64_TLSDESC_CALL [[VARSYM]] Index: test/tools/llvm-readobj/reloc-types.test =================================================================== --- test/tools/llvm-readobj/reloc-types.test +++ test/tools/llvm-readobj/reloc-types.test @@ -253,8 +253,8 @@ ELF-AARCH64: Type: R_AARCH64_TLSDESC_LD_PREL19 (560) ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADR_PREL21 (561) ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADR_PAGE21 (562) -ELF-AARCH64: Type: R_AARCH64_TLSDESC_LD64_LO12_NC (563) -ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADD_LO12_NC (564) +ELF-AARCH64: Type: R_AARCH64_TLSDESC_LD64_LO12 (563) +ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADD_LO12 (564) ELF-AARCH64: Type: R_AARCH64_TLSDESC_OFF_G1 (565) ELF-AARCH64: Type: R_AARCH64_TLSDESC_OFF_G0_NC (566) ELF-AARCH64: Type: R_AARCH64_TLSDESC_LDR (567)