Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -848,6 +848,31 @@
     }
     break;
   }
+  case ISD::BUILD_PAIR: {
+    EVT HalfVT = Op.getOperand(0).getValueType();
+    unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
+
+    APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
+    APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
+
+    APInt KnownZeroLo, KnownOneLo;
+    APInt KnownZeroHi, KnownOneHi;
+
+    if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
+                             KnownOneLo, TLO, Depth + 1))
+      return true;
+
+    if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
+                             KnownOneHi, TLO, Depth + 1))
+      return true;
+
+    KnownZero = KnownZeroLo.zext(BitWidth) |
+                KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
+
+    KnownOne = KnownOneLo.zext(BitWidth) |
+               KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
+    break;
+  }
   case ISD::ZERO_EXTEND: {
     unsigned OperandBitWidth =
       Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Index: test/CodeGen/R600/simplify-demanded-bits-build-pair.ll
===================================================================
--- /dev/null
+++ test/CodeGen/R600/simplify-demanded-bits-build-pair.ll
@@ -0,0 +1,81 @@
+; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+
+; SI-LABEL: @trunc_select_i64
+; SI: V_CNDMASK_B32
+; SI-NOT: V_CNDMASK_B32
+; SI: S_ENDPGM
+define void @trunc_select_i64(i32 addrspace(1)* %out, i64 %a, i64 %b, i32 %c) {
+  %cmp = icmp eq i32 %c, 0
+  %select = select i1 %cmp, i64 %a, i64 %b
+  %trunc = trunc i64 %select to i32
+  store i32 %trunc, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; SI-LABEL: @select_ashr_trunc_hi_i64
+; SI: V_CNDMASK_B32
+; SI-NOT: V_CNDMASK_B32
+; SI: S_ENDPGM
+define void @select_ashr_trunc_hi_i64(i32 addrspace(1)* %out, i64 %a, i64 %b, i32 %c) {
+  %cmp = icmp eq i32 %c, 0
+  %select = select i1 %cmp, i64 %a, i64 %b
+  %shr = ashr i64 %select, 32
+  %trunc = trunc i64 %shr to i32
+  store i32 %trunc, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; SI-LABEL: @select_lshr_trunc_hi_i64
+; SI: V_CNDMASK_B32
+; SI-NOT: V_CNDMASK_B32
+; SI: S_ENDPGM
+define void @select_lshr_trunc_hi_i64(i32 addrspace(1)* %out, i64 %a, i64 %b, i32 %c) {
+  %cmp = icmp eq i32 %c, 0
+  %select = select i1 %cmp, i64 %a, i64 %b
+  %shr = lshr i64 %select, 32
+  %trunc = trunc i64 %shr to i32
+  store i32 %trunc, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; SI-LABEL: @select_ashr_hi_i64
+; SI: V_CNDMASK_B32
+; SI-NOT: V_CNDMASK_B32
+; SI: S_ENDPGM
+define void @select_ashr_hi_i64(i64 addrspace(1)* %out, i64 %a, i64 %b, i32 %c) {
+  %cmp = icmp eq i32 %c, 0
+  %select = select i1 %cmp, i64 %a, i64 %b
+  %shr = ashr i64 %select, 32
+  %shl = shl i64 %shr, 32
+  store i64 %shl, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; SI-LABEL: @select_lshr_hi_i64
+; SI: V_CNDMASK_B32
+; SI-NOT: V_CNDMASK_B32
+; SI: S_ENDPGM
+define void @select_lshr_hi_i64(i64 addrspace(1)* %out, i64 %a, i64 %b, i32 %c) {
+  %cmp = icmp eq i32 %c, 0
+  %select = select i1 %cmp, i64 %a, i64 %b
+  %shr = lshr i64 %select, 32
+  %shl = shl i64 %shr, 32
+  store i64 %shl, i64 addrspace(1)* %out, align 8
+  ret void
+}
+
+; SI-LABEL: @trunc_select_select_i64
+; SI: V_CNDMASK_B32
+; SI: V_CNDMASK_B32
+; SI-NOT: V_CNDMASK_B32
+; SI-NOT: V_CNDMASK_B32
+; SI: S_ENDPGM
+define void @trunc_select_select_i64(i32 addrspace(1)* %out, i64 %a, i64 %b, i32 %c, i32 %d) {
+  %cmp0 = icmp eq i32 %c, 0
+  %select0 = select i1 %cmp0, i64 %a, i64 0
+  %cmp1 = icmp eq i32 %d, 0
+  %select1 = select i1 %cmp1, i64 %select0, i64 %b
+  %trunc = trunc i64 %select1 to i32
+  store i32 %trunc, i32 addrspace(1)* %out, align 4
+  ret void
+}