Index: lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp =================================================================== --- lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -104,7 +104,7 @@ static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, @@ -113,13 +113,13 @@ static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeHvxVPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, @@ -480,10 +480,10 @@ return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); } -static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { - static const MCPhysReg VecRegDecoderTable[] = { +static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const void *Decoder) { + static const MCPhysReg HvxVRDecoderTable[] = { Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, @@ -492,7 +492,7 @@ Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V30, Hexagon::V31}; - return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable); + return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); } static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, @@ -516,16 +516,16 @@ return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); } -static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { - static const MCPhysReg VecDblRegDecoderTable[] = { +static DecodeStatus DecodeHvxVPRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const void *Decoder) { + static const MCPhysReg HvxVPDecoderTable[] = { Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; - return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable)); + return (DecodeRegisterClass(Inst, RegNo >> 1, HvxVPDecoderTable)); } static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, @@ -537,13 +537,13 @@ return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); } -static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { - static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, - Hexagon::Q2, Hexagon::Q3}; +static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const void *Decoder) { + static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, + Hexagon::Q2, Hexagon::Q3}; - return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable); + return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); } static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, Index: lib/Target/Hexagon/Hexagon.td =================================================================== --- lib/Target/Hexagon/Hexagon.td +++ lib/Target/Hexagon/Hexagon.td @@ -44,6 +44,9 @@ def UseHVX : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">, AssemblerPredicate<"ExtensionHVX">; +def Hvx64 : HwMode<"+hvx,-hvx-double">; +def Hvx128 : HwMode<"+hvx,+hvx-double">; + //===----------------------------------------------------------------------===// // Classes used for relation maps. //===----------------------------------------------------------------------===// Index: lib/Target/Hexagon/HexagonAsmPrinter.cpp =================================================================== --- lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -285,10 +285,8 @@ MCInst &MappedInst = static_cast (Inst); const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo(); const MachineFunction &MF = *MI.getParent()->getParent(); - const auto &HST = MF.getSubtarget(); - const auto &VecRC = HST.useHVXSglOps() ? Hexagon::VectorRegsRegClass - : Hexagon::VectorRegs128BRegClass; - unsigned VectorSize = HST.getRegisterInfo()->getSpillSize(VecRC); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); + unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; switch (Inst.getOpcode()) { default: return; @@ -607,8 +605,7 @@ Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); return; } - case Hexagon::V6_vd0: - case Hexagon::V6_vd0_128B: { + case Hexagon::V6_vd0: { MCInst TmpInst; assert (Inst.getOperand(0).isReg() && "Expected register and none was found"); @@ -628,13 +625,6 @@ case Hexagon::V6_vL32b_nt_pi: case Hexagon::V6_vL32b_nt_tmp_pi: case Hexagon::V6_vL32b_tmp_pi: - case Hexagon::V6_vL32Ub_pi_128B: - case Hexagon::V6_vL32b_cur_pi_128B: - case Hexagon::V6_vL32b_nt_cur_pi_128B: - case Hexagon::V6_vL32b_pi_128B: - case Hexagon::V6_vL32b_nt_pi_128B: - case Hexagon::V6_vL32b_nt_tmp_pi_128B: - case Hexagon::V6_vL32b_tmp_pi_128B: MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); return; @@ -645,13 +635,6 @@ case Hexagon::V6_vL32b_nt_cur_ai: case Hexagon::V6_vL32b_nt_tmp_ai: case Hexagon::V6_vL32b_tmp_ai: - case Hexagon::V6_vL32Ub_ai_128B: - case Hexagon::V6_vL32b_ai_128B: - case Hexagon::V6_vL32b_cur_ai_128B: - case Hexagon::V6_vL32b_nt_ai_128B: - case Hexagon::V6_vL32b_nt_cur_ai_128B: - case Hexagon::V6_vL32b_nt_tmp_ai_128B: - case Hexagon::V6_vL32b_tmp_ai_128B: MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); return; @@ -660,11 +643,6 @@ case Hexagon::V6_vS32b_nt_new_pi: case Hexagon::V6_vS32b_nt_pi: case Hexagon::V6_vS32b_pi: - case Hexagon::V6_vS32Ub_pi_128B: - case Hexagon::V6_vS32b_new_pi_128B: - case Hexagon::V6_vS32b_nt_new_pi_128B: - case Hexagon::V6_vS32b_nt_pi_128B: - case Hexagon::V6_vS32b_pi_128B: MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); return; @@ -673,11 +651,6 @@ case Hexagon::V6_vS32b_new_ai: case Hexagon::V6_vS32b_nt_ai: case Hexagon::V6_vS32b_nt_new_ai: - case Hexagon::V6_vS32Ub_ai_128B: - case Hexagon::V6_vS32b_ai_128B: - case Hexagon::V6_vS32b_new_ai_128B: - case Hexagon::V6_vS32b_nt_ai_128B: - case Hexagon::V6_vS32b_nt_new_ai_128B: MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext); return; @@ -693,18 +666,6 @@ case Hexagon::V6_vL32b_pred_pi: case Hexagon::V6_vL32b_tmp_npred_pi: case Hexagon::V6_vL32b_tmp_pred_pi: - case Hexagon::V6_vL32b_cur_npred_pi_128B: - case Hexagon::V6_vL32b_cur_pred_pi_128B: - case Hexagon::V6_vL32b_npred_pi_128B: - case Hexagon::V6_vL32b_nt_cur_npred_pi_128B: - case Hexagon::V6_vL32b_nt_cur_pred_pi_128B: - case Hexagon::V6_vL32b_nt_npred_pi_128B: - case Hexagon::V6_vL32b_nt_pred_pi_128B: - case Hexagon::V6_vL32b_nt_tmp_npred_pi_128B: - case Hexagon::V6_vL32b_nt_tmp_pred_pi_128B: - case Hexagon::V6_vL32b_pred_pi_128B: - case Hexagon::V6_vL32b_tmp_npred_pi_128B: - case Hexagon::V6_vL32b_tmp_pred_pi_128B: MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext); return; @@ -720,18 +681,6 @@ case Hexagon::V6_vL32b_pred_ai: case Hexagon::V6_vL32b_tmp_npred_ai: case Hexagon::V6_vL32b_tmp_pred_ai: - case Hexagon::V6_vL32b_cur_npred_ai_128B: - case Hexagon::V6_vL32b_cur_pred_ai_128B: - case Hexagon::V6_vL32b_npred_ai_128B: - case Hexagon::V6_vL32b_nt_cur_npred_ai_128B: - case Hexagon::V6_vL32b_nt_cur_pred_ai_128B: - case Hexagon::V6_vL32b_nt_npred_ai_128B: - case Hexagon::V6_vL32b_nt_pred_ai_128B: - case Hexagon::V6_vL32b_nt_tmp_npred_ai_128B: - case Hexagon::V6_vL32b_nt_tmp_pred_ai_128B: - case Hexagon::V6_vL32b_pred_ai_128B: - case Hexagon::V6_vL32b_tmp_npred_ai_128B: - case Hexagon::V6_vL32b_tmp_pred_ai_128B: MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); return; @@ -749,20 +698,6 @@ case Hexagon::V6_vS32b_nt_qpred_pi: case Hexagon::V6_vS32b_pred_pi: case Hexagon::V6_vS32b_qpred_pi: - case Hexagon::V6_vS32Ub_npred_pi_128B: - case Hexagon::V6_vS32Ub_pred_pi_128B: - case Hexagon::V6_vS32b_new_npred_pi_128B: - case Hexagon::V6_vS32b_new_pred_pi_128B: - case Hexagon::V6_vS32b_npred_pi_128B: - case Hexagon::V6_vS32b_nqpred_pi_128B: - case Hexagon::V6_vS32b_nt_new_npred_pi_128B: - case Hexagon::V6_vS32b_nt_new_pred_pi_128B: - case Hexagon::V6_vS32b_nt_npred_pi_128B: - case Hexagon::V6_vS32b_nt_nqpred_pi_128B: - case Hexagon::V6_vS32b_nt_pred_pi_128B: - case Hexagon::V6_vS32b_nt_qpred_pi_128B: - case Hexagon::V6_vS32b_pred_pi_128B: - case Hexagon::V6_vS32b_qpred_pi_128B: MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); return; @@ -780,20 +715,6 @@ case Hexagon::V6_vS32b_nt_qpred_ai: case Hexagon::V6_vS32b_pred_ai: case Hexagon::V6_vS32b_qpred_ai: - case Hexagon::V6_vS32Ub_npred_ai_128B: - case Hexagon::V6_vS32Ub_pred_ai_128B: - case Hexagon::V6_vS32b_new_npred_ai_128B: - case Hexagon::V6_vS32b_new_pred_ai_128B: - case Hexagon::V6_vS32b_npred_ai_128B: - case Hexagon::V6_vS32b_nqpred_ai_128B: - case Hexagon::V6_vS32b_nt_new_npred_ai_128B: - case Hexagon::V6_vS32b_nt_new_pred_ai_128B: - case Hexagon::V6_vS32b_nt_npred_ai_128B: - case Hexagon::V6_vS32b_nt_nqpred_ai_128B: - case Hexagon::V6_vS32b_nt_pred_ai_128B: - case Hexagon::V6_vS32b_nt_qpred_ai_128B: - case Hexagon::V6_vS32b_pred_ai_128B: - case Hexagon::V6_vS32b_qpred_ai_128B: MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); return; } Index: lib/Target/Hexagon/HexagonBitSimplify.cpp =================================================================== --- lib/Target/Hexagon/HexagonBitSimplify.cpp +++ lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -415,8 +415,7 @@ switch (RC->getID()) { case Hexagon::DoubleRegsRegClassID: - case Hexagon::VecDblRegsRegClassID: - case Hexagon::VecDblRegs128BRegClassID: + case Hexagon::HvxVPRegClassID: Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 2; if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi) Begin = Width; @@ -913,12 +912,9 @@ case Hexagon::DoubleRegsRegClassID: VerifySR(RC, RR.Sub); return &Hexagon::IntRegsRegClass; - case Hexagon::VecDblRegsRegClassID: + case Hexagon::HvxVPRegClassID: VerifySR(RC, RR.Sub); - return &Hexagon::VectorRegsRegClass; - case Hexagon::VecDblRegs128BRegClassID: - VerifySR(RC, RR.Sub); - return &Hexagon::VectorRegs128BRegClass; + return &Hexagon::HvxVRRegClass; } return nullptr; } @@ -1622,8 +1618,7 @@ } if (FRC == &Hexagon::DoubleRegsRegClass || - FRC == &Hexagon::VecDblRegsRegClass || - FRC == &Hexagon::VecDblRegs128BRegClass) { + FRC == &Hexagon::HvxVPRegClass) { // Try to generate REG_SEQUENCE. unsigned SubLo = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_lo); unsigned SubHi = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_hi); @@ -1660,7 +1655,6 @@ case Hexagon::A2_tfrp: case Hexagon::A2_combinew: case Hexagon::V6_vcombine: - case Hexagon::V6_vcombine_128B: return NoConv; default: break; @@ -1699,8 +1693,7 @@ break; } case Hexagon::A2_combinew: - case Hexagon::V6_vcombine: - case Hexagon::V6_vcombine_128B: { + case Hexagon::V6_vcombine: { const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg); unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo); unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); Index: lib/Target/Hexagon/HexagonBitTracker.cpp =================================================================== --- lib/Target/Hexagon/HexagonBitTracker.cpp +++ lib/Target/Hexagon/HexagonBitTracker.cpp @@ -102,8 +102,7 @@ bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); switch (ID) { case DoubleRegsRegClassID: - case VecDblRegsRegClassID: - case VecDblRegs128BRegClassID: + case HvxVPRegClassID: return IsSubLo ? BT::BitMask(0, RW-1) : BT::BitMask(RW, 2*RW-1); default: @@ -703,7 +702,6 @@ case A4_combineri: case A2_combinew: case V6_vcombine: - case V6_vcombine_128B: assert(W0 % 2 == 0); return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs); case A2_combine_ll: Index: lib/Target/Hexagon/HexagonCopyToCombine.cpp =================================================================== --- lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -161,7 +161,6 @@ } case Hexagon::V6_vassign: - case Hexagon::V6_vassign_128B: return true; default: @@ -231,8 +230,7 @@ assert(TargetRegisterInfo::isPhysicalRegister(Reg)); if (Hexagon::IntRegsRegClass.contains(Reg)) return (Reg - Hexagon::R0) % 2 == 0; - if (Hexagon::VectorRegsRegClass.contains(Reg) || - Hexagon::VectorRegs128BRegClass.contains(Reg)) + if (Hexagon::HvxVRRegClass.contains(Reg)) return (Reg - Hexagon::V0) % 2 == 0; llvm_unreachable("Invalid register"); } @@ -590,12 +588,9 @@ if (Hexagon::IntRegsRegClass.contains(LoRegDef)) { SuperRC = &Hexagon::DoubleRegsRegClass; SubLo = Hexagon::isub_lo; - } else if (Hexagon::VectorRegsRegClass.contains(LoRegDef)) { + } else if (Hexagon::HvxVRRegClass.contains(LoRegDef)) { assert(ST->useHVXOps()); - if (ST->useHVXSglOps()) - SuperRC = &Hexagon::VecDblRegsRegClass; - else - SuperRC = &Hexagon::VecDblRegs128BRegClass; + SuperRC = &Hexagon::HvxVPRegClass; SubLo = Hexagon::vsub_lo; } else llvm_unreachable("Unexpected register class"); @@ -872,12 +867,9 @@ unsigned NewOpc; if (Hexagon::DoubleRegsRegClass.contains(DoubleDestReg)) { NewOpc = Hexagon::A2_combinew; - } else if (Hexagon::VecDblRegsRegClass.contains(DoubleDestReg)) { + } else if (Hexagon::HvxVPRegClass.contains(DoubleDestReg)) { assert(ST->useHVXOps()); - if (ST->useHVXSglOps()) - NewOpc = Hexagon::V6_vcombine; - else - NewOpc = Hexagon::V6_vcombine_128B; + NewOpc = Hexagon::V6_vcombine; } else llvm_unreachable("Unexpected register"); Index: lib/Target/Hexagon/HexagonDepInstrFormats.td =================================================================== --- lib/Target/Hexagon/HexagonDepInstrFormats.td +++ lib/Target/Hexagon/HexagonDepInstrFormats.td @@ -27,16 +27,6 @@ bits <5> Vw32; let Inst{4-0} = Vw32{4-0}; } -class Enc_13397056 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Qv4; - let Inst{12-11} = Qv4{1-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} class Enc_7315939 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -307,17 +297,6 @@ bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_738356 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} class Enc_14400220 : OpcodeHexagon { bits <5> Ii; let Inst{9-5} = Ii{4-0}; @@ -989,17 +968,6 @@ bits <5> Vx32; let Inst{7-3} = Vx32{4-0}; } -class Enc_13937564 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; -} class Enc_7171569 : OpcodeHexagon { bits <3> Ii; let Inst{7-5} = Ii{2-0}; @@ -1176,16 +1144,6 @@ bits <5> Rxx32; let Inst{4-0} = Rxx32{4-0}; } -class Enc_15560488 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} class Enc_7581852 : OpcodeHexagon { bits <2> Ii; let Inst{13-13} = Ii{1-1}; @@ -1317,15 +1275,6 @@ bits <5> Vu32; let Inst{20-16} = Vu32{4-0}; } -class Enc_5757366 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; -} class Enc_9752128 : OpcodeHexagon { bits <7> Ii; let Inst{8-5} = Ii{6-3}; @@ -1377,15 +1326,6 @@ bits <5> Rxx32; let Inst{12-8} = Rxx32{4-0}; } -class Enc_2152247 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; -} class Enc_12848507 : OpcodeHexagon { bits <2> Ii; let Inst{13-13} = Ii{1-1}; @@ -1959,14 +1899,6 @@ bits <5> Rtt32; let Inst{12-8} = Rtt32{4-0}; } -class Enc_2296022 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} class Enc_9664427 : OpcodeHexagon { bits <5> Vuu32; let Inst{20-16} = Vuu32{4-0}; @@ -2199,15 +2131,6 @@ bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_8437395 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} class Enc_16578332 : OpcodeHexagon { bits <9> Ii; let Inst{10-8} = Ii{8-6}; @@ -2251,14 +2174,6 @@ bits <4> Rd16; let Inst{3-0} = Rd16{3-0}; } -class Enc_11039423 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} class Enc_6730375 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -2538,17 +2453,6 @@ bits <5> Vss32; let Inst{7-3} = Vss32{4-0}; } -class Enc_9470751 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; -} class Enc_2683366 : OpcodeHexagon { bits <3> Quu8; let Inst{10-8} = Quu8{2-0}; @@ -3102,17 +3006,6 @@ bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } -class Enc_2703240 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Qv4; - let Inst{12-11} = Qv4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; -} class Enc_6975103 : OpcodeHexagon { bits <2> Ps4; let Inst{17-16} = Ps4{1-0}; @@ -3831,14 +3724,6 @@ bits <8> Ii; let Inst{8-4} = Ii{7-3}; } -class Enc_11244923 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} class Enc_8612939 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -3879,16 +3764,6 @@ let Inst{24-22} = n1{3-1}; let Inst{8-8} = n1{0-0}; } -class Enc_14459927 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} class Enc_7504828 : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; @@ -4079,16 +3954,6 @@ bits <5> Rt32; let Inst{4-0} = Rt32{4-0}; } -class Enc_2735552 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} class Enc_16410950 : OpcodeHexagon { bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; Index: lib/Target/Hexagon/HexagonDepInstrInfo.td =================================================================== --- lib/Target/Hexagon/HexagonDepInstrInfo.td +++ lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -25456,8 +25456,8 @@ let DecoderNamespace = "SUBINSN_S2"; } def V6_MAP_equb : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25466,33 +25466,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_MAP_equb_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_MAP_equb_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_MAP_equb_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25500,25 +25476,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_MAP_equb_ior : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_MAP_equb_ior_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25527,24 +25489,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_MAP_equb_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_MAP_equb_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25552,23 +25501,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_MAP_equh : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_MAP_equh_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25576,23 +25513,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_MAP_equh_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_MAP_equh_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25600,25 +25524,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_MAP_equh_ior : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_MAP_equh_ior_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25627,24 +25537,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_MAP_equh_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_MAP_equh_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25652,12 +25549,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_MAP_equw : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25666,33 +25562,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_MAP_equw_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_MAP_equw_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_MAP_equw_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25700,25 +25572,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_MAP_equw_ior : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_MAP_equw_ior_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25727,24 +25585,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_MAP_equw_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_MAP_equw_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25752,26 +25597,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_extractw : HInst< (outs IntRegs:$Rd32), -(ins VectorRegs:$Vu32, IntRegs:$Rs32), -"$Rd32 = vextract($Vu32,$Rs32)", -LD_tc_ld_SLOT0, TypeLD>, Enc_16601956, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b10010010000; -let hasNewValue = 1; -let opNewValue = 0; -let isSolo = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_extractw_128B : HInst< -(outs IntRegs:$Rd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rs32), +(ins HvxVR:$Vu32, IntRegs:$Rs32), "$Rd32 = vextract($Vu32,$Rs32)", LD_tc_ld_SLOT0, TypeLD>, Enc_16601956, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -25782,22 +25612,10 @@ let isSolo = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_extractw_alt : HInst< (outs IntRegs:$Rd32), -(ins VectorRegs:$Vu32, IntRegs:$Rs32), -"$Rd32.w = vextract($Vu32,$Rs32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_extractw_alt_128B : HInst< -(outs IntRegs:$Rd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rs32), +(ins HvxVR:$Vu32, IntRegs:$Rs32), "$Rd32.w = vextract($Vu32,$Rs32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -25805,42 +25623,19 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_hi : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vss32), -"$Vd32 = hi($Vss32)", -CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_hi_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vss32), +(outs HvxVR:$Vd32), +(ins HvxVP:$Vss32), "$Vd32 = hi($Vss32)", CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_ld0 : HInst< -(outs VectorRegs:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32 = vmem($Rt32)", -PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_ld0_128B : HInst< -(outs VectorRegs128B:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vmem($Rt32)", PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { @@ -25849,21 +25644,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_ldnt0 : HInst< -(outs VectorRegs:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32 = vmem($Rt32):nt", -PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_ldnt0_128B : HInst< -(outs VectorRegs128B:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vmem($Rt32):nt", PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { @@ -25872,21 +25655,9 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_ldu0 : HInst< -(outs VectorRegs:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32 = vmemu($Rt32)", -PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_ldu0_128B : HInst< -(outs VectorRegs128B:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vmemu($Rt32)", PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { @@ -25895,42 +25666,19 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_lo : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vss32), -"$Vd32 = lo($Vss32)", -CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_lo_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vss32), +(outs HvxVR:$Vd32), +(ins HvxVP:$Vss32), "$Vd32 = lo($Vss32)", CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_lvsplatb : HInst< -(outs VectorRegs:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32.b = vsplat($Rt32)", -CVI_VX, TypeCVI_VX>, Enc_9768377, Requires<[HasV62T,UseHVX]> { -let Inst{13-5} = 0b000000010; -let Inst{31-21} = 0b00011001110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_lvsplatb_128B : HInst< -(outs VectorRegs128B:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32.b = vsplat($Rt32)", CVI_VX, TypeCVI_VX>, Enc_9768377, Requires<[HasV62T,UseHVX]> { @@ -25939,21 +25687,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_lvsplath : HInst< -(outs VectorRegs:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32.h = vsplat($Rt32)", -CVI_VX, TypeCVI_VX>, Enc_9768377, Requires<[HasV62T,UseHVX]> { -let Inst{13-5} = 0b000000001; -let Inst{31-21} = 0b00011001110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_lvsplath_128B : HInst< -(outs VectorRegs128B:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32.h = vsplat($Rt32)", CVI_VX, TypeCVI_VX>, Enc_9768377, Requires<[HasV62T,UseHVX]> { @@ -25962,21 +25698,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_lvsplatw : HInst< -(outs VectorRegs:$Vd32), -(ins IntRegs:$Rt32), -"$Vd32 = vsplat($Rt32)", -CVI_VX_LATE, TypeCVI_VX>, Enc_9768377, Requires<[HasV60T,UseHVX]> { -let Inst{13-5} = 0b000000001; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_lvsplatw_128B : HInst< -(outs VectorRegs128B:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vsplat($Rt32)", CVI_VX_LATE, TypeCVI_VX>, Enc_9768377, Requires<[HasV60T,UseHVX]> { @@ -25985,24 +25709,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_pred_and : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), -"$Qd4 = and($Qs4,$Qt4)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000000; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_pred_and_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = and($Qs4,$Qt4)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000000; @@ -26012,24 +25722,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_pred_and_n : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), -"$Qd4 = and($Qs4,!$Qt4)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000101; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_pred_and_n_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = and($Qs4,!$Qt4)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000101; @@ -26039,23 +25735,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_pred_not : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4), -"$Qd4 = not($Qs4)", -CVI_VA, TypeCVI_VA>, Enc_4897205, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000010; -let Inst{13-10} = 0b0000; -let Inst{31-16} = 0b0001111000000011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_pred_not_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4), "$Qd4 = not($Qs4)", CVI_VA, TypeCVI_VA>, Enc_4897205, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000010; @@ -26064,11 +25747,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_pred_or : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = or($Qs4,$Qt4)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000001; @@ -26079,60 +25761,21 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_pred_or_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), -"$Qd4 = or($Qs4,$Qt4)", +def V6_pred_or_n : HInst< +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), +"$Qd4 = or($Qs4,!$Qt4)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000001; +let Inst{7-2} = 0b000100; let Inst{13-10} = 0b0000; let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_pred_or_n : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), -"$Qd4 = or($Qs4,!$Qt4)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000100; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_pred_or_n_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), -"$Qd4 = or($Qs4,!$Qt4)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000100; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_pred_scalar2 : HInst< -(outs VecPredRegs:$Qd4), -(ins IntRegs:$Rt32), -"$Qd4 = vsetq($Rt32)", -CVI_VP_LONG, TypeCVI_VP>, Enc_12781442, Requires<[HasV60T,UseHVX]> { -let Inst{13-2} = 0b000000010001; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_pred_scalar2_128B : HInst< -(outs VecPredRegs128B:$Qd4), +(outs HvxQR:$Qd4), (ins IntRegs:$Rt32), "$Qd4 = vsetq($Rt32)", CVI_VP_LONG, TypeCVI_VP>, Enc_12781442, Requires<[HasV60T,UseHVX]> { @@ -26141,21 +25784,9 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_pred_scalar2v2 : HInst< -(outs VecPredRegs:$Qd4), -(ins IntRegs:$Rt32), -"$Qd4 = vsetq2($Rt32)", -CVI_VP_LONG, TypeCVI_VP>, Enc_12781442, Requires<[HasV62T,UseHVX]> { -let Inst{13-2} = 0b000000010011; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_pred_scalar2v2_128B : HInst< -(outs VecPredRegs128B:$Qd4), +(outs HvxQR:$Qd4), (ins IntRegs:$Rt32), "$Qd4 = vsetq2($Rt32)", CVI_VP_LONG, TypeCVI_VP>, Enc_12781442, Requires<[HasV62T,UseHVX]> { @@ -26164,24 +25795,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_pred_xor : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), -"$Qd4 = xor($Qs4,$Qt4)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000011; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_pred_xor_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = xor($Qs4,$Qt4)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000011; @@ -26191,24 +25808,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_shuffeqh : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), -"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV62T,UseHVX]> { -let Inst{7-2} = 0b000110; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_shuffeqh_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4.b = vshuffe($Qs4.h,$Qt4.h)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV62T,UseHVX]> { let Inst{7-2} = 0b000110; @@ -26218,24 +25821,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_shuffeqw : HInst< -(outs VecPredRegs:$Qd4), -(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), -"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV62T,UseHVX]> { -let Inst{7-2} = 0b000111; -let Inst{13-10} = 0b0000; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_shuffeqw_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +(outs HvxQR:$Qd4), +(ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4.h = vshuffe($Qs4.w,$Qt4.w)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV62T,UseHVX]> { let Inst{7-2} = 0b000111; @@ -26245,299 +25834,146 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_st0 : HInst< (outs), -(ins IntRegs:$Rt32, VectorRegs:$Vs32), -"vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_st0_128B : HInst< -(outs), -(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins IntRegs:$Rt32, HvxVR:$Vs32), "vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stn0 : HInst< (outs), -(ins IntRegs:$Rt32, VectorRegs:$Os8), -"vmem($Rt32) = $Os8.new", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let opNewValue = 1; -} -def V6_stn0_128B : HInst< -(outs), -(ins IntRegs:$Rt32, VectorRegs128B:$Os8), +(ins IntRegs:$Rt32, HvxVR:$Os8), "vmem($Rt32) = $Os8.new", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let opNewValue = 1; } def V6_stnnt0 : HInst< (outs), -(ins IntRegs:$Rt32, VectorRegs:$Os8), -"vmem($Rt32):nt = $Os8.new", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let opNewValue = 1; -} -def V6_stnnt0_128B : HInst< -(outs), -(ins IntRegs:$Rt32, VectorRegs128B:$Os8), +(ins IntRegs:$Rt32, HvxVR:$Os8), "vmem($Rt32):nt = $Os8.new", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let opNewValue = 1; } def V6_stnp0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), -"if (!$Pv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stnp0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stnpnt0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), -"if (!$Pv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stnpnt0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stnq0 : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), -"if (!$Qv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stnq0_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stnqnt0 : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), -"if (!$Qv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stnqnt0_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stnt0 : HInst< (outs), -(ins IntRegs:$Rt32, VectorRegs:$Vs32), -"vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stnt0_128B : HInst< -(outs), -(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins IntRegs:$Rt32, HvxVR:$Vs32), "vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stp0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), -"if ($Pv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stp0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stpnt0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), -"if ($Pv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stpnt0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stq0 : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), -"if ($Qv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stq0_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stqnt0 : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), -"if ($Qv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stqnt0_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stu0 : HInst< (outs), -(ins IntRegs:$Rt32, VectorRegs:$Vs32), -"vmemu($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stu0_128B : HInst< -(outs), -(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins IntRegs:$Rt32, HvxVR:$Vs32), "vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stunp0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), -"if (!$Pv4) vmemu($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stunp0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_stup0 : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), -"if ($Pv4) vmemu($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_stup0_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vL32Ub_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32 = vmemu($Rt32+#$Ii)", CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_1244745, Requires<[HasV60T,UseHVX]> { @@ -26552,25 +25988,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32Ub_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32 = vmemu($Rt32+#$Ii)", -CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_8437395, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32Ub_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32 = vmemu($Rx32++#$Ii)", CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_10039393, Requires<[HasV60T,UseHVX]> { @@ -26586,26 +26005,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32Ub_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32 = vmemu($Rx32++#$Ii)", -CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_11039423, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32Ub_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32 = vmemu($Rx32++$Mu2)", CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_15949334, Requires<[HasV60T,UseHVX]> { @@ -26620,25 +26021,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32Ub_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32 = vmemu($Rx32++$Mu2)", -CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_15949334, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000111; -let Inst{31-21} = 0b00101011000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32 = vmem($Rt32+#$Ii)", CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { @@ -26654,26 +26038,8 @@ let isCVLoadable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32 = vmem($Rt32+#$Ii)", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_cur_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.cur = vmem($Rt32+#$Ii)", CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { @@ -26688,25 +26054,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_cur_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32.cur = vmem($Rt32+#$Ii)", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_cur_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -26722,26 +26071,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_cur_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_cur_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -26759,28 +26090,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_cur_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { @@ -26797,27 +26108,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000101; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_cur_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32.cur = vmem($Rx32++#$Ii)", CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { @@ -26833,26 +26125,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32.cur = vmem($Rx32++#$Ii)", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_cur_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.cur = vmem($Rx32++$Mu2)", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { @@ -26867,25 +26141,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32.cur = vmem($Rx32++$Mu2)", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000001; -let Inst{31-21} = 0b00101011000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_cur_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -26900,25 +26157,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_cur_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_cur_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", CVI_VM_CUR_LD, TypeCOPROC_VMEM>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -26935,27 +26175,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", -CVI_VM_CUR_LD, TypeCOPROC_VMEM>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_cur_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { @@ -26971,26 +26192,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_cur_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000100; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)", CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -27006,26 +26209,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)", CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -27043,28 +26228,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)", CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { @@ -27081,27 +26246,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000011; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32 = vmem($Rt32+#$Ii):nt", CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { @@ -27118,27 +26264,8 @@ let isCVLoadable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32 = vmem($Rt32+#$Ii):nt", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_cur_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.cur = vmem($Rt32+#$Ii):nt", CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { @@ -27154,26 +26281,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_cur_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32.cur = vmem($Rt32+#$Ii):nt", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_cur_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -27190,27 +26299,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_cur_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_cur_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -27229,29 +26319,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_cur_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { @@ -27269,28 +26338,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000101; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_cur_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32.cur = vmem($Rx32++#$Ii):nt", CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { @@ -27307,27 +26356,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32.cur = vmem($Rx32++#$Ii):nt", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_cur_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.cur = vmem($Rx32++$Mu2):nt", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { @@ -27343,26 +26373,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32.cur = vmem($Rx32++$Mu2):nt", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000001; -let Inst{31-21} = 0b00101011010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_cur_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -27378,26 +26390,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_cur_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_cur_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -27415,28 +26409,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", -CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_cur_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", CVI_VM_CUR_LD, TypeCOPROC_VMEM>, Enc_3158657, Requires<[HasV62T,UseHVX]> { @@ -27453,27 +26427,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_cur_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", -CVI_VM_CUR_LD, TypeCOPROC_VMEM>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000100; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -27490,27 +26445,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -27529,29 +26465,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { @@ -27569,28 +26484,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000011; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32 = vmem($Rx32++#$Ii):nt", CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { @@ -27608,28 +26503,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32 = vmem($Rx32++#$Ii):nt", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32 = vmem($Rx32++$Mu2):nt", CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { @@ -27646,27 +26521,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32 = vmem($Rx32++$Mu2):nt", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000000; -let Inst{31-21} = 0b00101011010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -27682,26 +26538,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -27719,28 +26557,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { @@ -27757,27 +26575,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000010; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_tmp_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.tmp = vmem($Rt32+#$Ii):nt", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { @@ -27793,26 +26592,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_tmp_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32.tmp = vmem($Rt32+#$Ii):nt", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_tmp_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -27829,27 +26610,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_tmp_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_tmp_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -27868,36 +26630,33 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; +def V6_vL32b_nt_tmp_npred_ppu : HInst< +(outs HvxVR:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000111; +let Inst{31-21} = 0b00101011110; let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; -let accessSize = Vector128Access; +let accessSize = Vector64Access; let isCVLoad = 1; let isNonTemporal = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000111; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let isPredicatedFalse = 1; +def V6_vL32b_nt_tmp_pi : HInst< +(outs HvxVR:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32.tmp = vmem($Rx32++#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; let hasNewValue = 1; let opNewValue = 0; let addrMode = PostInc; @@ -27908,65 +26667,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000111; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} -def V6_vL32b_nt_tmp_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32.tmp = vmem($Rx32++#$Ii):nt", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector64Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Rx32 = $Rx32in"; -} -def V6_vL32b_nt_tmp_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32.tmp = vmem($Rx32++#$Ii):nt", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_tmp_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.tmp = vmem($Rx32++$Mu2):nt", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { @@ -27982,26 +26684,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32.tmp = vmem($Rx32++$Mu2):nt", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000010; -let Inst{31-21} = 0b00101011010; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_tmp_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -28017,26 +26701,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_nt_tmp_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{31-21} = 0b00101000110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_nt_tmp_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -28054,28 +26720,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_nt_tmp_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { @@ -28092,27 +26738,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_nt_tmp_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000110; -let Inst{31-21} = 0b00101011110; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let isNonTemporal = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32 = vmem($Rx32++#$Ii)", CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { @@ -28129,27 +26756,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32 = vmem($Rx32++#$Ii)", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32 = vmem($Rx32++$Mu2)", CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { @@ -28165,26 +26773,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32 = vmem($Rx32++$Mu2)", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000000; -let Inst{31-21} = 0b00101011000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let isCVLoadable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)", CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -28199,25 +26789,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)", CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -28234,27 +26807,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)", CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { @@ -28270,26 +26824,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)", -CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000010; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.tmp = vmem($Rt32+#$Ii)", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { @@ -28304,25 +26840,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_tmp_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins IntRegs:$Rt32, s4_0Imm:$Ii), -"$Vd32.tmp = vmem($Rt32+#$Ii)", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_tmp_npred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -28338,26 +26857,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_tmp_npred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_tmp_npred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -28375,28 +26876,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_npred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_npred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { @@ -28413,27 +26894,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_npred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000111; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32.tmp = vmem($Rx32++#$Ii)", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { @@ -28449,26 +26911,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii), -"$Vd32.tmp = vmem($Rx32++#$Ii)", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.tmp = vmem($Rx32++$Mu2)", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { @@ -28483,25 +26927,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2), -"$Vd32.tmp = vmem($Rx32++$Mu2)", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { -let Inst{12-5} = 0b00000010; -let Inst{31-21} = 0b00101011000; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_pred_ai : HInst< -(outs VectorRegs:$Vd32), +(outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { @@ -28516,25 +26943,8 @@ let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vL32b_tmp_pred_ai_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), -"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{31-21} = 0b00101000100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vL32b_tmp_pred_pi : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { @@ -28551,27 +26961,8 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_pred_pi_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), -"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vL32b_tmp_pred_ppu : HInst< -(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { @@ -28587,27 +26978,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vL32b_tmp_pred_ppu_128B : HInst< -(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), -"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", -CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { -let Inst{10-5} = 0b000110; -let Inst{31-21} = 0b00101011100; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isCVLoad = 1; -let mayLoad = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_ai : HInst< (outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "vmemu($Rt32+#$Ii) = $Vs32", CVI_VM_STU, TypeCVI_VM_STU>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b111; @@ -28620,25 +26993,9 @@ let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32Ub_ai_128B : HInst< -(outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmemu($Rt32+#$Ii) = $Vs32", -CVI_VM_STU, TypeCVI_VM_STU>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b111; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000001; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ai_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32Ub_npred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32", CVI_VM_STU, TypeCVI_VM_STU>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b111; @@ -28651,25 +27008,9 @@ let BaseOpcode = "V6_vS32Ub_ai"; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32Ub_npred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32", -CVI_VM_STU, TypeCVI_VM_STU>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b111; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32Ub_npred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32", CVI_VM_STU, TypeCVI_VM_STU>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b111; @@ -28684,27 +27025,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_npred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32", -CVI_VM_STU, TypeCVI_VM_STU>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_pi_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_npred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32", CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-5} = 0b000111; @@ -28718,26 +27041,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_npred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32", -CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-5} = 0b000111; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_pi : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "vmemu($Rx32++#$Ii) = $Vs32", CVI_VM_STU, TypeCVI_VM_STU>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b111; @@ -28751,26 +27057,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmemu($Rx32++#$Ii) = $Vs32", -CVI_VM_STU, TypeCVI_VM_STU>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b111; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_pi_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_ppu : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "vmemu($Rx32++$Mu2) = $Vs32", CVI_VM_STU, TypeCVI_VM_STU>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{12-5} = 0b00000111; @@ -28783,25 +27072,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"vmemu($Rx32++$Mu2) = $Vs32", -CVI_VM_STU, TypeCVI_VM_STU>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{12-5} = 0b00000111; -let Inst{31-21} = 0b00101011001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ppu_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_pred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32", CVI_VM_STU, TypeCVI_VM_STU>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b110; @@ -28813,24 +27086,9 @@ let BaseOpcode = "V6_vS32Ub_ai"; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32Ub_pred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32", -CVI_VM_STU, TypeCVI_VM_STU>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b110; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32Ub_pred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32", CVI_VM_STU, TypeCVI_VM_STU>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b110; @@ -28844,26 +27102,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_pred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32", -CVI_VM_STU, TypeCVI_VM_STU>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_pi_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32Ub_pred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32", CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-5} = 0b000110; @@ -28876,25 +27117,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32Ub_pred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32", -CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-5} = 0b000110; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32Ub_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_ai : HInst< (outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rt32+#$Ii) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; @@ -28908,26 +27133,9 @@ let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_ai_128B : HInst< -(outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmem($Rt32+#$Ii) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000001; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_new_ai : HInst< (outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "vmem($Rt32+#$Ii) = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_6608821, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b00100; @@ -28943,28 +27151,9 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 2; } -def V6_vS32b_new_ai_128B : HInst< -(outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"vmem($Rt32+#$Ii) = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2152247, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b00100; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000001; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 2; -} def V6_vS32b_new_npred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01101; @@ -28980,28 +27169,9 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; } -def V6_vS32b_new_npred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01101; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -} def V6_vS32b_new_npred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01101; @@ -29019,30 +27189,9 @@ let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_npred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_new_npred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-3} = 0b00001101; @@ -29059,29 +27208,9 @@ let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_npred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-3} = 0b00001101; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_new_pi : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "vmem($Rx32++#$Ii) = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_12244921, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b00100; @@ -29098,29 +27227,9 @@ let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"vmem($Rx32++#$Ii) = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_11244923, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b00100; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_new_ppu : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "vmem($Rx32++$Mu2) = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{12-3} = 0b0000000100; @@ -29136,28 +27245,9 @@ let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"vmem($Rx32++$Mu2) = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{12-3} = 0b0000000100; -let Inst{31-21} = 0b00101011001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_new_pred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01000; @@ -29172,27 +27262,9 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; } -def V6_vS32b_new_pred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01000; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -} def V6_vS32b_new_pred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01000; @@ -29209,29 +27281,9 @@ let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_pred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_new_pred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-3} = 0b00001000; @@ -29247,28 +27299,9 @@ let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_new_pred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-3} = 0b00001000; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_npred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b001; @@ -29282,26 +27315,9 @@ let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_npred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b001; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_npred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b001; @@ -29317,28 +27333,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_npred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_npred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-5} = 0b000001; @@ -29353,27 +27350,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_npred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-5} = 0b000001; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nqpred_ai : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -29383,22 +27362,9 @@ let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nqpred_ai_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{31-21} = 0b00101000100; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nqpred_pi : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -29410,24 +27376,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nqpred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nqpred_ppu : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { let Inst{10-5} = 0b000001; @@ -29438,23 +27389,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nqpred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { -let Inst{10-5} = 0b000001; -let Inst{31-21} = 0b00101011100; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_ai : HInst< (outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rt32+#$Ii):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; @@ -29469,27 +27406,9 @@ let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nt_ai_128B : HInst< -(outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmem($Rt32+#$Ii):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000011; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nt_new_ai : HInst< (outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "vmem($Rt32+#$Ii):nt = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_6608821, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b00100; @@ -29506,29 +27425,9 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 2; } -def V6_vS32b_nt_new_ai_128B : HInst< -(outs), -(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"vmem($Rt32+#$Ii):nt = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2152247, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b00100; -let Inst{12-11} = 0b00; -let Inst{31-21} = 0b00101000011; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNonTemporal = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 2; -} def V6_vS32b_nt_new_npred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01111; @@ -29545,29 +27444,9 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; } -def V6_vS32b_nt_new_npred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01111; -let Inst{31-21} = 0b00101000111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNonTemporal = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -} def V6_vS32b_nt_new_npred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01111; @@ -29586,31 +27465,9 @@ let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_new_npred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNonTemporal = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_new_npred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-3} = 0b00001111; @@ -29628,30 +27485,9 @@ let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_new_npred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-3} = 0b00001111; -let Inst{31-21} = 0b00101011111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNonTemporal = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_new_pi : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "vmem($Rx32++#$Ii):nt = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_12244921, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b00100; @@ -29669,30 +27505,9 @@ let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_new_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"vmem($Rx32++#$Ii):nt = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_11244923, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b00100; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001011; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNonTemporal = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_new_ppu : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "vmem($Rx32++$Mu2):nt = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{12-3} = 0b0000000100; @@ -29709,29 +27524,9 @@ let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_new_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"vmem($Rx32++$Mu2):nt = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{12-3} = 0b0000000100; -let Inst{31-21} = 0b00101011011; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNonTemporal = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_new_pred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01010; @@ -29747,28 +27542,9 @@ let DecoderNamespace = "EXT_mmvec"; let opNewValue = 3; } -def V6_vS32b_nt_new_pred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01010; -let Inst{31-21} = 0b00101000111; -let isPredicated = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNonTemporal = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 3; -} def V6_vS32b_nt_new_pred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-3} = 0b01010; @@ -29786,69 +27562,28 @@ let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_new_pred_pi_128B : HInst< +def V6_vS32b_nt_new_pred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-3} = 0b01010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001111; +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), +"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001010; +let Inst{31-21} = 0b00101011111; let isPredicated = 1; let addrMode = PostInc; -let accessSize = Vector128Access; +let accessSize = Vector64Access; let isNVStore = 1; let mayStore = 1; let isNonTemporal = 1; let isNewValue = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; +let BaseOpcode = "V6_vS32b_ppu"; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} -def V6_vS32b_nt_new_pred_ppu : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), -"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-3} = 0b00001010; -let Inst{31-21} = 0b00101011111; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector64Access; -let isNVStore = 1; -let mayStore = 1; -let isNonTemporal = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ppu"; -let DecoderNamespace = "EXT_mmvec"; -let opNewValue = 4; -let Constraints = "$Rx32 = $Rx32in"; -} -def V6_vS32b_nt_new_pred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), -"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", -CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-3} = 0b00001010; -let Inst{31-21} = 0b00101011111; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let isNVStore = 1; -let mayStore = 1; -let isNonTemporal = 1; -let isNewValue = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } def V6_vS32b_nt_npred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b001; @@ -29863,27 +27598,9 @@ let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nt_npred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b001; -let Inst{31-21} = 0b00101000111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nt_npred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b001; @@ -29900,29 +27617,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_npred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_npred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-5} = 0b000001; @@ -29938,28 +27635,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_npred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-5} = 0b000001; -let Inst{31-21} = 0b00101011111; -let isPredicated = 1; -let isPredicatedFalse = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_nqpred_ai : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -29970,23 +27648,9 @@ let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nt_nqpred_ai_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{31-21} = 0b00101000110; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nt_nqpred_pi : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -29999,25 +27663,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_nqpred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_nqpred_ppu : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { let Inst{10-5} = 0b000001; @@ -30029,24 +27677,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_nqpred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { -let Inst{10-5} = 0b000001; -let Inst{31-21} = 0b00101011110; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_pi : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rx32++#$Ii):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; @@ -30062,28 +27695,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmem($Rx32++#$Ii):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001011; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_ppu : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "vmem($Rx32++$Mu2):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{12-5} = 0b00000000; @@ -30098,27 +27712,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"vmem($Rx32++$Mu2):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{12-5} = 0b00000000; -let Inst{31-21} = 0b00101011011; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_pred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; @@ -30132,26 +27728,9 @@ let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nt_pred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{31-21} = 0b00101000111; -let isPredicated = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nt_pred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; @@ -30167,28 +27746,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_pred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001111; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_pred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{10-5} = 0b000000; @@ -30203,27 +27763,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_pred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{10-5} = 0b000000; -let Inst{31-21} = 0b00101011111; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let BaseOpcode = "V6_vS32b_ppu_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_qpred_ai : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -30234,23 +27776,9 @@ let isNonTemporal = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_nt_qpred_ai_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{31-21} = 0b00101000110; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_nt_qpred_pi : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -30263,25 +27791,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_qpred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001110; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_nt_qpred_ppu : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { let Inst{10-5} = 0b000000; @@ -30293,24 +27805,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_nt_qpred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { -let Inst{10-5} = 0b000000; -let Inst{31-21} = 0b00101011110; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNonTemporal = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_pi : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rx32++#$Ii) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; @@ -30325,27 +27822,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"vmem($Rx32++#$Ii) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{13-11} = 0b000; -let Inst{31-21} = 0b00101001001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_ppu : HInst< (outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "vmem($Rx32++$Mu2) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{12-5} = 0b00000000; @@ -30358,25 +27837,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"vmem($Rx32++$Mu2) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{12-5} = 0b00000000; -let Inst{31-21} = 0b00101011001; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNVStorable = 1; -let isPredicable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_pred_ai : HInst< (outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32+#$Ii) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { let Inst{7-5} = 0b000; @@ -30389,25 +27852,9 @@ let isNVStorable = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_pred_ai_128B : HInst< -(outs), -(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { -let Inst{7-5} = 0b000; -let Inst{31-21} = 0b00101000101; -let isPredicated = 1; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_ai_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_pred_pi : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++#$Ii) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -30422,27 +27869,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_pred_pi_128B : HInst< +def V6_vS32b_pred_ppu : HInst< (outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let BaseOpcode = "V6_vS32b_pi_128B"; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} -def V6_vS32b_pred_ppu : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++$Mu2) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]> { let Inst{10-5} = 0b000000; @@ -30455,25 +27884,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_pred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]> { -let Inst{10-5} = 0b000000; -let Inst{31-21} = 0b00101011101; -let isPredicated = 1; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let isNVStorable = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_qpred_ai : HInst< (outs), -(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32+#$Ii) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -30483,22 +27896,9 @@ let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vS32b_qpred_ai_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{31-21} = 0b00101000100; -let addrMode = BaseImmOffset; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vS32b_qpred_pi : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++#$Ii) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -30510,24 +27910,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_qpred_pi_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00101001100; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vS32b_qpred_ppu : HInst< (outs IntRegs:$Rx32), -(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++$Mu2) = $Vs32", CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { let Inst{10-5} = 0b000000; @@ -30538,35 +27923,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } -def V6_vS32b_qpred_ppu_128B : HInst< -(outs IntRegs:$Rx32), -(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), -"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32", -CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { -let Inst{10-5} = 0b000000; -let Inst{31-21} = 0b00101011100; -let addrMode = PostInc; -let accessSize = Vector128Access; -let mayStore = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Rx32 = $Rx32in"; -} def V6_vabsdiffh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)", -CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsdiffh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)", CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -30575,11 +27934,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsdiffh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -30588,33 +27946,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vabsdiffh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vabsdiffh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vabsdiffub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)", -CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsdiffub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)", CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -30623,22 +27957,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsdiffub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vabsdiffub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsdiffub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -30646,23 +27968,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsdiffuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)", -CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsdiffuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)", CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -30671,22 +27980,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsdiffuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vabsdiffuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsdiffuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -30694,23 +27991,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsdiffw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)", -CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsdiffw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)", CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -30719,22 +28003,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsdiffw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vabsdiffw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsdiffw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -30742,23 +28014,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32.h = vabs($Vu32.h)", -CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vabs($Vu32.h)", CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -30767,22 +28026,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vabsh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vabsh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -30790,23 +28037,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsh_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32.h = vabs($Vu32.h):sat", -CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsh_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vabs($Vu32.h):sat", CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -30815,22 +28049,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsh_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vabsh($Vu32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsh_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vabsh($Vu32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -30838,23 +28060,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32.w = vabs($Vu32.w)", -CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.w = vabs($Vu32.w)", CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -30863,22 +28072,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vabsw($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vabsw($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -30886,23 +28083,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsw_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32.w = vabs($Vu32.w):sat", -CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsw_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.w = vabs($Vu32.w):sat", CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -30911,22 +28095,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vabsw_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vabsw($Vu32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vabsw_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vabsw($Vu32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -30934,23 +28106,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.b = vadd($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vadd($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -30959,22 +28118,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vaddb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -30982,23 +28129,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddb_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddb_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -31007,22 +28141,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddb_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vaddb($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddb_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vaddb($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31030,11 +28152,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddbnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.b += $Vu32.b", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -31047,67 +28168,22 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddbnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4) $Vx32.b += $Vu32.b", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; +def V6_vaddbnq_alt : HInst< +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), +"if (!$Qv4.b) $Vx32.b += $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaddbnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if (!$Qv4.b) $Vx32.b += $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaddbnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if (!$Qv4.b) $Vx32.b += $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; +let isPseudo = 1; let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaddbq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if ($Qv4) $Vx32.b += $Vu32.b", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaddbq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.b += $Vu32.b", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -31118,25 +28194,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaddbq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if ($Qv4.b) $Vx32.b += $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaddbq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.b) $Vx32.b += $Vu32.b", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31145,24 +28207,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaddbsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddbsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vadd($Vu32.b,$Vv32.b):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b000; @@ -31171,22 +28220,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddbsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vaddb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddbsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddb($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -31194,23 +28231,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddbsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddbsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b000; @@ -31219,22 +28243,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddbsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vaddb($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddbsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vaddb($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -31242,26 +28254,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddcarry : HInst< -(outs VectorRegs:$Vd32, VecPredRegs:$Qx4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, VecPredRegs:$Qx4in), -"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry", -CVI_VA, TypeCVI_VA>, Enc_13691337, Requires<[HasV62T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vaddcarry_128B : HInst< -(outs VectorRegs128B:$Vd32, VecPredRegs128B:$Qx4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, VecPredRegs128B:$Qx4in), +(outs HvxVR:$Vd32, HvxQR:$Qx4), +(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in), "$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry", CVI_VA, TypeCVI_VA>, Enc_13691337, Requires<[HasV62T,UseHVX]> { let Inst{7-7} = 0b0; @@ -31272,24 +28268,11 @@ let hasNewValue2 = 1; let opNewValue2 = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vaddclbh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddclbh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b000; @@ -31298,23 +28281,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddclbw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddclbw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -31323,23 +28293,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vadd($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vadd($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -31348,22 +28305,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vaddh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31371,23 +28316,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddh_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddh_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -31396,22 +28328,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddh_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vaddh($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddh_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vaddh($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31419,26 +28339,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddhnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if (!$Qv4) $Vx32.h += $Vu32.h", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaddhnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.h += $Vu32.h", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -31449,25 +28353,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaddhnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if (!$Qv4.h) $Vx32.h += $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaddhnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.h) $Vx32.h += $Vu32.h", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31476,27 +28366,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaddhq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if ($Qv4) $Vx32.h += $Vu32.h", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaddhq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.h += $Vu32.h", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -31507,12 +28381,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaddhq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.h) $Vx32.h += $Vu32.h", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31523,35 +28396,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vaddhq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), -"if ($Qv4.h) $Vx32.h += $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vaddhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vadd($Vu32.h,$Vv32.h):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -31560,22 +28407,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vaddh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddhsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31583,23 +28418,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddhsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddhsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -31608,22 +28430,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddhsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vaddh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddhsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vaddh($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31631,23 +28441,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddhw : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.w = vadd($Vu32.h,$Vv32.h)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddhw_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vadd($Vu32.h,$Vv32.h)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -31656,11 +28453,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddhw_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vadd($Vu32.h,$Vv32.h)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b010; @@ -31672,37 +28468,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vaddhw_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vxx32.w += vadd($Vu32.h,$Vv32.h)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vaddhw_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32 += vaddh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vaddhw_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vaddh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -31711,23 +28479,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vaddhw_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vaddh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddhw_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vaddh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31735,23 +28491,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddubh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddubh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -31760,25 +28503,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddubh_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vaddubh_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b101; @@ -31788,25 +28516,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vaddubh_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32 += vaddub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vaddubh_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vaddub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -31815,23 +28529,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vaddubh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vaddub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddubh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vaddub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31839,23 +28541,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddubsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddubsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -31864,22 +28553,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddubsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vaddub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddubsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddub($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31887,23 +28564,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddubsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddubsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -31912,22 +28576,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddubsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vaddub($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddubsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vaddub($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -31935,23 +28587,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddububb_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddububb_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -31960,23 +28599,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vadduhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vadduhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -31985,22 +28611,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vadduhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vadduh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vadduhsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vadduh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32008,23 +28622,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vadduhsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vadduhsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -32033,22 +28634,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vadduhsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vadduh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vadduhsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vadduh($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32056,23 +28645,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vadduhw : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vadduhw_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -32081,25 +28657,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vadduhw_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vadduhw_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -32109,25 +28670,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vadduhw_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32 += vadduh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vadduhw_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vadduh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -32136,23 +28683,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vadduhw_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vadduh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vadduhw_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vadduh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32160,23 +28695,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vadduwsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vadduwsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -32185,22 +28707,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vadduwsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vadduw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vadduwsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vadduw($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -32208,23 +28718,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vadduwsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vadduwsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b010; @@ -32233,22 +28730,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vadduwsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vadduw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vadduwsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vadduw($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -32256,23 +28741,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vadd($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vadd($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -32281,22 +28753,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vaddw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32304,11 +28764,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddw_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -32318,33 +28777,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vaddw_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), -"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vaddw_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vaddw($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddw_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vaddw($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32352,26 +28787,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddwnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if (!$Qv4) $Vx32.w += $Vu32.w", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaddwnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.w += $Vu32.w", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -32382,25 +28801,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaddwnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if (!$Qv4.w) $Vx32.w += $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaddwnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.w) $Vx32.w += $Vu32.w", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32409,27 +28814,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaddwq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if ($Qv4) $Vx32.w += $Vu32.w", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaddwq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.w += $Vu32.w", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -32440,25 +28829,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaddwq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if ($Qv4.w) $Vx32.w += $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaddwq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.w) $Vx32.w += $Vu32.w", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32467,24 +28842,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaddwsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddwsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vadd($Vu32.w,$Vv32.w):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -32493,22 +28855,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddwsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vaddw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddwsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddw($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32516,23 +28866,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddwsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddwsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -32541,22 +28878,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaddwsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vaddw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaddwsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vaddw($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32564,23 +28889,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_valignb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = valign($Vu32,$Vv32,$Rt8)", -CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_valignb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = valign($Vu32,$Vv32,$Rt8)", CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -32589,22 +28901,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_valignbi : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), -"$Vd32 = valign($Vu32,$Vv32,#$Ii)", -CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011110001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_valignbi_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vd32 = valign($Vu32,$Vv32,#$Ii)", CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { let Inst{13-13} = 0b1; @@ -32612,23 +28912,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vand : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vand($Vu32,$Vv32)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vand_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vand($Vu32,$Vv32)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -32637,23 +28924,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vandnqrt : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qu4, IntRegs:$Rt32), -"$Vd32 = vand(!$Qu4,$Rt32)", -CVI_VX, TypeCVI_VX>, Enc_4711514, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-10} = 0b0001; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vandnqrt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32 = vand(!$Qu4,$Rt32)", CVI_VX, TypeCVI_VX>, Enc_4711514, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b101; @@ -32662,25 +28936,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vandnqrt_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), -"$Vx32 |= vand(!$Qu4,$Rt32)", -CVI_VX, TypeCVI_VX>, Enc_4944558, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-10} = 0b1001; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vandnqrt_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32 |= vand(!$Qu4,$Rt32)", CVI_VX, TypeCVI_VX>, Enc_4944558, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -32690,25 +28949,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vandnqrt_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), -"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vandnqrt_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -32717,23 +28962,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vandnqrt_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qu4, IntRegs:$Rt32), -"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vandnqrt_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -32741,23 +28974,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vandqrt : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qu4, IntRegs:$Rt32), -"$Vd32 = vand($Qu4,$Rt32)", -CVI_VX_LATE, TypeCVI_VX>, Enc_4711514, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-10} = 0b0000; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vandqrt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32 = vand($Qu4,$Rt32)", CVI_VX_LATE, TypeCVI_VX>, Enc_4711514, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -32766,25 +28986,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vandqrt_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), -"$Vx32 |= vand($Qu4,$Rt32)", -CVI_VX_LATE, TypeCVI_VX>, Enc_4944558, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-10} = 0b1000; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vandqrt_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32 |= vand($Qu4,$Rt32)", CVI_VX_LATE, TypeCVI_VX>, Enc_4944558, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -32794,25 +28999,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vandqrt_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), -"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vandqrt_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32821,23 +29012,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vandqrt_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qu4, IntRegs:$Rt32), -"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vandqrt_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -32845,24 +29024,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vandvnqv : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vu32), -"$Vd32 = vand(!$Qv4,$Vu32)", -CVI_VA, TypeCVI_VA>, Enc_1220199, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vandvnqv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qv4, HvxVR:$Vu32), "$Vd32 = vand(!$Qv4,$Vu32)", CVI_VA, TypeCVI_VA>, Enc_1220199, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -32872,24 +29037,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vandvqv : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vu32), -"$Vd32 = vand($Qv4,$Vu32)", -CVI_VA, TypeCVI_VA>, Enc_1220199, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000011; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vandvqv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxQR:$Qv4, HvxVR:$Vu32), "$Vd32 = vand($Qv4,$Vu32)", CVI_VA, TypeCVI_VA>, Enc_1220199, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b000; @@ -32899,23 +29050,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vandvrt : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Qd4 = vand($Vu32,$Rt32)", -CVI_VX_LATE, TypeCVI_VX>, Enc_11498120, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vandvrt_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Qd4 = vand($Vu32,$Rt32)", CVI_VX_LATE, TypeCVI_VX>, Enc_11498120, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010010; @@ -32924,11 +29062,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vandvrt_acc : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32), "$Qx4 |= vand($Vu32,$Rt32)", CVI_VX_LATE, TypeCVI_VX>, Enc_10612292, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100000; @@ -32940,62 +29077,22 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vandvrt_acc_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Qx4 |= vand($Vu32,$Rt32)", -CVI_VX_LATE, TypeCVI_VX>, Enc_10612292, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vandvrt_acc_alt : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vandvrt_acc_alt_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +def V6_vandvrt_acc_alt : HInst< +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32), +"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vandvrt_alt : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vandvrt_alt_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33003,23 +29100,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaslh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vasl($Vu32.h,$Rt32)", -CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaslh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vasl($Vu32.h,$Rt32)", CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -33028,22 +29112,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaslh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vaslh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaslh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vaslh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33051,23 +29123,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaslhv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vasl($Vu32.h,$Vv32.h)", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaslhv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vasl($Vu32.h,$Vv32.h)", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -33076,22 +29135,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaslhv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vaslh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaslhv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaslh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33099,23 +29146,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaslw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vasl($Vu32.w,$Rt32)", -CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaslw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vasl($Vu32.w,$Rt32)", CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -33124,25 +29158,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaslw_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vasl($Vu32.w,$Rt32)", -CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaslw_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vasl($Vu32.w,$Rt32)", CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -33152,25 +29171,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaslw_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32 += vaslw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vaslw_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vaslw($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33179,23 +29184,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vaslw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vaslw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaslw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vaslw($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33203,23 +29196,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaslwv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vasl($Vu32.w,$Vv32.w)", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaslwv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vasl($Vu32.w,$Vv32.w)", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -33228,22 +29208,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vaslwv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vaslw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vaslwv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaslw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33251,23 +29219,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vasr($Vu32.h,$Rt32)", -CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vasr($Vu32.h,$Rt32)", CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -33276,22 +29231,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vasrh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vasrh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33299,23 +29242,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrhbrndsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", -CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrhbrndsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -33324,11 +29254,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrhbrndsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -33337,20 +29266,8 @@ let isCodeGenOnly = 1; } def V6_vasrhbsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat", -CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrhbsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat", CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b000; @@ -33359,23 +29276,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrhubrndsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", -CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrhubrndsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -33384,11 +29288,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrhubrndsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -33397,20 +29300,8 @@ let isCodeGenOnly = 1; } def V6_vasrhubsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat", -CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrhubsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat", CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -33419,11 +29310,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrhubsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -33432,20 +29322,8 @@ let isCodeGenOnly = 1; } def V6_vasrhv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vasr($Vu32.h,$Vv32.h)", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrhv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vasr($Vu32.h,$Vv32.h)", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -33454,22 +29332,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrhv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vasrh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrhv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vasrh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33477,23 +29343,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasruwuhrndsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat", -CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasruwuhrndsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat", CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -33502,23 +29355,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vasr($Vu32.w,$Rt32)", -CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vasr($Vu32.w,$Rt32)", CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -33527,25 +29367,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrw_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vasr($Vu32.w,$Rt32)", -CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vasrw_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vasr($Vu32.w,$Rt32)", CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -33555,12 +29380,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vasrw_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vasrw($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33571,71 +29395,32 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vasrw_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vasrw($Vu32,$Rt32)", +def V6_vasrw_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), +"$Vd32 = vasrw($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; let opNewValue = 0; -let isAccumulator = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; } -def V6_vasrw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vasrw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +def V6_vasrwh : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vasrw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vasrwh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)", -CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrwh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)", -CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vasrwh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -33644,20 +29429,8 @@ let isCodeGenOnly = 1; } def V6_vasrwhrndsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", -CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrwhrndsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -33666,11 +29439,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrwhrndsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -33679,20 +29451,8 @@ let isCodeGenOnly = 1; } def V6_vasrwhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat", -CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrwhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat", CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -33701,11 +29461,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrwhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -33714,20 +29473,8 @@ let isCodeGenOnly = 1; } def V6_vasrwuhrndsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", -CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrwuhrndsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b010; @@ -33736,23 +29483,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrwuhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat", -CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrwuhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat", CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -33761,11 +29495,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrwuhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { let hasNewValue = 1; @@ -33774,20 +29507,8 @@ let isCodeGenOnly = 1; } def V6_vasrwv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vasr($Vu32.w,$Vv32.w)", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrwv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vasr($Vu32.w,$Vv32.w)", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -33796,22 +29517,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vasrwv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vasrw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vasrwv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vasrw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33819,23 +29528,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vassign : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = $Vu32", -CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-16} = 0b0001111000000011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vassign_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = $Vu32", CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -33844,44 +29540,20 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vassignp : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32), -"$Vdd32 = $Vuu32", -CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vassignp_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32), "$Vdd32 = $Vuu32", CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavgh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vavg($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavgh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vavg($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -33890,22 +29562,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavgh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vavgh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavgh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33913,23 +29573,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavghrnd : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavghrnd_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -33938,22 +29585,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavghrnd_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vavgh($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavghrnd_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgh($Vu32,$Vv32):rnd", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -33961,11 +29596,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavgub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -33975,33 +29609,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavgub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vavgub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavgub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34009,23 +29619,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavgubrnd : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavgubrnd_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -34034,22 +29631,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavgubrnd_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vavgub($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavgubrnd_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgub($Vu32,$Vv32):rnd", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34057,23 +29642,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavguh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavguh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -34082,11 +29654,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavguh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavguh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34095,33 +29666,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavguh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vavguh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vavguhrnd : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavguhrnd_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -34130,22 +29677,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavguhrnd_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vavguh($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavguhrnd_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavguh($Vu32,$Vv32):rnd", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34153,23 +29688,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavgw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vavg($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavgw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vavg($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34178,22 +29700,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavgw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vavgw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavgw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34201,23 +29711,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavgwrnd : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vavgwrnd_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -34226,11 +29723,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vavgwrnd_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgw($Vu32,$Vv32):rnd", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34239,34 +29735,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vavgwrnd_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vavgw($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vccombine : HInst< -(outs VecDblRegs:$Vdd32), -(ins PredRegs:$Ps4, VectorRegs:$Vu32, VectorRegs:$Vv32), -"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011010011; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vccombine_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins PredRegs:$Ps4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32), "if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -34276,23 +29747,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vcl0h : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32.uh = vcl0($Vu32.uh)", -CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vcl0h_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.uh = vcl0($Vu32.uh)", CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34301,22 +29759,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vcl0h_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vcl0h($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vcl0h_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vcl0h($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34324,11 +29770,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vcl0w : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.uw = vcl0($Vu32.uw)", CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -34338,33 +29783,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vcl0w_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.uw = vcl0($Vu32.uw)", -CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vcl0w_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vcl0w($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vcl0w_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vcl0w($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34372,24 +29793,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vcmov : HInst< -(outs VectorRegs:$Vd32), -(ins PredRegs:$Ps4, VectorRegs:$Vu32), -"if ($Ps4) $Vd32 = $Vu32", -CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001101000000000; -let isPredicated = 1; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vcmov_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Ps4, VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins PredRegs:$Ps4, HvxVR:$Vu32), "if ($Ps4) $Vd32 = $Vu32", CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -34399,24 +29806,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vcombine : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vcombine($Vu32,$Vv32)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let isRegSequence = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vcombine_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vcombine($Vu32,$Vv32)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34426,21 +29819,9 @@ let opNewValue = 0; let isRegSequence = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vd0 : HInst< -(outs VectorRegs:$Vd32), -(ins), -"$Vd32 = #0", -CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vd0_128B : HInst< -(outs VectorRegs128B:$Vd32), +(outs HvxVR:$Vd32), (ins), "$Vd32 = #0", CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { @@ -34449,26 +29830,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdeal : HInst< -(outs VectorRegs:$Vy32, VectorRegs:$Vx32), -(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), -"vdeal($Vy32,$Vx32,$Rt32)", -CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001111; -let hasNewValue = 1; -let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; -} -def V6_vdeal_128B : HInst< -(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), +(outs HvxVR:$Vy32, HvxVR:$Vx32), +(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), "vdeal($Vy32,$Vx32,$Rt32)", CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -34479,12 +29844,11 @@ let hasNewValue2 = 1; let opNewValue2 = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; } def V6_vdealb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.b = vdeal($Vu32.b)", CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34495,8 +29859,8 @@ let DecoderNamespace = "EXT_mmvec"; } def V6_vdealb4w : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vdeale($Vu32.b,$Vv32.b)", CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34506,33 +29870,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdealb4w_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vdeale($Vu32.b,$Vv32.b)", -CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdealb4w_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vdealb4w($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdealb4w_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vdealb4w($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34540,35 +29880,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vdealb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32.b = vdeal($Vu32.b)", -CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdealb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vdealb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdealb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vdealb($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34576,23 +29891,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdealh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32.h = vdeal($Vu32.h)", -CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdealh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vdeal($Vu32.h)", CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -34601,11 +29903,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdealh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vdealh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34614,33 +29915,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdealh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vdealh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdealvdd : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)", -CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdealvdd_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)", CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -34649,23 +29926,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdelta : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vdelta($Vu32,$Vv32)", -CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdelta_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vdelta($Vu32,$Vv32)", CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -34674,23 +29938,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpybus : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)", -CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpybus_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)", CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -34699,25 +29950,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpybus_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)", -CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpybus_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)", CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -34727,25 +29963,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpybus_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32 += vdmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpybus_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34754,23 +29976,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpybus_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vdmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpybus_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34778,23 +29988,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpybus_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpybus_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34803,25 +30000,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpybus_dv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vdmpybus_dv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -34831,25 +30013,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vdmpybus_dv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vdmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vdmpybus_dv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vdmpybus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34858,12 +30026,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vdmpybus_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vdmpybus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34872,60 +30039,21 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpybus_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vdmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vdmpyhb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)", -CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)", -CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; +def V6_vdmpyhb : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhb_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)", -CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhb_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vu32.h,$Rt32.b)", CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -34935,25 +30063,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhb_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32 += vdmpyhb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhb_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpyhb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34962,23 +30076,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vdmpyhb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpyhb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -34986,23 +30088,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhb_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhb_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -35011,25 +30100,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhb_dv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vdmpyhb_dv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -35039,25 +30113,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vdmpyhb_dv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vdmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vdmpyhb_dv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vdmpyhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35066,23 +30126,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vdmpyhb_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vdmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhb_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vdmpyhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35090,23 +30138,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhisat : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhisat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -35115,25 +30150,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhisat_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhisat_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -35143,25 +30163,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhisat_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vx32 += vdmpyh($Vuu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhisat_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vx32 += vdmpyh($Vuu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35170,23 +30176,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhisat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vd32 = vdmpyh($Vuu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhisat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vd32 = vdmpyh($Vuu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35194,23 +30188,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -35219,25 +30200,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhsat_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhsat_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -35247,25 +30213,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhsat_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32 += vdmpyh($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhsat_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpyh($Vu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35274,23 +30226,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vdmpyh($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpyh($Vu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35298,23 +30238,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhsuisat : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhsuisat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -35323,25 +30250,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhsuisat_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhsuisat_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -35351,25 +30263,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhsuisat_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhsuisat_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35378,23 +30276,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhsuisat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhsuisat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35402,23 +30288,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhsusat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhsusat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -35427,25 +30300,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhsusat_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhsusat_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -35455,25 +30313,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhsusat_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhsusat_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35482,12 +30326,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhsusat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35496,33 +30339,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vdmpyhsusat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vdmpyhvsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhvsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -35531,25 +30350,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdmpyhvsat_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhvsat_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -35559,25 +30363,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhvsat_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32 += vdmpyh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vdmpyhvsat_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vdmpyh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35586,23 +30376,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vdmpyhvsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vdmpyh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdmpyhvsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vdmpyh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35610,23 +30388,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdsaduh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdsaduh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -35635,25 +30400,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vdsaduh_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vdsaduh_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -35663,25 +30413,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vdsaduh_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vdsaduh($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vdsaduh_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vdsaduh($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35690,23 +30426,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vdsaduh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vdsaduh($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vdsaduh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vdsaduh($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -35714,23 +30438,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_veqb : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_veqb_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000000; @@ -35739,24 +30450,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_veqb_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_veqb_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000000; @@ -35765,26 +30462,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_veqb_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_veqb_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010000; @@ -35794,25 +30476,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_veqb_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_veqb_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100000; @@ -35821,24 +30489,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_veqh : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_veqh_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000001; @@ -35847,24 +30502,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_veqh_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_veqh_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000001; @@ -35873,26 +30514,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_veqh_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_veqh_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010001; @@ -35902,25 +30528,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_veqh_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_veqh_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100001; @@ -35929,24 +30541,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_veqw : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_veqw_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000010; @@ -35955,24 +30554,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_veqw_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_veqw_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000010; @@ -35981,26 +30566,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_veqw_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_veqw_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010010; @@ -36010,25 +30580,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_veqw_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_veqw_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100010; @@ -36037,24 +30593,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vgtb : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vgtb_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000100; @@ -36063,24 +30606,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vgtb_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vgtb_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000100; @@ -36089,12 +30618,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vgtb_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010100; @@ -36106,51 +30634,22 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtb_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)", +def V6_vgtb_xor : HInst< +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010100; +let Inst{7-2} = 0b100100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; -let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vgtb_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vgtb_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vgth : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000101; @@ -36160,35 +30659,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vgth_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vgth_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vgth_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000101; @@ -36197,12 +30670,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vgth_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010101; @@ -36214,37 +30686,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgth_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgth_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vgth_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100101; @@ -36253,24 +30697,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vgtub : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)", -CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vgtub_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)", CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001000; @@ -36279,11 +30710,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vgtub_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001000; @@ -36294,37 +30724,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtub_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtub_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b011000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vgtub_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b011000; @@ -36334,25 +30736,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vgtub_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b101000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vgtub_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b101000; @@ -36361,12 +30749,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vgtuh : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)", CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001001; @@ -36376,35 +30763,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vgtuh_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)", -CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vgtuh_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vgtuh_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001001; @@ -36413,26 +30774,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vgtuh_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b011001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vgtuh_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b011001; @@ -36442,12 +30788,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vgtuh_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b101001; @@ -36458,35 +30803,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtuh_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b101001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtuw : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)", -CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vgtuw_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)", CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001010; @@ -36495,11 +30814,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vgtuw_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b001010; @@ -36510,23 +30828,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtuw_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b001010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtuw_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b011010; @@ -36538,37 +30842,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtuw_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b011010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtuw_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b101010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vgtuw_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b101010; @@ -36577,12 +30853,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vgtw : HInst< -(outs VecPredRegs:$Qd4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qd4), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000110; @@ -36592,22 +30867,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vgtw_128B : HInst< -(outs VecPredRegs128B:$Qd4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vgtw_and : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b000110; @@ -36618,37 +30880,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtw_and_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b000110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vgtw_or : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b010110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vgtw_or_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b010110; @@ -36658,12 +30892,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vgtw_xor : HInst< -(outs VecPredRegs:$Qx4), -(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxQR:$Qx4), +(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { let Inst{7-2} = 0b100110; @@ -36674,20 +30907,6 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } -def V6_vgtw_xor_128B : HInst< -(outs VecPredRegs128B:$Qx4), -(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { -let Inst{7-2} = 0b100110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Qx4 = $Qx4in"; -} def V6_vhist : HInst< (outs), (ins), @@ -36697,19 +30916,9 @@ let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; } -def V6_vhist_128B : HInst< -(outs), -(ins), -"vhist", -CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV60T,UseHVX]> { -let Inst{13-0} = 0b10000010000000; -let Inst{31-16} = 0b0001111000000000; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vhistq : HInst< (outs), -(ins VecPredRegs:$Qv4), +(ins HvxQR:$Qv4), "vhist($Qv4)", CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV60T,UseHVX]> { let Inst{13-0} = 0b10000010000000; @@ -36717,20 +30926,9 @@ let Inst{31-24} = 0b00011110; let DecoderNamespace = "EXT_mmvec"; } -def V6_vhistq_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4), -"vhist($Qv4)", -CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV60T,UseHVX]> { -let Inst{13-0} = 0b10000010000000; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vinsertwr : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, IntRegs:$Rt32), "$Vx32.w = vinsert($Rt32)", CVI_VX_LATE, TypeCVI_VX>, Enc_313333, Requires<[HasV60T,UseHVX]> { let Inst{13-5} = 0b100000001; @@ -36740,22 +30938,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vinsertwr_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, IntRegs:$Rt32), -"$Vx32.w = vinsert($Rt32)", -CVI_VX_LATE, TypeCVI_VX>, Enc_313333, Requires<[HasV60T,UseHVX]> { -let Inst{13-5} = 0b100000001; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vlalignb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vlalign($Vu32,$Vv32,$Rt8)", CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -36765,33 +30950,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlalignb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)", -CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlalignbi : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), -"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)", -CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011110011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vlalignbi_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vd32 = vlalign($Vu32,$Vv32,#$Ii)", CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { let Inst{13-13} = 0b1; @@ -36799,11 +30960,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vlsrb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.ub = vlsr($Vu32.ub,$Rt32)", CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -36813,22 +30973,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.ub = vlsr($Vu32.ub,$Rt32)", -CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.uh = vlsr($Vu32.uh,$Rt32)", CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -36838,33 +30985,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.uh = vlsr($Vu32.uh,$Rt32)", -CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vlsrh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vlsrh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vlsrh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -36872,23 +30995,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vlsrhv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vlsr($Vu32.h,$Vv32.h)", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vlsrhv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vlsr($Vu32.h,$Vv32.h)", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -36897,11 +31007,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vlsrhv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vlsrh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -36910,33 +31019,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrhv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vlsrh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.uw = vlsr($Vu32.uw,$Rt32)", -CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vlsrw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.uw = vlsr($Vu32.uw,$Rt32)", CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -36945,22 +31030,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vlsrw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vlsrw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vlsrw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vlsrw($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -36968,11 +31041,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vlsrwv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vlsr($Vu32.w,$Vv32.w)", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -36982,22 +31054,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrwv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vlsr($Vu32.w,$Vv32.w)", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlsrwv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vlsrw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37006,21 +31065,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlsrwv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vlsrw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvvb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)", CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -37030,22 +31077,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlutvvb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)", -CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvvb_nm : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch", CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -37055,36 +31089,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlutvvb_nm_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch", -CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvvb_oracc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)", -CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_8877260, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vlutvvb_oracc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)", CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_8877260, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -37094,25 +31101,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vlutvvb_oracci : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), -"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)", -CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_8280533, Requires<[HasV62T,UseHVX]> { -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100110; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vlutvvb_oracci_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)", CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_8280533, Requires<[HasV62T,UseHVX]> { let Inst{13-13} = 0b1; @@ -37121,12 +31114,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vlutvvbi : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)", CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV62T,UseHVX]> { let Inst{13-13} = 0b0; @@ -37135,21 +31127,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlutvvbi_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), -"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)", -CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV62T,UseHVX]> { -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvwh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)", CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -37159,22 +31139,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlutvwh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)", -CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvwh_nm : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch", CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -37184,22 +31151,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vlutvwh_nm_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch", -CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-24} = 0b00011000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vlutvwh_oracc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)", CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_16213761, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -37211,37 +31165,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vlutvwh_oracc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), -"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)", -CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_16213761, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vlutvwh_oracci : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), -"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)", -CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_3457570, Requires<[HasV62T,UseHVX]> { -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vlutvwh_oracci_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)", CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_3457570, Requires<[HasV62T,UseHVX]> { let Inst{13-13} = 0b1; @@ -37250,23 +31176,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vlutvwhi : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), -"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)", -CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_13261538, Requires<[HasV62T,UseHVX]> { -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vlutvwhi_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)", CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_13261538, Requires<[HasV62T,UseHVX]> { let Inst{13-13} = 0b0; @@ -37274,47 +31188,22 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmaxb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vmax($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmaxb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vmax($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vmaxb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmaxb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +def V6_vmaxb_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -37322,23 +31211,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmaxh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vmax($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmaxh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmax($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -37347,22 +31223,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmaxh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmaxh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmaxh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37370,23 +31234,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmaxub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmaxub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -37395,22 +31246,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmaxub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmaxub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmaxub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37418,23 +31257,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmaxuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmaxuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -37443,22 +31269,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmaxuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmaxuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmaxuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37466,11 +31280,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmaxw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmax($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -37480,33 +31293,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmaxw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vmax($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmaxw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmaxw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmaxw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37514,23 +31303,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vminb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.b = vmin($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vminb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vmin($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -37539,22 +31315,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vminb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vminb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vminb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -37562,23 +31326,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vminh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vmin($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vminh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmin($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -37587,11 +31338,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vminh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37600,33 +31350,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vminh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vminh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vminub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vminub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -37635,22 +31361,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vminub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vminub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vminub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37658,23 +31372,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vminuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vminuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -37683,22 +31384,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vminuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vminuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vminuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37706,23 +31395,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vminw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vmin($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vminw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmin($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -37731,22 +31407,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vminw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vminw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vminw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37754,23 +31418,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpabus : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpabus_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -37779,25 +31430,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpabus_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpabus_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -37807,25 +31443,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpabus_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vmpabus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpabus_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vmpabus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37834,23 +31456,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpabus_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vmpabus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpabus_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vmpabus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37858,23 +31468,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpabusv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpabusv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -37883,22 +31480,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpabusv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vmpabus($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpabusv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vmpabus($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37906,23 +31491,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpabuuv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpabuuv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -37931,22 +31503,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vmpabuuv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vmpabuu($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpabuuv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +def V6_vmpabuuv_alt : HInst< +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vmpabuu($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -37954,23 +31514,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpahb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpahb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -37979,25 +31526,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpahb_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpahb_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -38007,25 +31539,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpahb_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vmpahb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpahb_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vmpahb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38034,23 +31552,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpahb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vmpahb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpahb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vmpahb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38058,23 +31564,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpauhb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpauhb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b101; @@ -38083,25 +31576,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpauhb_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpauhb_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b010; @@ -38111,25 +31589,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpauhb_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vmpauhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpauhb_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vmpauhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -38138,23 +31602,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpauhb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vmpauhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpauhb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vmpauhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -38162,23 +31614,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpybus : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpybus_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -38187,25 +31626,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpybus_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpybus_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -38215,25 +31639,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpybus_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vxx32 += vmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpybus_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38242,23 +31652,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpybus_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vdd32 = vmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpybus_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38266,23 +31664,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpybusv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpybusv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -38291,25 +31676,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpybusv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpybusv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -38319,25 +31689,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpybusv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32 += vmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpybusv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpybus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38346,23 +31702,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpybusv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpybusv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpybus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38370,23 +31714,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpybv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpybv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vmpy($Vu32.b,$Vv32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -38395,25 +31726,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpybv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpybv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.h += vmpy($Vu32.b,$Vv32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -38423,25 +31739,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpybv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32 += vmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpybv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38450,23 +31752,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpybv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpybv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38474,23 +31764,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyewuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyewuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpye($Vu32.w,$Vv32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -38499,11 +31776,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyewuh_64 : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpye($Vu32.w,$Vv32.uh)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b110; @@ -38513,57 +31789,20 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyewuh_64_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyewuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmpyewuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyewuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyewuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vmpyh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +def V6_vmpyh : HInst< +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.w = vmpy($Vu32.h,$Rt32.h)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -38572,22 +31811,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vdd32 = vmpyh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpyh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38595,25 +31822,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyhsat_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyhsat_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -38623,25 +31835,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyhsat_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vxx32 += vmpyh($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyhsat_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpyh($Vu32,$Rt32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38650,24 +31848,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyhsrs : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyhsrs_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -38676,22 +31861,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyhsrs_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyhsrs_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38699,23 +31872,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyhss : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyhss_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -38724,22 +31884,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyhss_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyhss_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38747,23 +31895,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyhus : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyhus_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -38772,25 +31907,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyhus_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyhus_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -38800,25 +31920,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyhus_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32 += vmpyhus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyhus_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyhus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38827,23 +31933,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyhus_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vmpyhus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyhus_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyhus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38851,23 +31945,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyhv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyhv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vmpy($Vu32.h,$Vv32.h)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -38876,25 +31957,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyhv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyhv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vmpy($Vu32.h,$Vv32.h)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -38904,25 +31970,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyhv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32 += vmpyh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyhv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38931,23 +31983,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyhv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vmpyh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyhv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -38955,23 +31995,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyhvsrs : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyhvsrs_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -38980,22 +32007,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyhvsrs_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyhvsrs_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39003,23 +32018,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyieoh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)", -CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyieoh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)", CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39028,25 +32030,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyiewh_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyiewh_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyie($Vu32.w,$Vv32.h)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39056,25 +32043,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyiewh_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32 += vmpyiewh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyiewh_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyiewh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39083,24 +32056,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyiewuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyiewuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39109,25 +32069,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyiewuh_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyiewuh_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -39137,50 +32082,24 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyiewuh_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32 += vmpyiewuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyiewuh_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vx32 += vmpyiewuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyiewuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmpyiewuh($Vu32,$Vv32)", +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), +"$Vx32 += vmpyiewuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; let opNewValue = 0; +let isAccumulator = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiewuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +def V6_vmpyiewuh_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyiewuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39188,23 +32107,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyih : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyih_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmpyi($Vu32.h,$Vv32.h)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -39213,25 +32119,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyih_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyih_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.h += vmpyi($Vu32.h,$Vv32.h)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -39241,25 +32132,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyih_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32 += vmpyih($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyih_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyih($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39268,23 +32145,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyih_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmpyih($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyih_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyih($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39292,23 +32157,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyihb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)", -CVI_VX_LONG, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyihb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vmpyi($Vu32.h,$Rt32.b)", CVI_VX_LONG, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39317,25 +32169,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyihb_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)", -CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyihb_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.h += vmpyi($Vu32.h,$Rt32.b)", CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -39345,25 +32182,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyihb_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32 += vmpyihb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyihb_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyihb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39372,12 +32195,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyihb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyihb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39386,33 +32208,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyihb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyihb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiowh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyiowh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyio($Vu32.w,$Vv32.h)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -39421,22 +32219,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyiowh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmpyiowh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyiowh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyiowh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39444,23 +32230,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyiwb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)", -CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyiwb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vmpyi($Vu32.w,$Rt32.b)", CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39469,25 +32242,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyiwb_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)", -CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyiwb_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vmpyi($Vu32.w,$Rt32.b)", CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -39497,25 +32255,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyiwb_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32 += vmpyiwb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyiwb_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyiwb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39524,23 +32268,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyiwb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyiwb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyiwb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyiwb($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39548,23 +32280,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyiwh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyiwh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vmpyi($Vu32.w,$Rt32.h)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -39573,11 +32292,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyiwh_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vmpyi($Vu32.w,$Rt32.h)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -39589,37 +32307,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vmpyiwh_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vmpyiwh_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32 += vmpyiwh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyiwh_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyiwh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39628,23 +32318,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyiwh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyiwh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyiwh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyiwh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39652,11 +32330,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyiwub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)", CVI_VX_LONG, TypeCVI_VX>, Enc_16214129, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b110; @@ -39666,36 +32343,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vmpyiwub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)", -CVI_VX_LONG, TypeCVI_VX>, Enc_16214129, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vmpyiwub_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)", -CVI_VX_LONG, TypeCVI_VX>, Enc_10058269, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyiwub_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)", CVI_VX_LONG, TypeCVI_VX>, Enc_10058269, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -39705,25 +32355,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyiwub_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32 += vmpyiwub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyiwub_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyiwub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -39732,23 +32368,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyiwub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vmpyiwub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyiwub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyiwub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -39756,50 +32380,22 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyowh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyowh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vmpyowh_64_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; -let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vmpyowh_64_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +def V6_vmpyowh_64_acc : HInst< +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyo($Vu32.w,$Vv32.h)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -39809,23 +32405,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyowh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyowh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39833,23 +32417,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyowh_rnd : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyowh_rnd_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat", CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -39858,22 +32429,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyowh_rnd_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyowh_rnd_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39881,25 +32440,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyowh_rnd_sacc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyowh_rnd_sacc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -39909,24 +32453,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyowh_rnd_sacc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyowh_rnd_sacc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39934,26 +32465,11 @@ let isAccumulator = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyowh_sacc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyowh_sacc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -39963,24 +32479,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyowh_sacc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vmpyowh_sacc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -39988,24 +32491,11 @@ let isAccumulator = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vmpyub : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyub_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -40014,25 +32504,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyub_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001100; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyub_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -40042,25 +32517,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyub_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vxx32 += vmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyub_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpyub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40069,23 +32530,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyub_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vdd32 = vmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyub_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpyub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40093,23 +32542,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyubv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyubv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -40118,25 +32554,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyubv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyubv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -40146,25 +32567,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyubv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32 += vmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyubv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40173,23 +32580,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyubv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyubv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40197,23 +32592,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyuh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyuh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -40222,25 +32604,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyuh_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyuh_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -40250,25 +32617,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyuh_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vxx32 += vmpyuh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyuh_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpyuh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40277,23 +32630,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyuh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vdd32 = vmpyuh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyuh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpyuh($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40301,23 +32642,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyuhv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyuhv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -40326,25 +32654,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vmpyuhv_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyuhv_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -40354,25 +32667,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyuhv_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vxx32 += vmpyuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vmpyuhv_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40381,23 +32680,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vmpyuhv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vmpyuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vmpyuhv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40405,23 +32692,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vmux : HInst< -(outs VectorRegs:$Vd32), -(ins VecPredRegs:$Qt4, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vmux($Qt4,$Vu32,$Vv32)", -CVI_VA, TypeCVI_VA>, Enc_1572239, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011110111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; } -def V6_vmux_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VecPredRegs128B:$Qt4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +def V6_vmux : HInst< +(outs HvxVR:$Vd32), +(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmux($Qt4,$Vu32,$Vv32)", CVI_VA, TypeCVI_VA>, Enc_1572239, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -40430,23 +32704,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vnavgh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vnavg($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vnavgh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vnavg($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -40455,22 +32716,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vnavgh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vnavgh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vnavgh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vnavgh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40478,23 +32727,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vnavgub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vnavgub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -40503,22 +32739,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vnavgub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vnavgub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vnavgub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vnavgub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40526,23 +32750,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vnavgw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vnavg($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vnavgw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vnavg($Vu32.w,$Vv32.w)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -40551,22 +32762,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vnavgw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vnavgw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vnavgw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vnavgw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40574,25 +32773,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vnccombine : HInst< -(outs VecDblRegs:$Vdd32), -(ins PredRegs:$Ps4, VectorRegs:$Vu32, VectorRegs:$Vv32), -"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011010010; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vnccombine_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins PredRegs:$Ps4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32), "if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -40603,25 +32787,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vncmov : HInst< -(outs VectorRegs:$Vd32), -(ins PredRegs:$Ps4, VectorRegs:$Vu32), -"if (!$Ps4) $Vd32 = $Vu32", -CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001101000100000; -let isPredicated = 1; -let isPredicatedFalse = 1; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vncmov_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins PredRegs:$Ps4, VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins PredRegs:$Ps4, HvxVR:$Vu32), "if (!$Ps4) $Vd32 = $Vu32", CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -40632,23 +32801,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vnormamth : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32.h = vnormamt($Vu32.h)", -CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vnormamth_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vnormamt($Vu32.h)", CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -40657,22 +32813,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vnormamth_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vnormamth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vnormamth_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vnormamth($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40680,23 +32824,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vnormamtw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32.w = vnormamt($Vu32.w)", -CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vnormamtw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.w = vnormamt($Vu32.w)", CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -40705,11 +32836,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vnormamtw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vnormamtw($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40718,33 +32848,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vnormamtw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), -"$Vd32 = vnormamtw($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vnot : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vnot($Vu32)", -CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vnot_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vnot($Vu32)", CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -40753,23 +32859,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vor : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vor($Vu32,$Vv32)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vor_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vor($Vu32,$Vv32)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -40778,23 +32871,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackeb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.b = vpacke($Vu32.h,$Vv32.h)", -CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackeb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vpacke($Vu32.h,$Vv32.h)", CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -40803,22 +32883,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackeb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vpackeb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackeb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackeb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40826,11 +32894,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackeh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vpacke($Vu32.w,$Vv32.w)", CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -40840,33 +32907,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackeh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vpacke($Vu32.w,$Vv32.w)", -CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackeh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vpackeh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackeh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackeh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40874,23 +32917,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackhb_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat", -CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackhb_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vpack($Vu32.h,$Vv32.h):sat", CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -40899,22 +32929,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackhb_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vpackhb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackhb_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackhb($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40922,23 +32940,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackhub_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat", -CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackhub_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat", CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -40947,11 +32952,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackhub_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackhub($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -40960,33 +32964,9 @@ let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackhub_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vpackhub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vpackob : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.b = vpacko($Vu32.h,$Vv32.h)", -CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackob_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vpacko($Vu32.h,$Vv32.h)", CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -40995,22 +32975,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackob_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vpackob($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackob_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackob($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41018,47 +32986,22 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackoh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vpacko($Vu32.w,$Vv32.w)", -CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackoh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vpacko($Vu32.w,$Vv32.w)", CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vpackoh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vpackoh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vpackoh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +def V6_vpackoh_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackoh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41066,23 +33009,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackwh_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat", -CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackwh_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vpack($Vu32.w,$Vv32.w):sat", CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -41091,22 +33021,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackwh_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vpackwh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackwh_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackwh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41114,23 +33032,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackwuh_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat", -CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackwuh_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat", CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -41139,22 +33044,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpackwuh_sat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vpackwuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpackwuh_sat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackwuh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41162,23 +33055,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpopcounth : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32.h = vpopcount($Vu32.h)", -CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpopcounth_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vpopcount($Vu32.h)", CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -41187,22 +33067,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vpopcounth_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vpopcounth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vpopcounth_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vpopcounth($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41210,11 +33078,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrdelta : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrdelta($Vu32,$Vv32)", CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -41224,34 +33091,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrdelta_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vrdelta($Vu32,$Vv32)", -CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpybus : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)", -CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpybus_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)", CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -41260,25 +33102,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrmpybus_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)", -CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vrmpybus_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)", CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -41288,12 +33115,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vrmpybus_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vrmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41304,34 +33130,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vrmpybus_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), -"$Vx32 += vrmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} def V6_vrmpybus_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vrmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpybus_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vrmpybus($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41339,23 +33140,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrmpybusi : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b10; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpybusi_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b10; @@ -41364,25 +33152,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrmpybusi_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b10; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vrmpybusi_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b10; @@ -41392,25 +33165,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vrmpybusi_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vrmpybusi_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41419,23 +33178,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vrmpybusi_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpybusi_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41443,23 +33190,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrmpybusv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)", -CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpybusv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)", CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -41468,25 +33202,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrmpybusv_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vrmpybusv_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -41496,25 +33215,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vrmpybusv_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32 += vrmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vrmpybusv_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vrmpybus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41523,23 +33228,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vrmpybusv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vrmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpybusv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrmpybus($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41547,23 +33240,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrmpybv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)", -CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpybv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vrmpy($Vu32.b,$Vv32.b)", CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -41572,25 +33252,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrmpybv_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vrmpybv_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vrmpy($Vu32.b,$Vv32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -41600,25 +33265,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vrmpybv_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32 += vrmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vrmpybv_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vrmpyb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41627,47 +33278,22 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vrmpybv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vrmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpybv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32 = vrmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vrmpyub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)", -CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32 = vrmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpyub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +def V6_vrmpyub : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)", CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -41676,25 +33302,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrmpyub_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)", -CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vrmpyub_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)", CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -41704,25 +33315,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vrmpyub_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vx32 += vrmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vrmpyub_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vrmpyub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41731,23 +33328,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vrmpyub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vrmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpyub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vrmpyub($Vu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41755,23 +33340,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrmpyubi : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b11; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpyubi_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b11; @@ -41780,11 +33352,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrmpyubi_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b11; @@ -41796,37 +33367,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vrmpyubi_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b11; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vrmpyubi_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vrmpyubi_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41835,23 +33378,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vrmpyubi_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpyubi_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41859,11 +33390,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrmpyubv : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)", CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -41873,36 +33403,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vrmpyubv_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)", -CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vrmpyubv_acc : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vrmpyubv_acc_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -41912,25 +33415,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vrmpyubv_acc_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vx32 += vrmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vrmpyubv_acc_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vrmpyub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41939,23 +33428,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vrmpyubv_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vrmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrmpyubv_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrmpyub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -41963,23 +33440,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vror : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, IntRegs:$Rt32), -"$Vd32 = vror($Vu32,$Rt32)", -CVI_VP, TypeCVI_VP>, Enc_16214129, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vror_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vror($Vu32,$Rt32)", CVI_VP, TypeCVI_VP>, Enc_16214129, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -41988,23 +33452,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vroundhb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.b = vround($Vu32.h,$Vv32.h):sat", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vroundhb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vround($Vu32.h,$Vv32.h):sat", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -42013,22 +33464,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vroundhb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vroundhb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vroundhb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundhb($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42036,23 +33475,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vroundhub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vroundhub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vround($Vu32.h,$Vv32.h):sat", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -42061,22 +33487,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vroundhub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vroundhub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vroundhub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundhub($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42084,23 +33498,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrounduhub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrounduhub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -42109,22 +33510,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrounduhub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vrounduhub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrounduhub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrounduhub($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -42132,23 +33521,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrounduwuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111111; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrounduwuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -42157,22 +33533,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrounduwuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vrounduwuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrounduwuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrounduwuh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -42180,11 +33544,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vroundwh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vround($Vu32.w,$Vv32.w):sat", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -42194,33 +33557,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vroundwh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.h = vround($Vu32.w,$Vv32.w):sat", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vroundwh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vroundwh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vroundwh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundwh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42228,23 +33567,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vroundwuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat", -CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vroundwuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vround($Vu32.w,$Vv32.w):sat", CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -42253,22 +33579,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vroundwuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vroundwuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vroundwuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundwuh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42276,23 +33590,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vrsadubi : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b11; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; } -def V6_vrsadubi_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +def V6_vrsadubi : HInst< +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b11; @@ -42301,25 +33602,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vrsadubi_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", -CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { -let Inst{7-6} = 0b11; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001010; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vrsadubi_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { let Inst{7-6} = 0b11; @@ -42329,25 +33615,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vrsadubi_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vrsadubi_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42356,23 +33628,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vrsadubi_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), -"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vrsadubi_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42380,23 +33640,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsathub : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vsat($Vu32.h,$Vv32.h)", -CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsathub_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vsat($Vu32.h,$Vv32.h)", CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -42405,22 +33652,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsathub_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsathub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsathub_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsathub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42428,23 +33663,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsatuwuh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsatuwuh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b110; @@ -42453,22 +33675,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsatuwuh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsatuwuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsatuwuh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsatuwuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -42476,23 +33686,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsatwh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vsat($Vu32.w,$Vv32.w)", -CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsatwh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vsat($Vu32.w,$Vv32.w)", CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -42501,22 +33698,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsatwh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsatwh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsatwh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsatwh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42524,23 +33709,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32.h = vsxt($Vu32.b)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.h = vsxt($Vu32.b)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -42549,22 +33721,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32 = vsxtb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vsxtb($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42572,23 +33732,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32.w = vsxt($Vu32.h)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.w = vsxt($Vu32.h)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -42597,22 +33744,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32 = vsxth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vsxth($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42620,23 +33755,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshufeh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshufeh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vshuffe($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -42645,22 +33767,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshufeh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vshuffeh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshufeh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffeh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42668,26 +33778,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshuff : HInst< -(outs VectorRegs:$Vy32, VectorRegs:$Vx32), -(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), -"vshuff($Vy32,$Vx32,$Rt32)", -CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001111; -let hasNewValue = 1; -let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; -} -def V6_vshuff_128B : HInst< -(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), +(outs HvxVR:$Vy32, HvxVR:$Vx32), +(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), "vshuff($Vy32,$Vx32,$Rt32)", CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -42698,24 +33792,11 @@ let hasNewValue2 = 1; let opNewValue2 = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; } def V6_vshuffb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32.b = vshuff($Vu32.b)", -CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshuffb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.b = vshuff($Vu32.b)", CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -42724,22 +33805,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshuffb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vshuffb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshuffb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vshuffb($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42747,23 +33816,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshuffeb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshuffeb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vshuffe($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -42772,22 +33828,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshuffeb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vshuffeb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshuffeb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffeb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42795,23 +33839,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshuffh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32.h = vshuff($Vu32.h)", -CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshuffh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32.h = vshuff($Vu32.h)", CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -42820,22 +33851,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshuffh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32), -"$Vd32 = vshuffh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshuffh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), "$Vd32 = vshuffh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42843,23 +33862,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshuffob : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshuffob_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vshuffo($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -42868,22 +33874,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshuffob_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vshuffob($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshuffob_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffob($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42891,23 +33885,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshuffvdd : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), -"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)", -CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{31-24} = 0b00011011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshuffvdd_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)", CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -42916,23 +33897,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshufoeb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshufoeb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -42941,22 +33909,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshufoeb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vshuffoeb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshufoeb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vshuffoeb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -42964,23 +33920,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshufoeh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshufoeh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -42989,22 +33932,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshufoeh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vshuffoeh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshufoeh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vshuffoeh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43012,23 +33943,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshufoh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshufoh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vshuffo($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -43037,22 +33955,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vshufoh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vshuffoh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vshufoh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffoh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43060,11 +33966,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubb : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vsub($Vu32.b,$Vv32.b)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -43074,33 +33979,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubb_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.b = vsub($Vu32.b,$Vv32.b)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vsubb_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsubb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubb_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubb($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43108,23 +33989,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubb_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubb_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -43133,22 +34001,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubb_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vsubb($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubb_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vsubb($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43156,25 +34012,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubbnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if (!$Qv4) $Vx32.b -= $Vu32.b", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubbnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.b -= $Vu32.b", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -43184,24 +34025,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vsubbnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if (!$Qv4.b) $Vx32.b -= $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubbnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.b) $Vx32.b -= $Vu32.b", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43209,26 +34037,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vsubbq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if ($Qv4) $Vx32.b -= $Vu32.b", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubbq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.b -= $Vu32.b", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -43238,24 +34051,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vsubbq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if ($Qv4.b) $Vx32.b -= $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubbq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.b) $Vx32.b -= $Vu32.b", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43263,24 +34063,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vsubbsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubbsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vsub($Vu32.b,$Vv32.b):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b010; @@ -43289,22 +34076,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubbsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsubb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubbsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubb($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -43312,23 +34087,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubbsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubbsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b001; @@ -43337,22 +34099,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubbsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vsubb($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubbsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vsubb($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -43360,26 +34110,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubcarry : HInst< -(outs VectorRegs:$Vd32, VecPredRegs:$Qx4), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32, VecPredRegs:$Qx4in), -"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry", -CVI_VA, TypeCVI_VA>, Enc_13691337, Requires<[HasV62T,UseHVX]> { -let Inst{7-7} = 0b1; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; -} -def V6_vsubcarry_128B : HInst< -(outs VectorRegs128B:$Vd32, VecPredRegs128B:$Qx4), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, VecPredRegs128B:$Qx4in), +(outs HvxVR:$Vd32, HvxQR:$Qx4), +(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in), "$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry", CVI_VA, TypeCVI_VA>, Enc_13691337, Requires<[HasV62T,UseHVX]> { let Inst{7-7} = 0b1; @@ -43390,24 +34124,11 @@ let hasNewValue2 = 1; let opNewValue2 = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Qx4 = $Qx4in"; } def V6_vsubh : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vsub($Vu32.h,$Vv32.h)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubh_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vsub($Vu32.h,$Vv32.h)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -43416,22 +34137,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubh_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsubh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubh_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43439,23 +34148,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubh_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubh_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -43464,22 +34160,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubh_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vsubh($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubh_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vsubh($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43487,25 +34171,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubhnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if (!$Qv4) $Vx32.h -= $Vu32.h", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubhnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.h -= $Vu32.h", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -43515,51 +34184,23 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vsubhnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if (!$Qv4.h) $Vx32.h -= $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubhnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.h) $Vx32.h -= $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubhq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if ($Qv4) $Vx32.h -= $Vu32.h", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000001; -let Inst{31-24} = 0b00011110; +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } -def V6_vsubhq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +def V6_vsubhq : HInst< +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.h -= $Vu32.h", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -43569,24 +34210,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vsubhq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if ($Qv4.h) $Vx32.h -= $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubhq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.h) $Vx32.h -= $Vu32.h", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43594,24 +34222,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vsubhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vsub($Vu32.h,$Vv32.h):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -43620,22 +34235,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsubh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubhsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43643,23 +34246,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubhsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubhsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -43668,22 +34258,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubhsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vsubh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubhsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vsubh($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43691,23 +34269,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubhw : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.w = vsub($Vu32.h,$Vv32.h)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubhw_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vsub($Vu32.h,$Vv32.h)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -43716,22 +34281,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubhw_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vsubh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubhw_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vsubh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43739,23 +34292,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsububh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsububh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -43764,22 +34304,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsububh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vsubub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsububh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vsubub($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43787,23 +34315,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsububsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsububsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -43812,22 +34327,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsububsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsubub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsububsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubub($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43835,23 +34338,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsububsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsububsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -43860,22 +34350,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsububsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vsubub($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsububsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vsubub($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43883,23 +34361,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubububb_sat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubububb_sat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b101; @@ -43908,23 +34373,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubuhsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubuhsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -43933,22 +34385,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubuhsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsubuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubuhsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubuh($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -43956,23 +34396,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubuhsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubuhsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -43981,22 +34408,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubuhsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubuhsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44004,23 +34419,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubuhw : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b110; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubuhw_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b110; @@ -44029,22 +34431,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubuhw_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vsubuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubuhw_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vsubuh($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44052,23 +34442,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubuwsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011111110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubuwsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b100; @@ -44077,22 +34454,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubuwsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsubuw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubuwsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubuw($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -44100,23 +34465,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubuwsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubuwsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { let Inst{7-5} = 0b011; @@ -44125,22 +34477,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubuwsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubuwsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vsubuw($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { let hasNewValue = 1; @@ -44148,47 +34488,22 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubw : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vsub($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubw_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), -"$Vd32.w = vsub($Vu32.w,$Vv32.w)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} -def V6_vsubw_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsubw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32.w = vsub($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vsubw_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +def V6_vsubw_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubw($Vu32,$Vv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44196,23 +34511,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubw_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b101; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubw_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b101; @@ -44221,22 +34523,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubw_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vsubw($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubw_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vsubw($Vuu32,$Vvv32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44244,25 +34534,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubwnq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if (!$Qv4) $Vx32.w -= $Vu32.w", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubwnq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.w -= $Vu32.w", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -44272,24 +34547,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vsubwnq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if (!$Qv4.w) $Vx32.w -= $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubwnq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.w) $Vx32.w -= $Vu32.w", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44297,26 +34559,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vsubwq : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if ($Qv4) $Vx32.w -= $Vu32.w", -CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubwq_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.w -= $Vu32.w", CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -44326,24 +34573,11 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vsubwq_alt : HInst< -(outs VectorRegs:$Vx32), -(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), -"if ($Qv4.w) $Vx32.w -= $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vx32 = $Vx32in"; -} -def V6_vsubwq_alt_128B : HInst< -(outs VectorRegs128B:$Vx32), -(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +(outs HvxVR:$Vx32), +(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.w) $Vx32.w -= $Vu32.w", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44351,24 +34585,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vx32 = $Vx32in"; } def V6_vsubwsat : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100011; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubwsat_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vsub($Vu32.w,$Vv32.w):sat", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -44377,22 +34598,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubwsat_alt : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vsubw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubwsat_alt_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubw($Vu32,$Vv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44400,23 +34609,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubwsat_dv : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubwsat_dv_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat", CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -44425,22 +34621,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vsubwsat_dv_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), -"$Vdd32 = vsubw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vsubwsat_dv_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, HvxVP:$Vvv32), "$Vdd32 = vsubw($Vuu32,$Vvv32):sat", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44448,23 +34632,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vswap : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecPredRegs:$Qt4, VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_11424254, Requires<[HasV60T,UseHVX]> { -let Inst{7-7} = 0b0; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011110101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vswap_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecPredRegs128B:$Qt4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVP:$Vdd32), +(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vswap($Qt4,$Vu32,$Vv32)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_11424254, Requires<[HasV60T,UseHVX]> { let Inst{7-7} = 0b0; @@ -44473,23 +34644,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vtmpyb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vtmpyb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -44498,25 +34656,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vtmpyb_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vtmpyb_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -44526,25 +34669,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vtmpyb_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vtmpyb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vtmpyb_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vtmpyb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44553,23 +34682,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vtmpyb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vtmpyb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vtmpyb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vtmpyb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44577,23 +34694,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vtmpybus : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vtmpybus_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -44602,25 +34706,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vtmpybus_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vtmpybus_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -44630,25 +34719,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vtmpybus_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vtmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vtmpybus_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vtmpybus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44657,23 +34732,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vtmpybus_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vtmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vtmpybus_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vtmpybus($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44681,23 +34744,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vtmpyhb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b100; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011001101; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vtmpyhb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b100; @@ -44706,25 +34756,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vtmpyhb_acc : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)", -CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b1; -let Inst{31-21} = 0b00011001000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vtmpyhb_acc_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)", CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -44734,25 +34769,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vtmpyhb_acc_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vxx32 += vtmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vtmpyhb_acc_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVP:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vtmpyhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44761,49 +34782,22 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vtmpyhb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vtmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vtmpyhb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), -"$Vdd32 = vtmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vtran2x2_map : HInst< -(outs VectorRegs:$Vy32, VectorRegs:$Vx32), -(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), -"vtrans2x2($Vy32,$Vx32,$Rt32)", +def V6_vtmpyhb_alt : HInst< +(outs HvxVP:$Vdd32), +(ins HvxVP:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpyhb($Vuu32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; } -def V6_vtran2x2_map_128B : HInst< -(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), -(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), +def V6_vtran2x2_map : HInst< +(outs HvxVR:$Vy32, HvxVR:$Vx32), +(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), "vtrans2x2($Vy32,$Vx32,$Rt32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44813,24 +34807,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; } def V6_vunpackb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32.h = vunpack($Vu32.b)", -CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vunpackb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.h = vunpack($Vu32.b)", CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -44839,22 +34820,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vunpackb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32 = vunpackb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vunpackb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vunpackb($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44862,23 +34831,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vunpackh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32.w = vunpack($Vu32.h)", -CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b011; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vunpackh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.w = vunpack($Vu32.h)", CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b011; @@ -44887,22 +34843,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vunpackh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32 = vunpackh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vunpackh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vunpackh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44910,11 +34854,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vunpackob : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32), "$Vxx32.h |= vunpacko($Vu32.b)", CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -44926,36 +34869,9 @@ let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } -def V6_vunpackob_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), -"$Vxx32.h |= vunpacko($Vu32.b)", -CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b1; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -let Constraints = "$Vxx32 = $Vxx32in"; -} def V6_vunpackob_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), -"$Vxx32 |= vunpackob($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vunpackob_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32), "$Vxx32 |= vunpackob($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -44963,26 +34879,11 @@ let isAccumulator = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vunpackoh : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), -"$Vxx32.w |= vunpacko($Vu32.h)", -CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b1; -let Inst{31-16} = 0b0001111000000000; -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vunpackoh_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32), "$Vxx32.w |= vunpacko($Vu32.h)", CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -44992,25 +34893,11 @@ let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vunpackoh_alt : HInst< -(outs VecDblRegs:$Vxx32), -(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), -"$Vxx32 |= vunpackoh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isAccumulator = 1; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Vxx32 = $Vxx32in"; -} -def V6_vunpackoh_alt_128B : HInst< -(outs VecDblRegs128B:$Vxx32), -(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), +(outs HvxVP:$Vxx32), +(ins HvxVP:$Vxx32in, HvxVR:$Vu32), "$Vxx32 |= vunpackoh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45019,24 +34906,11 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; let Constraints = "$Vxx32 = $Vxx32in"; } def V6_vunpackub : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32.uh = vunpack($Vu32.ub)", -CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b000; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vunpackub_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.uh = vunpack($Vu32.ub)", CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b000; @@ -45045,22 +34919,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vunpackub_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32 = vunpackub($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vunpackub_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vunpackub($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45068,11 +34930,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vunpackuh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.uw = vunpack($Vu32.uh)", CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -45082,33 +34943,9 @@ let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } -def V6_vunpackuh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), -"$Vdd32.uw = vunpack($Vu32.uh)", -CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vunpackuh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32 = vunpackuh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vunpackuh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vunpackuh($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45116,7 +34953,6 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vwhist128 : HInst< (outs), @@ -45127,16 +34963,6 @@ let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist128_128B : HInst< -(outs), -(ins), -"vwhist128", -CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10010010000000; -let Inst{31-16} = 0b0001111000000000; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist128m : HInst< (outs), (ins u1_0Imm:$Ii), @@ -45147,52 +34973,19 @@ let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist128m_128B : HInst< -(outs), -(ins u1_0Imm:$Ii), -"vwhist128(#$Ii)", -CVI_HIST, TypeCVI_HIST>, Enc_1291652, Requires<[HasV62T,UseHVX]> { -let Inst{7-0} = 0b10000000; -let Inst{13-9} = 0b10011; -let Inst{31-16} = 0b0001111000000000; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist128q : HInst< (outs), -(ins VecPredRegs:$Qv4), -"vwhist128($Qv4)", -CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10010010000000; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vwhist128q_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4), +(ins HvxQR:$Qv4), "vwhist128($Qv4)", CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { let Inst{13-0} = 0b10010010000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vwhist128qm : HInst< (outs), -(ins VecPredRegs:$Qv4, u1_0Imm:$Ii), -"vwhist128($Qv4,#$Ii)", -CVI_HIST, TypeCVI_HIST>, Enc_7978128, Requires<[HasV62T,UseHVX]> { -let Inst{7-0} = 0b10000000; -let Inst{13-9} = 0b10011; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vwhist128qm_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4, u1_0Imm:$Ii), +(ins HvxQR:$Qv4, u1_0Imm:$Ii), "vwhist128($Qv4,#$Ii)", CVI_HIST, TypeCVI_HIST>, Enc_7978128, Requires<[HasV62T,UseHVX]> { let Inst{7-0} = 0b10000000; @@ -45200,7 +34993,6 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vwhist256 : HInst< (outs), @@ -45211,16 +35003,6 @@ let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist256_128B : HInst< -(outs), -(ins), -"vwhist256", -CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10001010000000; -let Inst{31-16} = 0b0001111000000000; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist256_sat : HInst< (outs), (ins), @@ -45230,73 +35012,29 @@ let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; } -def V6_vwhist256_sat_128B : HInst< -(outs), -(ins), -"vwhist256:sat", -CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10001110000000; -let Inst{31-16} = 0b0001111000000000; -let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; -} def V6_vwhist256q : HInst< (outs), -(ins VecPredRegs:$Qv4), -"vwhist256($Qv4)", -CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10001010000000; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vwhist256q_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4), +(ins HvxQR:$Qv4), "vwhist256($Qv4)", CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { let Inst{13-0} = 0b10001010000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vwhist256q_sat : HInst< (outs), -(ins VecPredRegs:$Qv4), -"vwhist256($Qv4):sat", -CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { -let Inst{13-0} = 0b10001110000000; -let Inst{21-16} = 0b000010; -let Inst{31-24} = 0b00011110; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vwhist256q_sat_128B : HInst< -(outs), -(ins VecPredRegs128B:$Qv4), +(ins HvxQR:$Qv4), "vwhist256($Qv4):sat", CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { let Inst{13-0} = 0b10001110000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vxor : HInst< -(outs VectorRegs:$Vd32), -(ins VectorRegs:$Vu32, VectorRegs:$Vv32), -"$Vd32 = vxor($Vu32,$Vv32)", -CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b111; -let Inst{13-13} = 0b0; -let Inst{31-21} = 0b00011100001; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vxor_128B : HInst< -(outs VectorRegs128B:$Vd32), -(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vxor($Vu32,$Vv32)", CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b111; @@ -45305,23 +35043,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vzb : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32.uh = vzxt($Vu32.ub)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b001; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vzb_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.uh = vzxt($Vu32.ub)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b001; @@ -45330,22 +35055,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vzb_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32 = vzxtb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vzb_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vzxtb($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45353,23 +35066,10 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vzh : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32.uw = vzxt($Vu32.uh)", -CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { -let Inst{7-5} = 0b010; -let Inst{13-13} = 0b0; -let Inst{31-16} = 0b0001111000000010; -let hasNewValue = 1; -let opNewValue = 0; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vzh_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32.uw = vzxt($Vu32.uh)", CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { let Inst{7-5} = 0b010; @@ -45378,22 +35078,10 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def V6_vzh_alt : HInst< -(outs VecDblRegs:$Vdd32), -(ins VectorRegs:$Vu32), -"$Vdd32 = vzxth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -let DecoderNamespace = "EXT_mmvec"; -} -def V6_vzh_alt_128B : HInst< -(outs VecDblRegs128B:$Vdd32), -(ins VectorRegs128B:$Vu32), +(outs HvxVP:$Vdd32), +(ins HvxVR:$Vu32), "$Vdd32 = vzxth($Vu32)", PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { let hasNewValue = 1; @@ -45401,7 +35089,6 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; -let isCodeGenOnly = 1; } def Y2_barrier : HInst< (outs), @@ -45542,7 +35229,8 @@ (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add($Rs32,$Rt32):sat:deprecated", -ALU64_tc_2_SLOT23, TypeALU64>, Enc_14071773 { +ALU64_tc_2_SLOT23, TypeALU64>, +Enc_14071773 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101100; @@ -45554,7 +35242,8 @@ (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32,$Rs32):sat:deprecated", -ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +ALU64_tc_2_SLOT23, TypeALU64>, +Enc_8605375 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101100; @@ -45566,7 +35255,8 @@ (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = packhl($Rs32,$Rt32):deprecated", -ALU64_tc_1_SLOT23, TypeALU64>, Enc_1997594 { +ALU64_tc_1_SLOT23, TypeALU64>, +Enc_1997594 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010100000; Index: lib/Target/Hexagon/HexagonDepMappings.td =================================================================== --- lib/Target/Hexagon/HexagonDepMappings.td +++ lib/Target/Hexagon/HexagonDepMappings.td @@ -140,515 +140,263 @@ def S4_storeirifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=#$II", (S4_storeirifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; def S4_storeirit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=#$II", (S4_storeirit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; def S4_storeiritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=#$II", (S4_storeiritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def V6_MAP_equbAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equhAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equwAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_extractw_altAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; -def V6_extractw_alt_128BAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; -def V6_ld0Alias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ld0_128BAlias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ldnt0Alias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ldnt0_128BAlias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ldu0Alias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ldu0_128BAlias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_st0Alias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_st0_128BAlias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stn0Alias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; -def V6_stn0_128BAlias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; -def V6_stnnt0Alias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; -def V6_stnnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; -def V6_stnp0Alias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnp0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnpnt0Alias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnpnt0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnq0Alias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnq0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnqnt0Alias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnqnt0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnt0Alias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stp0Alias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stp0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stpnt0Alias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stpnt0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stq0Alias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stq0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stqnt0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stu0Alias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stu0_128BAlias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stunp0_128BAlias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_stup0_128BAlias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; -def V6_vabsdiffh_altAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffub_altAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffub_alt_128BAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffuh_altAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffuh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffw_altAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffw_alt_128BAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsh_altAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsh_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsh_sat_altAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsh_sat_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsuh_altAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsuh_alt_128BAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsuw_altAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsuw_alt_128BAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsw_altAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsw_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsw_sat_altAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsw_sat_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddb_altAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddb_alt_128BAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddb_dv_altAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddb_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddh_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddh_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddh_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddh_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddhsat_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddhsat_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddhsat_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddhw_altAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddhw_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubh_altAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubh_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubsat_altAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubsat_alt_128BAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubsat_dv_altAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddubsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vadduhsat_altAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vadduhsat_alt_128BAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vadduhsat_dv_altAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vadduhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vadduhw_altAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vadduhw_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddw_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddw_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddw_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddw_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddwsat_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddwsat_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddwsat_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vandqrt_acc_altAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandqrt_acc_alt_128BAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandqrt_altAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandqrt_alt_128BAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandvrt_acc_altAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandvrt_acc_alt_128BAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandvrt_altAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandvrt_alt_128BAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslh_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslh_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslhv_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaslhv_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaslw_acc_altAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslw_acc_alt_128BAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslw_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslw_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslwv_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vaslwv_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vasrh_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrh_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32=vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrhubsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrhv_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vasrhv_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vasrw_acc_altAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrw_acc_alt_128BAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrw_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrw_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrwh_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwhsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32=vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwv_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vasrwv_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgh_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgh_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavghrnd_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavghrnd_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgub_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgub_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgubrnd_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgubrnd_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavguh_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavguh_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavguhrnd_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavguhrnd_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgw_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgw_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgwrnd_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgwrnd_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vcl0h_altAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vcl0h_alt_128BAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vcl0w_altAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vcl0w_alt_128BAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vd0Alias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>; -def V6_vd0_128BAlias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>; -def V6_vdd0Alias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>; -def V6_vdd0_128BAlias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>; -def V6_vdealb4w_altAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdealb4w_alt_128BAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdealb_altAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vdealb_alt_128BAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vdealh_altAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vdealh_alt_128BAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vdmpybus_acc_altAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_altAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_alt_128BAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_dv_altAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_acc_altAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_altAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_alt_128BAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_dv_altAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhisat_altAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsuisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsuisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsuisat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsuisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsusat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsusat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsusat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsusat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhvsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdmpyhvsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdmpyhvsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdmpyhvsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vdsaduh_acc_altAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdsaduh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdsaduh_altAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdsaduh_alt_128BAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrh_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrh_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrhv_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vlsrhv_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vlsrw_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrw_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrwv_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vlsrwv_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxh_altAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxh_alt_128BAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxub_altAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxub_alt_128BAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxuh_altAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxuh_alt_128BAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxw_altAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxw_alt_128BAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminh_altAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminh_alt_128BAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminub_altAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminub_alt_128BAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminuh_altAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminuh_alt_128BAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminw_altAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vminw_alt_128BAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpabus_acc_altAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpabus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpabus_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpabus_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpabusv_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vmpabusv_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vmpabuuv_altAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vmpabuuv_alt_128BAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vmpahb_acc_altAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpahb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpahb_altAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpahb_alt_128BAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybus_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybus_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybus_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybusv_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybusv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybusv_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybusv_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybv_acc_altAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybv_altAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybv_alt_128BAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyewuh_altAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyh_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyh_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhsat_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhsat_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhss_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhss_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhus_acc_altAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhus_altAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhus_alt_128BAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhv_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhvsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhvsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewuh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewuh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewuh_altAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyih_acc_altAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyih_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyih_altAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyih_alt_128BAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyihb_acc_altAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyihb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyihb_altAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyihb_alt_128BAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiowh_altAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiowh_alt_128BAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiwb_acc_altAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwb_altAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwb_alt_128BAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwh_acc_altAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwh_altAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwh_alt_128BAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyowh_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyowh_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyowh_rnd_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyowh_rnd_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyub_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyub_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyub_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyub_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyubv_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyubv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyubv_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyubv_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyuh_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyuh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyuh_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyuh_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyuhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyuhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyuhv_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyuhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgh_altAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgh_alt_128BAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgub_altAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgub_alt_128BAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgw_altAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgw_alt_128BAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vnormamth_altAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vnormamth_alt_128BAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vnormamtw_altAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vnormamtw_alt_128BAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vpackeb_altAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackeb_alt_128BAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackeh_altAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackeh_alt_128BAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackhb_sat_altAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackhb_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackhub_sat_altAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackhub_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackob_altAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackob_alt_128BAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackoh_altAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackoh_alt_128BAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackwh_sat_altAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackwh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackwuh_sat_altAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackwuh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vpopcounth_altAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vpopcounth_alt_128BAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vrmpybus_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpybus_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpybus_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpybusi_acc_altAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpybusi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpybusi_altAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpybusi_alt_128BAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpybusv_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybusv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybusv_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybusv_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybv_acc_altAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybv_altAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybv_alt_128BAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpyub_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpyub_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpyub_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpyub_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpyubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpyubi_alt_128BAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpyubv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpyubv_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpyubv_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundhb_altAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundhb_alt_128BAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundhub_altAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundhub_alt_128BAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundwh_altAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundwh_alt_128BAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundwuh_altAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundwuh_alt_128BAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vrsadubi_acc_altAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrsadubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrsadubi_altAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrsadubi_alt_128BAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vsathub_altAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsathub_alt_128BAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsatwh_altAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsatwh_alt_128BAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsb_altAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsb_alt_128BAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsh_altAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsh_alt_128BAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vshufeh_altAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufeh_alt_128BAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshuffb_altAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vshuffb_alt_128BAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vshuffeb_altAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshuffeb_alt_128BAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshuffh_altAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vshuffh_alt_128BAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vshuffob_altAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshuffob_alt_128BAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoeb_altAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoeb_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoeh_altAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoeh_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoh_altAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoh_alt_128BAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubb_altAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubb_alt_128BAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubb_dv_altAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubb_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubh_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubh_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubh_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubh_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubhsat_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubhsat_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubhsat_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubhw_altAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubhw_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububh_altAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububh_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububsat_altAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububsat_alt_128BAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububsat_dv_altAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsububsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubuhsat_altAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubuhsat_alt_128BAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubuhsat_dv_altAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubuhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubuhw_altAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubuhw_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubw_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubw_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubw_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubw_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubwsat_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubwsat_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubwsat_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; -def V6_vtmpyb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyb_altAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpybus_acc_altAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpybus_altAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpybus_alt_128BAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyhb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyhb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyhb_altAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyhb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtran2x2_mapAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtran2x2_map_128BAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vunpackb_altAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackb_alt_128BAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackh_altAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackh_alt_128BAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackoh_altAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackoh_alt_128BAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackub_altAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackub_alt_128BAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackuh_altAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackuh_alt_128BAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vzb_altAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vzb_alt_128BAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vzh_altAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; -def V6_vzh_alt_128BAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_MAP_equbAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equhAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equwAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_extractw_altAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, HvxVR:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; +def V6_ld0Alias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldnt0Alias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldu0Alias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_st0Alias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stn0Alias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8)>, Requires<[UseHVX]>; +def V6_stnnt0Alias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8)>, Requires<[UseHVX]>; +def V6_stnp0Alias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnpnt0Alias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnq0Alias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnqnt0Alias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnt0Alias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stp0Alias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stpnt0Alias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stq0Alias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stu0Alias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_vabsdiffh_altAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffub_altAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffuh_altAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffw_altAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsh_altAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsh_sat_altAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuh_altAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuw_altAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_altAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_sat_altAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddb_altAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddb_dv_altAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddh_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddh_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhsat_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddhsat_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhw_altAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubh_altAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_altAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_dv_altAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_altAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_dv_altAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhw_altAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddw_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddw_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwsat_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddwsat_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vandqrt_acc_altAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc HvxVR:$Vx32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandqrt_altAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt HvxVR:$Vd32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_acc_altAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc HvxQR:$Qx4, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_altAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt HvxQR:$Qd4, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslh_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslhv_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaslw_acc_altAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslw_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslwv_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrh_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32=vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhubsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhv_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrw_acc_altAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrw_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrwh_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwhsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32=vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwv_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgh_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavghrnd_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgub_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgubrnd_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguh_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguhrnd_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgw_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgwrnd_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vcl0h_altAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vcl0w_altAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vd0Alias : InstAlias<"$Vd32=#0", (V6_vxor HvxVR:$Vd32, HvxVR:$Vd32, HvxVR:$Vd32)>, Requires<[UseHVX]>; +def V6_vdd0Alias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv HvxVP:$Vdd32, W15, W15)>, Requires<[UseHVX]>; +def V6_vdealb4w_altAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vdealb_altAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vdealh_altAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vdmpybus_acc_altAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_altAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc HvxVP:$Vxx32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_altAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv HvxVP:$Vdd32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_acc_altAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_altAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc HvxVP:$Vxx32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_altAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv HvxVP:$Vdd32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc HvxVR:$Vx32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_altAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat HvxVR:$Vd32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc HvxVR:$Vx32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat HvxVR:$Vd32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vdsaduh_acc_altAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc HvxVP:$Vxx32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdsaduh_altAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh HvxVP:$Vdd32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrh_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrhv_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vlsrw_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrwv_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxh_altAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxub_altAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxuh_altAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxw_altAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminh_altAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminub_altAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminuh_altAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminw_altAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpabus_acc_altAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc HvxVP:$Vxx32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabus_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus HvxVP:$Vdd32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabusv_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpabuuv_altAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpahb_acc_altAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc HvxVP:$Vxx32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpahb_altAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb HvxVP:$Vdd32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc HvxVP:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus HvxVP:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybusv_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc HvxVP:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybusv_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_acc_altAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc HvxVP:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_altAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyewuh_altAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyh_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh HvxVP:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsat_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc HvxVP:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhss_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhus_acc_altAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc HvxVP:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhus_altAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc HvxVP:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhvsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_altAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_acc_altAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_altAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyihb_acc_altAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyihb_altAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiowh_altAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_acc_altAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_altAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_acc_altAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_altAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyowh_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyowh_rnd_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyub_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc HvxVP:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyub_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub HvxVP:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyubv_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc HvxVP:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyubv_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuh_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc HvxVP:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuh_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh HvxVP:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc HvxVP:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgh_altAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgub_altAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgw_altAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnormamth_altAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vnormamtw_altAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vpackeb_altAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackeh_altAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhb_sat_altAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhub_sat_altAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackob_altAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackoh_altAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwh_sat_altAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwuh_sat_altAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpopcounth_altAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vrmpybus_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybus_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybusi_acc_altAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc HvxVP:$Vxx32, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusi_altAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi HvxVP:$Vdd32, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusv_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybusv_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_acc_altAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_altAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyub_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyub_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc HvxVP:$Vxx32, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi HvxVP:$Vdd32, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyubv_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhb_altAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhub_altAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwh_altAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwuh_altAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrsadubi_acc_altAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc HvxVP:$Vxx32, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrsadubi_altAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi HvxVP:$Vdd32, HvxVP:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vsathub_altAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsatwh_altAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsb_altAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb HvxVP:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsh_altAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh HvxVP:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vshufeh_altAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffb_altAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffeb_altAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffh_altAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffob_altAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeb_altAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeh_altAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoh_altAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_altAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_dv_altAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubh_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubh_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhsat_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubhsat_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhw_altAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububh_altAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_altAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_dv_altAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_altAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_dv_altAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhw_altAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw HvxVP:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubw_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubw_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwsat_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubwsat_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv HvxVP:$Vdd32, HvxVP:$Vuu32, HvxVP:$Vvv32)>, Requires<[UseHVX]>; +def V6_vtmpyb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc HvxVP:$Vxx32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyb_altAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb HvxVP:$Vdd32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_acc_altAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc HvxVP:$Vxx32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_altAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus HvxVP:$Vdd32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc HvxVP:$Vxx32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_altAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb HvxVP:$Vdd32, HvxVP:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtran2x2_mapAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff HvxVR:$Vy32, HvxVR:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vunpackb_altAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb HvxVP:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackh_altAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh HvxVP:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackoh_altAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh HvxVP:$Vxx32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackub_altAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub HvxVP:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackuh_altAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh HvxVP:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vzb_altAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb HvxVP:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vzh_altAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh HvxVP:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; def Y2_dcfetchAlias : InstAlias<"dcfetch($Rs32)", (Y2_dcfetchbo IntRegs:$Rs32, 0)>; Index: lib/Target/Hexagon/HexagonEarlyIfConv.cpp =================================================================== --- lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -392,8 +392,7 @@ continue; switch (MRI->getRegClass(R)->getID()) { case Hexagon::PredRegsRegClassID: - case Hexagon::VecPredRegsRegClassID: - case Hexagon::VecPredRegs128BRegClassID: + case Hexagon::HvxQRRegClassID: break; default: continue; @@ -769,18 +768,12 @@ case Hexagon::DoubleRegsRegClassID: Opc = Hexagon::PS_pselect; break; - case Hexagon::VectorRegsRegClassID: + case Hexagon::HvxVRRegClassID: Opc = Hexagon::PS_vselect; break; - case Hexagon::VecDblRegsRegClassID: + case Hexagon::HvxVPRegClassID: Opc = Hexagon::PS_wselect; break; - case Hexagon::VectorRegs128BRegClassID: - Opc = Hexagon::PS_vselect_128B; - break; - case Hexagon::VecDblRegs128BRegClassID: - Opc = Hexagon::PS_wselect_128B; - break; default: llvm_unreachable("unexpected register type"); } Index: lib/Target/Hexagon/HexagonExpandCondsets.cpp =================================================================== --- lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -89,6 +89,7 @@ #define DEBUG_TYPE "expand-condsets" #include "HexagonInstrInfo.h" +#include "HexagonRegisterInfo.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallVector.h" Index: lib/Target/Hexagon/HexagonFrameLowering.cpp =================================================================== --- lib/Target/Hexagon/HexagonFrameLowering.cpp +++ lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -398,8 +398,7 @@ ShrinkCounter++; } - auto &HST = MF.getSubtarget(); - auto &HRI = *HST.getRegisterInfo(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); MachineDominatorTree MDT; MDT.runOnMachineFunction(MF); @@ -495,8 +494,7 @@ /// in one place allows shrink-wrapping of the stack frame. void HexagonFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { - auto &HST = MF.getSubtarget(); - auto &HRI = *HST.getRegisterInfo(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); const std::vector &CSI = MFI.getCalleeSavedInfo(); @@ -1564,7 +1562,6 @@ bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { - auto &HST = B.getParent()->getSubtarget(); MachineInstr *MI = &*It; if (!MI->getOperand(0).isFI()) return false; @@ -1573,10 +1570,7 @@ unsigned SrcR = MI->getOperand(2).getReg(); bool IsKill = MI->getOperand(2).isKill(); int FI = MI->getOperand(0).getIndex(); - - bool Is128B = HST.useHVXDblOps(); - auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass - : &Hexagon::VectorRegs128BRegClass; + auto *RC = &Hexagon::HvxVRRegClass; // Insert transfer to general vector register. // TmpR0 = A2_tfrsi 0x01010101 @@ -1588,8 +1582,7 @@ BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0) .addImm(0x01010101); - unsigned VandOpc = !Is128B ? Hexagon::V6_vandqrt : Hexagon::V6_vandqrt_128B; - BuildMI(B, It, DL, HII.get(VandOpc), TmpR1) + BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1) .addReg(SrcR, getKillRegState(IsKill)) .addReg(TmpR0, RegState::Kill); @@ -1606,7 +1599,6 @@ bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { - auto &HST = B.getParent()->getSubtarget(); MachineInstr *MI = &*It; if (!MI->getOperand(1).isFI()) return false; @@ -1614,10 +1606,7 @@ DebugLoc DL = MI->getDebugLoc(); unsigned DstR = MI->getOperand(0).getReg(); int FI = MI->getOperand(1).getIndex(); - - bool Is128B = HST.useHVXDblOps(); - auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass - : &Hexagon::VectorRegs128BRegClass; + auto *RC = &Hexagon::HvxVRRegClass; // TmpR0 = A2_tfrsi 0x01010101 // TmpR1 = load FI, 0 @@ -1627,12 +1616,12 @@ BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0) .addImm(0x01010101); - auto *HRI = B.getParent()->getSubtarget().getRegisterInfo(); + MachineFunction &MF = *B.getParent(); + auto *HRI = MF.getSubtarget().getRegisterInfo(); HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI); expandLoadVec(B, std::prev(It), MRI, HII, NewRegs); - unsigned VandOpc = !Is128B ? Hexagon::V6_vandvrt : Hexagon::V6_vandvrt_128B; - BuildMI(B, It, DL, HII.get(VandOpc), DstR) + BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR) .addReg(TmpR1, RegState::Kill) .addReg(TmpR0, RegState::Kill); @@ -1646,7 +1635,6 @@ MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); - auto &HST = MF.getSubtarget(); auto &MFI = MF.getFrameInfo(); auto &HRI = *MF.getSubtarget().getRegisterInfo(); MachineInstr *MI = &*It; @@ -1677,21 +1665,15 @@ bool IsKill = MI->getOperand(2).isKill(); int FI = MI->getOperand(0).getIndex(); - bool Is128B = HST.useHVXDblOps(); - const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass - : Hexagon::VectorRegs128BRegClass; - unsigned Size = HRI.getSpillSize(RC); - unsigned NeedAlign = HRI.getSpillAlignment(RC); + unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); + unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); unsigned HasAlign = MFI.getObjectAlignment(FI); unsigned StoreOpc; // Store low part. if (LPR.contains(SrcLo)) { - if (NeedAlign <= HasAlign) - StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B; - else - StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B; - + StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai + : Hexagon::V6_vS32Ub_ai; BuildMI(B, It, DL, HII.get(StoreOpc)) .addFrameIndex(FI) .addImm(0) @@ -1701,11 +1683,8 @@ // Store high part. if (LPR.contains(SrcHi)) { - if (NeedAlign <= MinAlign(HasAlign, Size)) - StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B; - else - StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B; - + StoreOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vS32b_ai + : Hexagon::V6_vS32Ub_ai; BuildMI(B, It, DL, HII.get(StoreOpc)) .addFrameIndex(FI) .addImm(Size) @@ -1721,7 +1700,6 @@ MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); - auto &HST = MF.getSubtarget(); auto &MFI = MF.getFrameInfo(); auto &HRI = *MF.getSubtarget().getRegisterInfo(); MachineInstr *MI = &*It; @@ -1734,31 +1712,22 @@ unsigned DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); int FI = MI->getOperand(1).getIndex(); - bool Is128B = HST.useHVXDblOps(); - const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass - : Hexagon::VectorRegs128BRegClass; - unsigned Size = HRI.getSpillSize(RC); - unsigned NeedAlign = HRI.getSpillAlignment(RC); + unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); + unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); unsigned HasAlign = MFI.getObjectAlignment(FI); unsigned LoadOpc; // Load low part. - if (NeedAlign <= HasAlign) - LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B; - else - LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B; - + LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai + : Hexagon::V6_vL32Ub_ai; BuildMI(B, It, DL, HII.get(LoadOpc), DstLo) .addFrameIndex(FI) .addImm(0) .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); // Load high part. - if (NeedAlign <= MinAlign(HasAlign, Size)) - LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B; - else - LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B; - + LoadOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vL32b_ai + : Hexagon::V6_vL32Ub_ai; BuildMI(B, It, DL, HII.get(LoadOpc), DstHi) .addFrameIndex(FI) .addImm(Size) @@ -1772,30 +1741,21 @@ MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); - auto &HST = MF.getSubtarget(); auto &MFI = MF.getFrameInfo(); MachineInstr *MI = &*It; if (!MI->getOperand(0).isFI()) return false; - auto &HRI = *HST.getRegisterInfo(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned SrcR = MI->getOperand(2).getReg(); bool IsKill = MI->getOperand(2).isKill(); int FI = MI->getOperand(0).getIndex(); - bool Is128B = HST.useHVXDblOps(); - const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass - : Hexagon::VectorRegs128BRegClass; - unsigned NeedAlign = HRI.getSpillAlignment(RC); + unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); unsigned HasAlign = MFI.getObjectAlignment(FI); - unsigned StoreOpc; - - if (NeedAlign <= HasAlign) - StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B; - else - StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B; - + unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai + : Hexagon::V6_vS32Ub_ai; BuildMI(B, It, DL, HII.get(StoreOpc)) .addFrameIndex(FI) .addImm(0) @@ -1810,29 +1770,20 @@ MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl &NewRegs) const { MachineFunction &MF = *B.getParent(); - auto &HST = MF.getSubtarget(); auto &MFI = MF.getFrameInfo(); MachineInstr *MI = &*It; if (!MI->getOperand(1).isFI()) return false; - auto &HRI = *HST.getRegisterInfo(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned DstR = MI->getOperand(0).getReg(); int FI = MI->getOperand(1).getIndex(); - bool Is128B = HST.useHVXDblOps(); - const auto &RC = !Is128B ? Hexagon::VectorRegsRegClass - : Hexagon::VectorRegs128BRegClass; - unsigned NeedAlign = HRI.getSpillAlignment(RC); + unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); unsigned HasAlign = MFI.getObjectAlignment(FI); - unsigned LoadOpc; - - if (NeedAlign <= HasAlign) - LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B; - else - LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B; - + unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai + : Hexagon::V6_vL32Ub_ai; BuildMI(B, It, DL, HII.get(LoadOpc), DstR) .addFrameIndex(FI) .addImm(0) @@ -1844,8 +1795,7 @@ bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF, SmallVectorImpl &NewRegs) const { - auto &HST = MF.getSubtarget(); - auto &HII = *HST.getInstrInfo(); + auto &HII = *MF.getSubtarget().getInstrInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); bool Changed = false; @@ -1870,23 +1820,17 @@ Changed |= expandLoadInt(B, I, MRI, HII, NewRegs); break; case Hexagon::PS_vstorerq_ai: - case Hexagon::PS_vstorerq_ai_128B: Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs); break; case Hexagon::PS_vloadrq_ai: - case Hexagon::PS_vloadrq_ai_128B: Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs); break; case Hexagon::PS_vloadrw_ai: case Hexagon::PS_vloadrwu_ai: - case Hexagon::PS_vloadrw_ai_128B: - case Hexagon::PS_vloadrwu_ai_128B: Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs); break; case Hexagon::PS_vstorerw_ai: case Hexagon::PS_vstorerwu_ai: - case Hexagon::PS_vstorerw_ai_128B: - case Hexagon::PS_vstorerwu_ai_128B: Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs); break; } @@ -1899,8 +1843,7 @@ void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const { - auto &HST = MF.getSubtarget(); - auto &HRI = *HST.getRegisterInfo(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); SavedRegs.resize(HRI.getNumRegs()); Index: lib/Target/Hexagon/HexagonHardwareLoops.cpp =================================================================== --- lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -1231,7 +1231,7 @@ // if the immediate fits in the instructions. Otherwise, we need to // create a new virtual register. int64_t CountImm = TripCount->getImm(); - if (!TII->isValidOffset(LOOP_i, CountImm)) { + if (!TII->isValidOffset(LOOP_i, CountImm, TRI)) { unsigned CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg) .addImm(CountImm); Index: lib/Target/Hexagon/HexagonISelDAGToDAG.cpp =================================================================== --- lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -237,22 +237,14 @@ case MVT::v32i16: case MVT::v16i32: case MVT::v8i64: - if (isAlignedMemNode(LD)) - Opcode = IsValidInc ? Hexagon::V6_vL32b_pi : Hexagon::V6_vL32b_ai; - else - Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi : Hexagon::V6_vL32Ub_ai; - break; - // 128B case MVT::v128i8: case MVT::v64i16: case MVT::v32i32: case MVT::v16i64: if (isAlignedMemNode(LD)) - Opcode = IsValidInc ? Hexagon::V6_vL32b_pi_128B - : Hexagon::V6_vL32b_ai_128B; + Opcode = IsValidInc ? Hexagon::V6_vL32b_pi : Hexagon::V6_vL32b_ai; else - Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi_128B - : Hexagon::V6_vL32Ub_ai_128B; + Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi : Hexagon::V6_vL32Ub_ai; break; default: llvm_unreachable("Unexpected memory type in indexed load"); @@ -525,22 +517,14 @@ case MVT::v32i16: case MVT::v16i32: case MVT::v8i64: - if (isAlignedMemNode(ST)) - Opcode = IsValidInc ? Hexagon::V6_vS32b_pi : Hexagon::V6_vS32b_ai; - else - Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi : Hexagon::V6_vS32Ub_ai; - break; - // 128B case MVT::v128i8: case MVT::v64i16: case MVT::v32i32: case MVT::v16i64: if (isAlignedMemNode(ST)) - Opcode = IsValidInc ? Hexagon::V6_vS32b_pi_128B - : Hexagon::V6_vS32b_ai_128B; + Opcode = IsValidInc ? Hexagon::V6_vS32b_pi : Hexagon::V6_vS32b_ai; else - Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi_128B - : Hexagon::V6_vS32Ub_ai_128B; + Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi : Hexagon::V6_vS32Ub_ai; break; default: llvm_unreachable("Unexpected memory type in indexed store"); Index: lib/Target/Hexagon/HexagonISelLowering.cpp =================================================================== --- lib/Target/Hexagon/HexagonISelLowering.cpp +++ lib/Target/Hexagon/HexagonISelLowering.cpp @@ -381,7 +381,6 @@ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); return false; } - // 128B Mode if ((UseHVX && UseHVXDbl) && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) { @@ -1191,14 +1190,14 @@ } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { unsigned VReg = - RegInfo.createVirtualRegister(&Hexagon::VectorRegsRegClass); + RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); } else if (UseHVX && UseHVXDbl && ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { unsigned VReg = - RegInfo.createVirtualRegister(&Hexagon::VectorRegs128BRegClass); + RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); @@ -1206,20 +1205,20 @@ } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) { unsigned VReg = - RegInfo.createVirtualRegister(&Hexagon::VecDblRegsRegClass); + RegInfo.createVirtualRegister(&Hexagon::HvxVPRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); } else if (UseHVX && UseHVXDbl && ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { unsigned VReg = - RegInfo.createVirtualRegister(&Hexagon::VecDblRegs128BRegClass); + RegInfo.createVirtualRegister(&Hexagon::HvxVPRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) { assert(0 && "need to support VecPred regs"); unsigned VReg = - RegInfo.createVirtualRegister(&Hexagon::VecPredRegsRegClass); + RegInfo.createVirtualRegister(&Hexagon::HvxQRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); } else { @@ -1803,25 +1802,25 @@ if (Subtarget.hasV60TOps()) { if (Subtarget.useHVXSglOps()) { - addRegisterClass(MVT::v64i8, &Hexagon::VectorRegsRegClass); - addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass); - addRegisterClass(MVT::v16i32, &Hexagon::VectorRegsRegClass); - addRegisterClass(MVT::v8i64, &Hexagon::VectorRegsRegClass); - addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass); - addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass); - addRegisterClass(MVT::v32i32, &Hexagon::VecDblRegsRegClass); - addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass); - addRegisterClass(MVT::v512i1, &Hexagon::VecPredRegsRegClass); + addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v8i64, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v128i8, &Hexagon::HvxVPRegClass); + addRegisterClass(MVT::v64i16, &Hexagon::HvxVPRegClass); + addRegisterClass(MVT::v32i32, &Hexagon::HvxVPRegClass); + addRegisterClass(MVT::v16i64, &Hexagon::HvxVPRegClass); + addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass); } else if (Subtarget.useHVXDblOps()) { - addRegisterClass(MVT::v128i8, &Hexagon::VectorRegs128BRegClass); - addRegisterClass(MVT::v64i16, &Hexagon::VectorRegs128BRegClass); - addRegisterClass(MVT::v32i32, &Hexagon::VectorRegs128BRegClass); - addRegisterClass(MVT::v16i64, &Hexagon::VectorRegs128BRegClass); - addRegisterClass(MVT::v256i8, &Hexagon::VecDblRegs128BRegClass); - addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass); - addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass); - addRegisterClass(MVT::v32i64, &Hexagon::VecDblRegs128BRegClass); - addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass); + addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v16i64, &Hexagon::HvxVRRegClass); + addRegisterClass(MVT::v256i8, &Hexagon::HvxVPRegClass); + addRegisterClass(MVT::v128i16, &Hexagon::HvxVPRegClass); + addRegisterClass(MVT::v64i32, &Hexagon::HvxVPRegClass); + addRegisterClass(MVT::v32i64, &Hexagon::HvxVPRegClass); + addRegisterClass(MVT::v1024i1, &Hexagon::HvxQRRegClass); } } @@ -3061,22 +3060,22 @@ default: llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size"); case 512: - return std::make_pair(0U, &Hexagon::VecPredRegsRegClass); + return std::make_pair(0U, &Hexagon::HvxQRRegClass); case 1024: - return std::make_pair(0U, &Hexagon::VecPredRegs128BRegClass); + return std::make_pair(0U, &Hexagon::HvxQRRegClass); } case 'v': // V0-V31 switch (VT.getSizeInBits()) { default: llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size"); case 512: - return std::make_pair(0U, &Hexagon::VectorRegsRegClass); + return std::make_pair(0U, &Hexagon::HvxVRRegClass); case 1024: if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl) - return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass); - return std::make_pair(0U, &Hexagon::VecDblRegsRegClass); + return std::make_pair(0U, &Hexagon::HvxVRRegClass); + return std::make_pair(0U, &Hexagon::HvxVPRegClass); case 2048: - return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass); + return std::make_pair(0U, &Hexagon::HvxVPRegClass); } default: @@ -3268,7 +3267,7 @@ case MVT::v32i16: case MVT::v16i32: case MVT::v8i64: - RRC = &Hexagon::VectorRegsRegClass; + RRC = &Hexagon::HvxVRRegClass; break; case MVT::v128i8: case MVT::v64i16: @@ -3276,15 +3275,15 @@ case MVT::v16i64: if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() && Subtarget.useHVXDblOps()) - RRC = &Hexagon::VectorRegs128BRegClass; + RRC = &Hexagon::HvxVRRegClass; else - RRC = &Hexagon::VecDblRegsRegClass; + RRC = &Hexagon::HvxVPRegClass; break; case MVT::v256i8: case MVT::v128i16: case MVT::v64i32: case MVT::v32i64: - RRC = &Hexagon::VecDblRegs128BRegClass; + RRC = &Hexagon::HvxVPRegClass; break; } return std::make_pair(RRC, Cost); Index: lib/Target/Hexagon/HexagonInstrInfo.h =================================================================== --- lib/Target/Hexagon/HexagonInstrInfo.h +++ lib/Target/Hexagon/HexagonInstrInfo.h @@ -14,7 +14,6 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H -#include "HexagonRegisterInfo.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" @@ -32,10 +31,9 @@ struct EVT; class HexagonSubtarget; +class HexagonRegisterInfo; class HexagonInstrInfo : public HexagonGenInstrInfo { - const HexagonRegisterInfo RI; - virtual void anchor(); public: @@ -293,8 +291,6 @@ /// HexagonInstrInfo specifics. /// - const HexagonRegisterInfo &getRegisterInfo() const { return RI; } - unsigned createVR(MachineFunction* MF, MVT VT) const; bool isAbsoluteSet(const MachineInstr &MI) const; @@ -358,7 +354,8 @@ const MachineInstr &MI2) const; bool isV60VectorInstruction(const MachineInstr &MI) const; bool isValidAutoIncImm(const EVT VT, const int Offset) const; - bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const; + bool isValidOffset(unsigned Opcode, int Offset, + const TargetRegisterInfo *TRI, bool Extend = true) const; bool isVecAcc(const MachineInstr &MI) const; bool isVecALU(const MachineInstr &MI) const; bool isVecUsableNextPacket(const MachineInstr &ProdMI, Index: lib/Target/Hexagon/HexagonInstrInfo.cpp =================================================================== --- lib/Target/Hexagon/HexagonInstrInfo.cpp +++ lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -93,10 +93,6 @@ /// /// Constants for Hexagon instructions. /// -const int Hexagon_MEMV_OFFSET_MAX_128B = 896; // #s4: -8*128...7*128 -const int Hexagon_MEMV_OFFSET_MIN_128B = -1024; // #s4 -const int Hexagon_MEMV_OFFSET_MAX = 448; // #s4: -8*64...7*64 -const int Hexagon_MEMV_OFFSET_MIN = -512; // #s4 const int Hexagon_MEMW_OFFSET_MAX = 4095; const int Hexagon_MEMW_OFFSET_MIN = -4096; const int Hexagon_MEMD_OFFSET_MAX = 8191; @@ -124,8 +120,7 @@ void HexagonInstrInfo::anchor() {} HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) - : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), - RI() {} + : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP) {} static bool isIntRegForSubInst(unsigned Reg) { return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || @@ -253,15 +248,11 @@ case Hexagon::L2_loadri_io: case Hexagon::L2_loadrd_io: case Hexagon::V6_vL32b_ai: - case Hexagon::V6_vL32b_ai_128B: case Hexagon::V6_vL32Ub_ai: - case Hexagon::V6_vL32Ub_ai_128B: case Hexagon::LDriw_pred: case Hexagon::LDriw_mod: case Hexagon::PS_vloadrq_ai: - case Hexagon::PS_vloadrw_ai: - case Hexagon::PS_vloadrq_ai_128B: - case Hexagon::PS_vloadrw_ai_128B: { + case Hexagon::PS_vloadrw_ai: { const MachineOperand OpFI = MI.getOperand(1); if (!OpFI.isFI()) return 0; @@ -305,15 +296,11 @@ case Hexagon::S2_storeri_io: case Hexagon::S2_storerd_io: case Hexagon::V6_vS32b_ai: - case Hexagon::V6_vS32b_ai_128B: case Hexagon::V6_vS32Ub_ai: - case Hexagon::V6_vS32Ub_ai_128B: case Hexagon::STriw_pred: case Hexagon::STriw_mod: case Hexagon::PS_vstorerq_ai: - case Hexagon::PS_vstorerw_ai: - case Hexagon::PS_vstorerq_ai_128B: - case Hexagon::PS_vstorerw_ai_128B: { + case Hexagon::PS_vstorerw_ai: { const MachineOperand &OpFI = MI.getOperand(0); if (!OpFI.isFI()) return 0; @@ -714,10 +701,11 @@ unsigned NewLoopCount = createVR(MF, MVT::i32); MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount). addReg(LoopCount).addImm(-1); + const auto &HRI = *MF->getSubtarget().getRegisterInfo(); // Update the previously generated instructions with the new loop counter. for (SmallVectorImpl::iterator I = PrevInsts.begin(), E = PrevInsts.end(); I != E; ++I) - (*I)->substituteRegister(LoopCount, NewLoopCount, 0, getRegisterInfo()); + (*I)->substituteRegister(LoopCount, NewLoopCount, 0, HRI); PrevInsts.clear(); PrevInsts.push_back(NewCmp); PrevInsts.push_back(NewAdd); @@ -756,7 +744,8 @@ MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const { - auto &HRI = getRegisterInfo(); + MachineFunction &MF = *MBB.getParent(); + auto &HRI = *MF.getSubtarget().getRegisterInfo(); unsigned KillFlag = getKillRegState(KillSrc); if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { @@ -811,12 +800,12 @@ .addReg(SrcReg, KillFlag); return; } - if (Hexagon::VectorRegsRegClass.contains(SrcReg, DestReg)) { + if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) { BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg). addReg(SrcReg, KillFlag); return; } - if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) { + if (Hexagon::HvxVPRegClass.contains(SrcReg, DestReg)) { unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg) @@ -824,33 +813,22 @@ .addReg(LoSrc, KillFlag); return; } - if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) { + if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) { BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg) .addReg(SrcReg) .addReg(SrcReg, KillFlag); return; } - if (Hexagon::VecPredRegsRegClass.contains(SrcReg) && - Hexagon::VectorRegsRegClass.contains(DestReg)) { + if (Hexagon::HvxQRRegClass.contains(SrcReg) && + Hexagon::HvxVRRegClass.contains(DestReg)) { llvm_unreachable("Unimplemented pred to vec"); return; } - if (Hexagon::VecPredRegsRegClass.contains(DestReg) && - Hexagon::VectorRegsRegClass.contains(SrcReg)) { + if (Hexagon::HvxQRRegClass.contains(DestReg) && + Hexagon::HvxVRRegClass.contains(SrcReg)) { llvm_unreachable("Unimplemented vec to pred"); return; } - if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) { - unsigned HiDst = HRI.getSubReg(DestReg, Hexagon::vsub_hi); - unsigned LoDst = HRI.getSubReg(DestReg, Hexagon::vsub_lo); - unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); - unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); - BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), HiDst) - .addReg(HiSrc, KillFlag); - BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), LoDst) - .addReg(LoSrc, KillFlag); - return; - } #ifndef NDEBUG // Show the invalid registers to ease debugging. @@ -867,12 +845,13 @@ DebugLoc DL = MBB.findDebugLoc(I); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); - unsigned Align = MFI.getObjectAlignment(FI); + unsigned SlotAlign = MFI.getObjectAlignment(FI); + unsigned RegAlign = TRI->getSpillAlignment(*RC); unsigned KillFlag = getKillRegState(isKill); MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore, - MFI.getObjectSize(FI), Align); + MFI.getObjectSize(FI), SlotAlign); if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io)) @@ -890,35 +869,19 @@ BuildMI(MBB, I, DL, get(Hexagon::STriw_mod)) .addFrameIndex(FI).addImm(0) .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai_128B)) - .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) { + } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai)) .addFrameIndex(FI).addImm(0) .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) { - unsigned Opc = Align < 128 ? Hexagon::V6_vS32Ub_ai_128B - : Hexagon::V6_vS32b_ai_128B; - BuildMI(MBB, I, DL, get(Opc)) - .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) { - unsigned Opc = Align < 64 ? Hexagon::V6_vS32Ub_ai - : Hexagon::V6_vS32b_ai; + } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { + unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai + : Hexagon::V6_vS32b_ai; BuildMI(MBB, I, DL, get(Opc)) .addFrameIndex(FI).addImm(0) .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) { - unsigned Opc = Align < 64 ? Hexagon::PS_vstorerwu_ai - : Hexagon::PS_vstorerw_ai; - BuildMI(MBB, I, DL, get(Opc)) - .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); - } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) { - unsigned Opc = Align < 128 ? Hexagon::PS_vstorerwu_ai_128B - : Hexagon::PS_vstorerw_ai_128B; + } else if (Hexagon::HvxVPRegClass.hasSubClassEq(RC)) { + unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai + : Hexagon::PS_vstorerw_ai; BuildMI(MBB, I, DL, get(Opc)) .addFrameIndex(FI).addImm(0) .addReg(SrcReg, KillFlag).addMemOperand(MMO); @@ -934,11 +897,12 @@ DebugLoc DL = MBB.findDebugLoc(I); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); - unsigned Align = MFI.getObjectAlignment(FI); + unsigned SlotAlign = MFI.getObjectAlignment(FI); + unsigned RegAlign = TRI->getSpillAlignment(*RC); MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad, - MFI.getObjectSize(FI), Align); + MFI.getObjectSize(FI), SlotAlign); if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg) @@ -952,30 +916,17 @@ } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::LDriw_mod), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai_128B), DestReg) - .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) { + } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) { - unsigned Opc = Align < 128 ? Hexagon::PS_vloadrwu_ai_128B - : Hexagon::PS_vloadrw_ai_128B; + } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { + unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai + : Hexagon::V6_vL32b_ai; BuildMI(MBB, I, DL, get(Opc), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) { - unsigned Opc = Align < 128 ? Hexagon::V6_vL32Ub_ai_128B - : Hexagon::V6_vL32b_ai_128B; - BuildMI(MBB, I, DL, get(Opc), DestReg) - .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) { - unsigned Opc = Align < 64 ? Hexagon::V6_vL32Ub_ai - : Hexagon::V6_vL32b_ai; - BuildMI(MBB, I, DL, get(Opc), DestReg) - .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) { - unsigned Opc = Align < 64 ? Hexagon::PS_vloadrwu_ai - : Hexagon::PS_vloadrw_ai; + } else if (Hexagon::HvxVPRegClass.hasSubClassEq(RC)) { + unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai + : Hexagon::PS_vloadrw_ai; BuildMI(MBB, I, DL, get(Opc), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO); } else { @@ -998,12 +949,12 @@ /// new instructions and erase MI. The function should return true if /// anything was changed. bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { - const HexagonRegisterInfo &HRI = getRegisterInfo(); - MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); + MachineFunction &MF = *MI.getParent()->getParent(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + const auto &HRI = *MF.getSubtarget().getRegisterInfo(); MachineBasicBlock &MBB = *MI.getParent(); DebugLoc DL = MI.getDebugLoc(); unsigned Opc = MI.getOpcode(); - const unsigned VecOffset = 1; switch (Opc) { case TargetOpcode::COPY: { @@ -1023,7 +974,6 @@ .addImm(-MI.getOperand(1).getImm()); MBB.erase(MI); return true; - case Hexagon::V6_vassignp_128B: case Hexagon::V6_vassignp: { unsigned SrcReg = MI.getOperand(1).getReg(); unsigned DstReg = MI.getOperand(0).getReg(); @@ -1034,7 +984,6 @@ MBB.erase(MI); return true; } - case Hexagon::V6_lo_128B: case Hexagon::V6_lo: { unsigned SrcReg = MI.getOperand(1).getReg(); unsigned DstReg = MI.getOperand(0).getReg(); @@ -1044,7 +993,6 @@ MRI.clearKillFlags(SrcSubLo); return true; } - case Hexagon::V6_hi_128B: case Hexagon::V6_hi: { unsigned SrcReg = MI.getOperand(1).getReg(); unsigned DstReg = MI.getOperand(0).getReg(); @@ -1055,25 +1003,14 @@ return true; } case Hexagon::PS_vstorerw_ai: - case Hexagon::PS_vstorerwu_ai: - case Hexagon::PS_vstorerw_ai_128B: - case Hexagon::PS_vstorerwu_ai_128B: { - bool Is128B = (Opc == Hexagon::PS_vstorerw_ai_128B || - Opc == Hexagon::PS_vstorerwu_ai_128B); - bool Aligned = (Opc == Hexagon::PS_vstorerw_ai || - Opc == Hexagon::PS_vstorerw_ai_128B); + case Hexagon::PS_vstorerwu_ai: { + bool Aligned = Opc == Hexagon::PS_vstorerw_ai; unsigned SrcReg = MI.getOperand(2).getReg(); unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); - unsigned NewOpc; - if (Aligned) - NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B - : Hexagon::V6_vS32b_ai; - else - NewOpc = Is128B ? Hexagon::V6_vS32Ub_ai_128B - : Hexagon::V6_vS32Ub_ai; + unsigned NewOpc = Aligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai; + unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass); - unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6; MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc)) .add(MI.getOperand(0)) @@ -1091,23 +1028,12 @@ return true; } case Hexagon::PS_vloadrw_ai: - case Hexagon::PS_vloadrwu_ai: - case Hexagon::PS_vloadrw_ai_128B: - case Hexagon::PS_vloadrwu_ai_128B: { - bool Is128B = (Opc == Hexagon::PS_vloadrw_ai_128B || - Opc == Hexagon::PS_vloadrwu_ai_128B); - bool Aligned = (Opc == Hexagon::PS_vloadrw_ai || - Opc == Hexagon::PS_vloadrw_ai_128B); - unsigned NewOpc; - if (Aligned) - NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B - : Hexagon::V6_vL32b_ai; - else - NewOpc = Is128B ? Hexagon::V6_vL32Ub_ai_128B - : Hexagon::V6_vL32Ub_ai; - + case Hexagon::PS_vloadrwu_ai: { + bool Aligned = Opc == Hexagon::PS_vloadrw_ai; unsigned DstReg = MI.getOperand(0).getReg(); - unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6; + unsigned NewOpc = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai; + unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass); + MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_lo)) .add(MI.getOperand(1)) @@ -1216,8 +1142,7 @@ MBB.erase(MI); return true; } - case Hexagon::PS_vselect: - case Hexagon::PS_vselect_128B: { + case Hexagon::PS_vselect: { const MachineOperand &Op0 = MI.getOperand(0); const MachineOperand &Op1 = MI.getOperand(1); const MachineOperand &Op2 = MI.getOperand(2); @@ -1245,8 +1170,7 @@ MBB.erase(MI); return true; } - case Hexagon::PS_wselect: - case Hexagon::PS_wselect_128B: { + case Hexagon::PS_wselect: { MachineOperand &Op0 = MI.getOperand(0); MachineOperand &Op1 = MI.getOperand(1); MachineOperand &Op2 = MI.getOperand(2); @@ -1408,9 +1332,11 @@ return false; } -bool HexagonInstrInfo::DefinesPredicate( - MachineInstr &MI, std::vector &Pred) const { - auto &HRI = getRegisterInfo(); +bool HexagonInstrInfo::DefinesPredicate(MachineInstr &MI, + std::vector &Pred) const { + MachineFunction &MF = *MI.getParent()->getParent(); + const auto &HRI = *MF.getSubtarget().getRegisterInfo(); + for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) { MachineOperand MO = MI.getOperand(oper); if (MO.isReg()) { @@ -1950,8 +1876,8 @@ const MachineInstr &ConsMI) const { if (!ProdMI.getDesc().getNumDefs()) return false; - - auto &HRI = getRegisterInfo(); + const MachineFunction &MF = *ProdMI.getParent()->getParent(); + const auto &HRI = *MF.getSubtarget().getRegisterInfo(); SmallVector DefsA; SmallVector DefsB; @@ -1986,8 +1912,6 @@ switch (MI.getOpcode()) { case Hexagon::V6_vL32b_cur_pi: case Hexagon::V6_vL32b_cur_ai: - case Hexagon::V6_vL32b_cur_pi_128B: - case Hexagon::V6_vL32b_cur_ai_128B: return true; } return false; @@ -2596,7 +2520,7 @@ } bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset, - bool Extend) const { + const TargetRegisterInfo *TRI, bool Extend) const { // This function is to check whether the "Offset" is in the correct range of // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is // inserted to calculate the final address. Due to this reason, the function @@ -2605,7 +2529,6 @@ // there are cases where a misaligned pointer recast can cause this // problem, and we need to allow for it. The front end warns of such // misaligns with respect to load size. - switch (Opcode) { case Hexagon::PS_vstorerq_ai: case Hexagon::PS_vstorerw_ai: @@ -2614,20 +2537,13 @@ case Hexagon::V6_vL32b_ai: case Hexagon::V6_vS32b_ai: case Hexagon::V6_vL32Ub_ai: - case Hexagon::V6_vS32Ub_ai: - return (Offset >= Hexagon_MEMV_OFFSET_MIN) && - (Offset <= Hexagon_MEMV_OFFSET_MAX); - - case Hexagon::PS_vstorerq_ai_128B: - case Hexagon::PS_vstorerw_ai_128B: - case Hexagon::PS_vloadrq_ai_128B: - case Hexagon::PS_vloadrw_ai_128B: - case Hexagon::V6_vL32b_ai_128B: - case Hexagon::V6_vS32b_ai_128B: - case Hexagon::V6_vL32Ub_ai_128B: - case Hexagon::V6_vS32Ub_ai_128B: - return (Offset >= Hexagon_MEMV_OFFSET_MIN_128B) && - (Offset <= Hexagon_MEMV_OFFSET_MAX_128B); + case Hexagon::V6_vS32Ub_ai: { + unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass); + assert(isPowerOf2_32(VectorSize)); + if (Offset & (VectorSize-1)) + return false; + return isInt<4>(Offset >> Log2_32(VectorSize)); + } case Hexagon::J2_loop0i: case Hexagon::J2_loop1i: @@ -3332,11 +3248,6 @@ return Hexagon::V6_vL32b_cur_pi; case Hexagon::V6_vL32b_ai: return Hexagon::V6_vL32b_cur_ai; - //128B - case Hexagon::V6_vL32b_pi_128B: - return Hexagon::V6_vL32b_cur_pi_128B; - case Hexagon::V6_vL32b_ai_128B: - return Hexagon::V6_vL32b_cur_ai_128B; } return 0; } @@ -3453,13 +3364,6 @@ case Hexagon::V6_vS32b_pi: return Hexagon::V6_vS32b_new_pi; - - // 128B - case Hexagon::V6_vS32b_ai_128B: - return Hexagon::V6_vS32b_new_ai_128B; - - case Hexagon::V6_vS32b_pi_128B: - return Hexagon::V6_vS32b_new_pi_128B; } return 0; } @@ -3604,7 +3508,8 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( const MachineInstr &MI) const { unsigned DstReg, SrcReg, Src1Reg, Src2Reg; - auto &HRI = getRegisterInfo(); + const MachineFunction &MF = *MI.getParent()->getParent(); + const auto &HRI = *MF.getSubtarget().getRegisterInfo(); switch (MI.getOpcode()) { default: Index: lib/Target/Hexagon/HexagonIntrinsics.td =================================================================== --- lib/Target/Hexagon/HexagonIntrinsics.td +++ lib/Target/Hexagon/HexagonIntrinsics.td @@ -1348,17 +1348,11 @@ def: T_stc_pat; multiclass MaskedStore { - def : Pat<(IntID VecPredRegs:$src1, IntRegs:$src2, VectorRegs:$src3), - (MI VecPredRegs:$src1, IntRegs:$src2, #0, VectorRegs:$src3)>, - Requires<[UseHVXSgl]>; - - def : Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, - IntRegs:$src2, - VectorRegs128B:$src3), - (!cast(MI#"_128B") VecPredRegs128B:$src1, - IntRegs:$src2, #0, - VectorRegs128B:$src3)>, - Requires<[UseHVXDbl]>; + def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>; + def : Pat<(!cast(IntID#"_128B") HvxQR:$src1, IntRegs:$src2, + HvxVR:$src3), + (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>; } defm : MaskedStore ; Index: lib/Target/Hexagon/HexagonIntrinsicsV60.td =================================================================== --- lib/Target/Hexagon/HexagonIntrinsicsV60.td +++ lib/Target/Hexagon/HexagonIntrinsicsV60.td @@ -13,445 +13,298 @@ let AddedComplexity = 100 in { -def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))), - (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_lo)) >, - Requires<[UseHVXSgl]>; +def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxVP:$src1))), + (v16i32 (EXTRACT_SUBREG (v32i32 HvxVP:$src1), vsub_lo)) >; -def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))), - (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_hi)) >, - Requires<[UseHVXSgl]>; +def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxVP:$src1))), + (v16i32 (EXTRACT_SUBREG (v32i32 HvxVP:$src1), vsub_hi)) >; -def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))), - (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_lo)) >, - Requires<[UseHVXDbl]>; +def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxVP:$src1))), + (v32i32 (EXTRACT_SUBREG (v64i32 HvxVP:$src1), vsub_lo)) >; -def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))), - (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_hi)) >, - Requires<[UseHVXDbl]>; +def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxVP:$src1))), + (v32i32 (EXTRACT_SUBREG (v64i32 HvxVP:$src1), vsub_hi)) >; } -def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))), - (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; - -def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))), - (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; - -def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))), - (v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; - -def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))), - (v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; - -def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))), - (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; - -def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))), - (v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; - -def : Pat <(v64i8 (bitconvert (v512i1 VecPredRegs:$src1))), - (v64i8 (V6_vandqrt(v512i1 VecPredRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; - -def : Pat <(v8i64 (bitconvert (v512i1 VecPredRegs:$src1))), - (v8i64 (V6_vandqrt(v512i1 VecPredRegs:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; - -def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))), - (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; - -def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))), - (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; - -def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))), - (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; - -def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))), - (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; - -def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))), - (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; - -def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))), - (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; - -def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))), - (v128i8 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; - -def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))), - (v16i64 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; +def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))), + (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))), + (v512i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))), + (v512i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v512i1 (bitconvert (v8i64 HvxVR:$src1))), + (v512i1 (V6_vandvrt(v8i64 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))), + (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))), + (v32i16 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))), + (v64i8 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v8i64 (bitconvert (v512i1 HvxQR:$src1))), + (v8i64 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))), + (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))), + (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))), + (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v1024i1 (bitconvert (v16i64 HvxVR:$src1))), + (v1024i1 (V6_vandvrt (v16i64 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))), + (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))), + (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v128i8 (bitconvert (v1024i1 HvxQR:$src1))), + (v128i8 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; + +def : Pat <(v16i64 (bitconvert (v1024i1 HvxQR:$src1))), + (v16i64 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; let AddedComplexity = 140 in { -def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)), +def : Pat <(store (v512i1 HvxQR:$src1), (i32 IntRegs:$addr)), (V6_vS32b_ai IntRegs:$addr, 0, - (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1), - (A2_tfrsi 0x01010101))))>, - Requires<[UseHVXSgl]>; + (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), + (A2_tfrsi 0x01010101))))>; def : Pat <(v512i1 (load (i32 IntRegs:$addr))), (v512i1 (V6_vandvrt - (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXSgl]>; + (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>; -def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)), - (V6_vS32b_ai_128B IntRegs:$addr, 0, - (v32i32 (V6_vandqrt_128B (v1024i1 VecPredRegs128B:$src1), - (A2_tfrsi 0x01010101))))>, - Requires<[UseHVXDbl]>; +def : Pat <(store (v1024i1 HvxQR:$src1), (i32 IntRegs:$addr)), + (V6_vS32b_ai IntRegs:$addr, 0, + (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), + (A2_tfrsi 0x01010101))))>; def : Pat <(v1024i1 (load (i32 IntRegs:$addr))), - (v1024i1 (V6_vandvrt_128B - (v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)), - (A2_tfrsi 0x01010101)))>, - Requires<[UseHVXDbl]>; + (v1024i1 (V6_vandvrt + (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>; } multiclass T_R_pat { - def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>; def: Pat<(!cast(IntID#"_128B") IntRegs:$src1), - (!cast(MI#"_128B") IntRegs:$src1)>, - Requires<[UseHVXDbl]>; + (MI IntRegs:$src1)>; } multiclass T_V_pat { - def: Pat<(IntID VectorRegs:$src1), - (MI VectorRegs:$src1)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1), + (MI HvxVR:$src1)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1), - (!cast(MI#"_128B") VectorRegs128B:$src1)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1), + (MI HvxVR:$src1)>; } multiclass T_W_pat { - def: Pat<(IntID VecDblRegs:$src1), - (MI VecDblRegs:$src1)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVP:$src1), + (MI HvxVP:$src1)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1), - (!cast(MI#"_128B") VecDblRegs128B:$src1)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1), + (MI HvxVP:$src1)>; } multiclass T_Q_pat { - def: Pat<(IntID VecPredRegs:$src1), - (MI VecPredRegs:$src1)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxQR:$src1), + (MI HvxQR:$src1)>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1), - (!cast(MI#"_128B") VecPredRegs128B:$src1)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1), + (MI HvxQR:$src1)>; } multiclass T_WR_pat { - def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2), - (MI VecDblRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVP:$src1, IntRegs:$src2), + (MI HvxVP:$src1, IntRegs:$src2)>; - def: Pat<(!cast(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2), - (!cast(MI#"_128B")VecDblRegs128B:$src1, IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B")HvxVP:$src1, IntRegs:$src2), + (MI HvxVP:$src1, IntRegs:$src2)>; } multiclass T_VR_pat { - def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2), - (MI VectorRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, IntRegs:$src2), + (MI HvxVR:$src1, IntRegs:$src2)>; - def: Pat<(!cast(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2), - (!cast(MI#"_128B")VectorRegs128B:$src1, IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(!cast(IntID#"_128B")HvxVR:$src1, IntRegs:$src2), + (MI HvxVR:$src1, IntRegs:$src2)>; } multiclass T_WV_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2), - (MI VecDblRegs:$src1, VectorRegs:$src2)>, - Requires<[UseHVXSgl]>; - - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVP:$src1, HvxVR:$src2), + (MI HvxVP:$src1, HvxVR:$src2)>; + + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, HvxVR:$src2), + (MI HvxVP:$src1, HvxVR:$src2)>; } multiclass T_WW_pat { - def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2), - (MI VecDblRegs:$src1, VecDblRegs:$src2)>, - Requires<[UseHVXSgl]>; - - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVP:$src1, HvxVP:$src2), + (MI HvxVP:$src1, HvxVP:$src2)>; + + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, HvxVP:$src2), + (MI HvxVP:$src1, HvxVP:$src2)>; } multiclass T_VV_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2), - (MI VectorRegs:$src1, VectorRegs:$src2)>, - Requires<[UseHVXSgl]>; - - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2), + (MI HvxVR:$src1, HvxVR:$src2)>; + + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2), + (MI HvxVR:$src1, HvxVR:$src2)>; } multiclass T_QR_pat { - def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2), - (MI VecPredRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; - - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, - IntRegs:$src2), - (!cast(MI#"_128B") VecPredRegs128B:$src1, - IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxQR:$src1, IntRegs:$src2), + (MI HvxQR:$src1, IntRegs:$src2)>; + + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, IntRegs:$src2), + (MI HvxQR:$src1, IntRegs:$src2)>; } multiclass T_QQ_pat { - def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2), - (MI VecPredRegs:$src1, VecPredRegs:$src2)>, - Requires<[UseHVXSgl]>; - - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, - VecPredRegs128B:$src2), - (!cast(MI#"_128B") VecPredRegs128B:$src1, - VecPredRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxQR:$src1, HvxQR:$src2), + (MI HvxQR:$src1, HvxQR:$src2)>; + + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, HvxQR:$src2), + (MI HvxQR:$src1, HvxQR:$src2)>; } multiclass T_WWR_pat { - def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3), - (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVP:$src1, HvxVP:$src2, IntRegs:$src3), + (MI HvxVP:$src1, HvxVP:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, HvxVP:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxVP:$src1, HvxVP:$src2, IntRegs:$src3)>; } multiclass T_VVR_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; } multiclass T_WVR_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3), - (MI VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVP:$src1, HvxVR:$src2, IntRegs:$src3), + (MI HvxVP:$src1, HvxVR:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, HvxVR:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxVP:$src1, HvxVR:$src2, IntRegs:$src3)>; } multiclass T_VWR_pat { - def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3), - (MI VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, HvxVP:$src2, IntRegs:$src3), + (MI HvxVR:$src1, HvxVP:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VecDblRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVP:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VecDblRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxVR:$src1, HvxVP:$src2, IntRegs:$src3)>; } multiclass T_VVV_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, - Requires<[UseHVXSgl]>; - - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>; + + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + HvxVR:$src3), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>; } multiclass T_WVV_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), - (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, - Requires<[UseHVXSgl]>; - - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVP:$src1, HvxVR:$src2, HvxVR:$src3), + (MI HvxVP:$src1, HvxVR:$src2, HvxVR:$src3)>; + + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, HvxVR:$src2, + HvxVR:$src3), + (MI HvxVP:$src1, HvxVR:$src2, HvxVR:$src3)>; } multiclass T_QVV_pat { - def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), - (MI VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, - Requires<[UseHVXSgl]>; - - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3), - (!cast(MI#"_128B") VecPredRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>; + + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, HvxVR:$src2, + HvxVR:$src3), + (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>; } multiclass T_VQR_pat { - def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3), - (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VecPredRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VecPredRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; } multiclass T_QVR_pat { - def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3), - (MI VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), + (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, - VectorRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VecPredRegs128B:$src1, - VectorRegs128B:$src2, - IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>; } multiclass T_VVI_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>, - Requires<[UseHVXSgl]>; - - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, imm:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, imm:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3), + (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; + + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, + HvxVR:$src2, imm:$src3), + (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; } multiclass T_WRI_pat { - def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3), - (MI VecDblRegs:$src1, IntRegs:$src2, imm:$src3)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVP:$src1, IntRegs:$src2, imm:$src3), + (MI HvxVP:$src1, IntRegs:$src2, imm:$src3)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, IntRegs:$src2, imm:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - IntRegs:$src2, imm:$src3)>, - Requires<[UseHVXDbl]>; + (MI HvxVP:$src1, IntRegs:$src2, imm:$src3)>; } multiclass T_WWRI_pat { - def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4), - (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4)>, - Requires<[UseHVXSgl]>; + def: Pat<(IntID HvxVP:$src1, HvxVP:$src2, IntRegs:$src3, imm:$src4), + (MI HvxVP:$src1, HvxVP:$src2, IntRegs:$src3, imm:$src4)>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2, + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, HvxVP:$src2, IntRegs:$src3, imm:$src4), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VecDblRegs128B:$src2, - IntRegs:$src3, imm:$src4)>, - Requires<[UseHVXDbl]>; + (MI HvxVP:$src1, HvxVP:$src2, IntRegs:$src3, imm:$src4)>; } multiclass T_VVVR_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, - IntRegs:$src4), - (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, - IntRegs:$src4)>, - Requires<[UseHVXSgl]>; - - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3, - IntRegs:$src4), - (!cast(MI#"_128B") VectorRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3, - IntRegs:$src4)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; + + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + HvxVR:$src3, IntRegs:$src4), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; } multiclass T_WVVR_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, - IntRegs:$src4), - (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, - IntRegs:$src4)>, - Requires<[UseHVXSgl]>; - - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3, - IntRegs:$src4), - (!cast(MI#"_128B") VecDblRegs128B:$src1, - VectorRegs128B:$src2, - VectorRegs128B:$src3, - IntRegs:$src4)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVP:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4), + (MI HvxVP:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; + + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, HvxVR:$src2, + HvxVR:$src3, IntRegs:$src4), + (MI HvxVP:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; } defm : T_WR_pat ; @@ -793,11 +646,10 @@ //def : T_PPQ_pat ; def: Pat<(v64i16 (trunc v64i32:$Vdd)), - (v64i16 (V6_vpackwh_sat_128B - (v32i32 (V6_hi_128B VecDblRegs128B:$Vdd)), - (v32i32 (V6_lo_128B VecDblRegs128B:$Vdd))))>, - Requires<[UseHVXDbl]>; + (v64i16 (V6_vpackwh_sat + (v32i32 (V6_hi HvxVP:$Vdd)), + (v32i32 (V6_lo HvxVP:$Vdd))))>; def: Pat<(int_hexagon_V6_vd0), (V6_vd0)>; -def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0_128B)>; +def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0)>; Index: lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td =================================================================== --- lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td +++ lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td @@ -8,147 +8,123 @@ //===----------------------------------------------------------------------===// multiclass T_VR_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2), - (MI VectorRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, IntRegs:$src2), - (!cast(MI#"_128B") VectorRegs128B:$src1, IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, IntRegs:$src2), + (MI HvxVR:$src1, IntRegs:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, IntRegs:$src2), + (MI HvxVR:$src1, IntRegs:$src2)>; } multiclass T_VVL_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + IntRegsLow8:$src3), + (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>; } multiclass T_VV_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2), - (MI VectorRegs:$src1, VectorRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2), - (!cast(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2), + (MI HvxVR:$src1, HvxVR:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2), + (MI HvxVR:$src1, HvxVR:$src2)>; } multiclass T_WW_HVX_gen_pat { - def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2), - (MI VecDblRegs:$src1, VecDblRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2), - (!cast(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVP:$src1, HvxVP:$src2), + (MI HvxVP:$src1, HvxVP:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, HvxVP:$src2), + (MI HvxVP:$src1, HvxVP:$src2)>; } multiclass T_WVV_HVX_gen_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), - (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVP:$src1, HvxVR:$src2, HvxVR:$src3), + (MI HvxVP:$src1, HvxVR:$src2, HvxVR:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, HvxVR:$src2, + HvxVR:$src3), + (MI HvxVP:$src1, HvxVR:$src2, HvxVR:$src3)>; } multiclass T_WR_HVX_gen_pat { - def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2), - (MI VecDblRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, IntRegs:$src2), - (!cast(MI#"_128B") VecDblRegs128B:$src1, IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVP:$src1, IntRegs:$src2), + (MI HvxVP:$src1, IntRegs:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, IntRegs:$src2), + (MI HvxVP:$src1, IntRegs:$src2)>; } multiclass T_WWR_HVX_gen_pat { - def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3), - (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVP:$src1, HvxVP:$src2, IntRegs:$src3), + (MI HvxVP:$src1, HvxVP:$src2, IntRegs:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, HvxVP:$src2, + IntRegs:$src3), + (MI HvxVP:$src1, HvxVP:$src2, IntRegs:$src3)>; } multiclass T_VVR_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + IntRegs:$src3), + (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; } multiclass T_ZR_HVX_gen_pat { - def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2), - (MI VecPredRegs:$src1, IntRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, IntRegs:$src2), - (!cast(MI#"_128B") VecPredRegs128B:$src1, IntRegs:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxQR:$src1, IntRegs:$src2), + (MI HvxQR:$src1, IntRegs:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, IntRegs:$src2), + (MI HvxQR:$src1, IntRegs:$src2)>; } multiclass T_VZR_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3), - (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxQR:$src2, + IntRegs:$src3), + (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; } multiclass T_ZV_HVX_gen_pat { - def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2), - (MI VecPredRegs:$src1, VectorRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2), - (!cast(MI#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxQR:$src1, HvxVR:$src2), + (MI HvxQR:$src1, HvxVR:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, HvxVR:$src2), + (MI HvxQR:$src1, HvxVR:$src2)>; } multiclass T_R_HVX_gen_pat { def: Pat<(IntID IntRegs:$src1), - (MI IntRegs:$src1)>, - Requires<[UseHVXSgl]>; + (MI IntRegs:$src1)>; def: Pat<(!cast(IntID#"_128B") IntRegs:$src1), - (!cast(MI#"_128B") IntRegs:$src1)>, - Requires<[UseHVXDbl]>; + (MI IntRegs:$src1)>; } multiclass T_ZZ_HVX_gen_pat { - def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2), - (MI VecPredRegs:$src1, VecPredRegs:$src2)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2), - (!cast(MI#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxQR:$src1, HvxQR:$src2), + (MI HvxQR:$src1, HvxQR:$src2)>; + def: Pat<(!cast(IntID#"_128B") HvxQR:$src1, HvxQR:$src2), + (MI HvxQR:$src1, HvxQR:$src2)>; } multiclass T_VVI_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3), - (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3), - (!cast(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3), + (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + imm:$src3), + (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; } multiclass T_VVVI_HVX_gen_pat { - def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4), - (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4), - (!cast(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; + def: Pat<(!cast(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + HvxVR:$src3, imm:$src4), + (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; } multiclass T_WVVI_HVX_gen_pat { - def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4), - (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>, - Requires<[UseHVXSgl]>; - def: Pat<(!cast(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4), - (!cast(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>, - Requires<[UseHVXDbl]>; + def: Pat<(IntID HvxVP:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4), + (MI HvxVP:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; + def: Pat<(!cast(IntID#"_128B") HvxVP:$src1, HvxVR:$src2, + HvxVR:$src3, imm:$src4), + (MI HvxVP:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>; } def : T_R_pat ; Index: lib/Target/Hexagon/HexagonPatterns.td =================================================================== --- lib/Target/Hexagon/HexagonPatterns.td +++ lib/Target/Hexagon/HexagonPatterns.td @@ -17,14 +17,14 @@ def IsOrAdd: PatFrag<(ops node:$Addr, node:$off), (or node:$Addr, node:$off), [{ return isOrEquivalentToAdd(N); }]>; -def Iss4_6 : PatLeaf<(i32 imm), [{ +def IsVecOff : PatLeaf<(i32 imm), [{ int32_t V = N->getSExtValue(); - return isShiftedInt<4,6>(V); -}]>; - -def Iss4_7 : PatLeaf<(i32 imm), [{ - int32_t V = N->getSExtValue(); - return isShiftedInt<4,7>(V); + int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass); + assert(isPowerOf2_32(VecSize)); + if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0) + return false; + int32_t L = Log2_32(VecSize); + return isInt<4>(V >> L); }]>; def IsPow2_32 : PatLeaf<(i32 imm), [{ @@ -2738,149 +2738,80 @@ multiclass vS32b_ai_pats { // Aligned stores - def : Pat<(alignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr), - (V6_vS32b_ai IntRegs:$addr, 0, (VTSgl VectorRegs:$src1))>, - Requires<[UseHVXSgl]>; - def : Pat<(unalignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr), - (V6_vS32Ub_ai IntRegs:$addr, 0, (VTSgl VectorRegs:$src1))>, - Requires<[UseHVXSgl]>; - - // 128B Aligned stores - def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr), - (V6_vS32b_ai_128B IntRegs:$addr, 0, (VTDbl VectorRegs128B:$src1))>, - Requires<[UseHVXDbl]>; - def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1), IntRegs:$addr), - (V6_vS32Ub_ai_128B IntRegs:$addr, 0, (VTDbl VectorRegs128B:$src1))>, - Requires<[UseHVXDbl]>; + def : Pat<(alignedstore (VTSgl HvxVR:$src1), IntRegs:$addr), + (V6_vS32b_ai IntRegs:$addr, 0, (VTSgl HvxVR:$src1))>; + def : Pat<(unalignedstore (VTSgl HvxVR:$src1), IntRegs:$addr), + (V6_vS32Ub_ai IntRegs:$addr, 0, (VTSgl HvxVR:$src1))>; // Fold Add R+OFF into vector store. let AddedComplexity = 10 in { - def : Pat<(alignedstore (VTSgl VectorRegs:$src1), - (add IntRegs:$src2, Iss4_6:$offset)), - (V6_vS32b_ai IntRegs:$src2, Iss4_6:$offset, - (VTSgl VectorRegs:$src1))>, - Requires<[UseHVXSgl]>; - def : Pat<(unalignedstore (VTSgl VectorRegs:$src1), - (add IntRegs:$src2, Iss4_6:$offset)), - (V6_vS32Ub_ai IntRegs:$src2, Iss4_6:$offset, - (VTSgl VectorRegs:$src1))>, - Requires<[UseHVXSgl]>; - - // Fold Add R+OFF into vector store 128B. - def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1), - (add IntRegs:$src2, Iss4_7:$offset)), - (V6_vS32b_ai_128B IntRegs:$src2, Iss4_7:$offset, - (VTDbl VectorRegs128B:$src1))>, - Requires<[UseHVXDbl]>; - def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1), - (add IntRegs:$src2, Iss4_7:$offset)), - (V6_vS32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset, - (VTDbl VectorRegs128B:$src1))>, - Requires<[UseHVXDbl]>; + def : Pat<(alignedstore (VTSgl HvxVR:$src1), + (add IntRegs:$src2, IsVecOff:$offset)), + (V6_vS32b_ai IntRegs:$src2, imm:$offset, + (VTSgl HvxVR:$src1))>; + def : Pat<(unalignedstore (VTSgl HvxVR:$src1), + (add IntRegs:$src2, IsVecOff:$offset)), + (V6_vS32Ub_ai IntRegs:$src2, imm:$offset, + (VTSgl HvxVR:$src1))>; } } -defm : vS32b_ai_pats ; -defm : vS32b_ai_pats ; -defm : vS32b_ai_pats ; -defm : vS32b_ai_pats ; +defm : vS32b_ai_pats ; +defm : vS32b_ai_pats ; +defm : vS32b_ai_pats ; +defm : vS32b_ai_pats ; multiclass vL32b_ai_pats { // Aligned loads def : Pat < (VTSgl (alignedload IntRegs:$addr)), - (V6_vL32b_ai IntRegs:$addr, 0) >, - Requires<[UseHVXSgl]>; + (V6_vL32b_ai IntRegs:$addr, 0) >; def : Pat < (VTSgl (unalignedload IntRegs:$addr)), - (V6_vL32Ub_ai IntRegs:$addr, 0) >, - Requires<[UseHVXSgl]>; - - // 128B Load - def : Pat < (VTDbl (alignedload IntRegs:$addr)), - (V6_vL32b_ai_128B IntRegs:$addr, 0) >, - Requires<[UseHVXDbl]>; - def : Pat < (VTDbl (unalignedload IntRegs:$addr)), - (V6_vL32Ub_ai_128B IntRegs:$addr, 0) >, - Requires<[UseHVXDbl]>; + (V6_vL32Ub_ai IntRegs:$addr, 0) >; // Fold Add R+OFF into vector load. let AddedComplexity = 10 in { - def : Pat<(VTDbl (alignedload (add IntRegs:$src2, Iss4_7:$offset))), - (V6_vL32b_ai_128B IntRegs:$src2, Iss4_7:$offset)>, - Requires<[UseHVXDbl]>; - def : Pat<(VTDbl (unalignedload (add IntRegs:$src2, Iss4_7:$offset))), - (V6_vL32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset)>, - Requires<[UseHVXDbl]>; - - def : Pat<(VTSgl (alignedload (add IntRegs:$src2, Iss4_6:$offset))), - (V6_vL32b_ai IntRegs:$src2, Iss4_6:$offset)>, - Requires<[UseHVXSgl]>; - def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, Iss4_6:$offset))), - (V6_vL32Ub_ai IntRegs:$src2, Iss4_6:$offset)>, - Requires<[UseHVXSgl]>; + def : Pat<(VTSgl (alignedload (add IntRegs:$src2, IsVecOff:$offset))), + (V6_vL32b_ai IntRegs:$src2, imm:$offset)>; + def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, IsVecOff:$offset))), + (V6_vL32Ub_ai IntRegs:$src2, imm:$offset)>; } } -defm : vL32b_ai_pats ; -defm : vL32b_ai_pats ; -defm : vL32b_ai_pats ; -defm : vL32b_ai_pats ; +defm : vL32b_ai_pats ; +defm : vL32b_ai_pats ; +defm : vL32b_ai_pats ; +defm : vL32b_ai_pats ; multiclass STrivv_pats { - def : Pat<(alignedstore (VTSgl VecDblRegs:$src1), IntRegs:$addr), - (PS_vstorerw_ai IntRegs:$addr, 0, (VTSgl VecDblRegs:$src1))>, - Requires<[UseHVXSgl]>; - def : Pat<(unalignedstore (VTSgl VecDblRegs:$src1), IntRegs:$addr), - (PS_vstorerwu_ai IntRegs:$addr, 0, (VTSgl VecDblRegs:$src1))>, - Requires<[UseHVXSgl]>; - - def : Pat<(alignedstore (VTDbl VecDblRegs128B:$src1), IntRegs:$addr), - (PS_vstorerw_ai_128B IntRegs:$addr, 0, - (VTDbl VecDblRegs128B:$src1))>, - Requires<[UseHVXDbl]>; - def : Pat<(unalignedstore (VTDbl VecDblRegs128B:$src1), IntRegs:$addr), - (PS_vstorerwu_ai_128B IntRegs:$addr, 0, - (VTDbl VecDblRegs128B:$src1))>, - Requires<[UseHVXDbl]>; -} - -defm : STrivv_pats ; -defm : STrivv_pats ; -defm : STrivv_pats ; -defm : STrivv_pats ; + def : Pat<(alignedstore (VTSgl HvxVP:$src1), IntRegs:$addr), + (PS_vstorerw_ai IntRegs:$addr, 0, (VTSgl HvxVP:$src1))>; + def : Pat<(unalignedstore (VTSgl HvxVP:$src1), IntRegs:$addr), + (PS_vstorerwu_ai IntRegs:$addr, 0, (VTSgl HvxVP:$src1))>; +} + +defm : STrivv_pats ; +defm : STrivv_pats ; +defm : STrivv_pats ; +defm : STrivv_pats ; multiclass LDrivv_pats { def : Pat<(VTSgl (alignedload I32:$addr)), - (PS_vloadrw_ai I32:$addr, 0)>, - Requires<[UseHVXSgl]>; + (PS_vloadrw_ai I32:$addr, 0)>; def : Pat<(VTSgl (unalignedload I32:$addr)), - (PS_vloadrwu_ai I32:$addr, 0)>, - Requires<[UseHVXSgl]>; - - def : Pat<(VTDbl (alignedload I32:$addr)), - (PS_vloadrw_ai_128B I32:$addr, 0)>, - Requires<[UseHVXDbl]>; - def : Pat<(VTDbl (unalignedload I32:$addr)), - (PS_vloadrwu_ai_128B I32:$addr, 0)>, - Requires<[UseHVXDbl]>; + (PS_vloadrwu_ai I32:$addr, 0)>; } -defm : LDrivv_pats ; -defm : LDrivv_pats ; -defm : LDrivv_pats ; -defm : LDrivv_pats ; +defm : LDrivv_pats ; +defm : LDrivv_pats ; +defm : LDrivv_pats ; +defm : LDrivv_pats ; -let Predicates = [HasV60T,UseHVXSgl] in { - def: Pat<(select I1:$Pu, (v16i32 VectorRegs:$Vs), VectorRegs:$Vt), - (PS_vselect I1:$Pu, VectorRegs:$Vs, VectorRegs:$Vt)>; - def: Pat<(select I1:$Pu, (v32i32 VecDblRegs:$Vs), VecDblRegs:$Vt), - (PS_wselect I1:$Pu, VecDblRegs:$Vs, VecDblRegs:$Vt)>; -} -let Predicates = [HasV60T,UseHVXDbl] in { - def: Pat<(select I1:$Pu, (v32i32 VectorRegs128B:$Vs), VectorRegs128B:$Vt), - (PS_vselect_128B I1:$Pu, VectorRegs128B:$Vs, VectorRegs128B:$Vt)>; - def: Pat<(select I1:$Pu, (v64i32 VecDblRegs128B:$Vs), VecDblRegs128B:$Vt), - (PS_wselect_128B I1:$Pu, VecDblRegs128B:$Vs, VecDblRegs128B:$Vt)>; +let Predicates = [HasV60T] in { + def: Pat<(select I1:$Pu, (VecI32 HvxVR:$Vs), HvxVR:$Vt), + (PS_vselect I1:$Pu, HvxVR:$Vs, HvxVR:$Vt)>; + def: Pat<(select I1:$Pu, (VecPI32 HvxVP:$Vs), HvxVP:$Vt), + (PS_wselect I1:$Pu, HvxVP:$Vs, HvxVP:$Vt)>; } @@ -2889,14 +2820,8 @@ def HexagonVCOMBINE: SDNode<"HexagonISD::VCOMBINE", SDTHexagonVCOMBINE>; -def: Pat<(v32i32 (HexagonVCOMBINE (v16i32 VectorRegs:$Vs), - (v16i32 VectorRegs:$Vt))), - (V6_vcombine VectorRegs:$Vs, VectorRegs:$Vt)>, - Requires<[UseHVXSgl]>; -def: Pat<(v64i32 (HexagonVCOMBINE (v32i32 VecDblRegs:$Vs), - (v32i32 VecDblRegs:$Vt))), - (V6_vcombine_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>, - Requires<[UseHVXDbl]>; +def: Pat<(VecPI32 (HexagonVCOMBINE (VecI32 HvxVR:$Vs), (VecI32 HvxVR:$Vt))), + (V6_vcombine HvxVR:$Vs, HvxVR:$Vt)>; def SDTHexagonVPACK: SDTypeProfile<1, 3, [SDTCisSameAs<1, 2>, SDTCisInt<3>]>; @@ -2904,39 +2829,18 @@ def HexagonVPACK: SDNode<"HexagonISD::VPACK", SDTHexagonVPACK>; // 0 as the last argument denotes vpacke. 1 denotes vpacko -def: Pat<(v64i8 (HexagonVPACK (v64i8 VectorRegs:$Vs), - (v64i8 VectorRegs:$Vt), (i32 0))), - (V6_vpackeb VectorRegs:$Vs, VectorRegs:$Vt)>, - Requires<[UseHVXSgl]>; -def: Pat<(v64i8 (HexagonVPACK (v64i8 VectorRegs:$Vs), - (v64i8 VectorRegs:$Vt), (i32 1))), - (V6_vpackob VectorRegs:$Vs, VectorRegs:$Vt)>, - Requires<[UseHVXSgl]>; -def: Pat<(v32i16 (HexagonVPACK (v32i16 VectorRegs:$Vs), - (v32i16 VectorRegs:$Vt), (i32 0))), - (V6_vpackeh VectorRegs:$Vs, VectorRegs:$Vt)>, - Requires<[UseHVXSgl]>; -def: Pat<(v32i16 (HexagonVPACK (v32i16 VectorRegs:$Vs), - (v32i16 VectorRegs:$Vt), (i32 1))), - (V6_vpackoh VectorRegs:$Vs, VectorRegs:$Vt)>, - Requires<[UseHVXSgl]>; - -def: Pat<(v128i8 (HexagonVPACK (v128i8 VecDblRegs:$Vs), - (v128i8 VecDblRegs:$Vt), (i32 0))), - (V6_vpackeb_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>, - Requires<[UseHVXDbl]>; -def: Pat<(v128i8 (HexagonVPACK (v128i8 VecDblRegs:$Vs), - (v128i8 VecDblRegs:$Vt), (i32 1))), - (V6_vpackob_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>, - Requires<[UseHVXDbl]>; -def: Pat<(v64i16 (HexagonVPACK (v64i16 VecDblRegs:$Vs), - (v64i16 VecDblRegs:$Vt), (i32 0))), - (V6_vpackeh_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>, - Requires<[UseHVXDbl]>; -def: Pat<(v64i16 (HexagonVPACK (v64i16 VecDblRegs:$Vs), - (v64i16 VecDblRegs:$Vt), (i32 1))), - (V6_vpackoh_128B VecDblRegs:$Vs, VecDblRegs:$Vt)>, - Requires<[UseHVXDbl]>; +def: Pat<(VecI8 (HexagonVPACK (VecI8 HvxVR:$Vs), + (VecI8 HvxVR:$Vt), (i32 0))), + (V6_vpackeb HvxVR:$Vs, HvxVR:$Vt)>; +def: Pat<(VecI8 (HexagonVPACK (VecI8 HvxVR:$Vs), + (VecI8 HvxVR:$Vt), (i32 1))), + (V6_vpackob HvxVR:$Vs, HvxVR:$Vt)>; +def: Pat<(VecI16 (HexagonVPACK (VecI16 HvxVR:$Vs), + (VecI16 HvxVR:$Vt), (i32 0))), + (V6_vpackeh HvxVR:$Vs, HvxVR:$Vt)>; +def: Pat<(VecI16 (HexagonVPACK (VecI16 HvxVR:$Vs), + (VecI16 HvxVR:$Vt), (i32 1))), + (V6_vpackoh HvxVR:$Vs, HvxVR:$Vt)>; def V2I1: PatLeaf<(v2i1 PredRegs:$R)>; def V4I1: PatLeaf<(v4i1 PredRegs:$R)>; Index: lib/Target/Hexagon/HexagonPseudo.td =================================================================== --- lib/Target/Hexagon/HexagonPseudo.td +++ lib/Target/Hexagon/HexagonPseudo.td @@ -296,7 +296,7 @@ let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1, isBarrier = 1 in defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel; -//defm V6_vtran2x2_map : HexagonMapping<(outs VectorRegs:$Vy32, VectorRegs:$Vx32), (ins VectorRegs:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, VectorRegs:$Vx32in, IntRegs:$Rt32)>; +//defm V6_vtran2x2_map : HexagonMapping<(outs HvxVR:$Vy32, HvxVR:$Vx32), (ins HvxVR:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff HvxVR:$Vy32, HvxVR:$Vx32, HvxVR:$Vx32in, IntRegs:$Rt32)>; // The reason for the custom inserter is to record all ALLOCA instructions // in MachineFunctionInfo. @@ -419,51 +419,33 @@ class STrivv_template : V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>; -def PS_vstorerw_ai: STrivv_template, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vstorerwu_ai: STrivv_template, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vstorerw_ai_128B: STrivv_template, - Requires<[HasV60T,UseHVXDbl]>; -def PS_vstorerwu_ai_128B: STrivv_template, - Requires<[HasV60T,UseHVXDbl]>; +def PS_vstorerw_ai: STrivv_template, + Requires<[HasV60T,UseHVX]>; +def PS_vstorerwu_ai: STrivv_template, + Requires<[HasV60T,UseHVX]>; let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in class LDrivv_template : V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>; -def PS_vloadrw_ai: LDrivv_template, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vloadrwu_ai: LDrivv_template, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vloadrw_ai_128B: LDrivv_template, - Requires<[HasV60T,UseHVXDbl]>; -def PS_vloadrwu_ai_128B: LDrivv_template, - Requires<[HasV60T,UseHVXDbl]>; +def PS_vloadrw_ai: LDrivv_template, + Requires<[HasV60T,UseHVX]>; +def PS_vloadrwu_ai: LDrivv_template, + Requires<[HasV60T,UseHVX]>; // Store vector predicate pseudo. let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in { def PS_vstorerq_ai : STInst<(outs), - (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs:$src1), + (ins IntRegs:$base, s32_0Imm:$offset, HvxQR:$src1), ".error \"should not emit\" ", []>, - Requires<[HasV60T,UseHVXSgl]>; - - def PS_vstorerq_ai_128B : STInst<(outs), - (ins IntRegs:$base, s32_0Imm:$offset, VectorRegs:$src1), - ".error \"should not emit\" ", []>, - Requires<[HasV60T,UseHVXSgl]>; + Requires<[HasV60T,UseHVX]>; def PS_vloadrq_ai : STInst<(outs), - (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1), - ".error \"should not emit\" ", []>, - Requires<[HasV60T,UseHVXDbl]>; - - def PS_vloadrq_ai_128B : STInst<(outs), - (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1), + (ins IntRegs:$base, s32_0Imm:$offset, HvxQR:$src1), ".error \"should not emit\" ", []>, - Requires<[HasV60T,UseHVXDbl]>; + Requires<[HasV60T,UseHVX]>; } class VSELInst pattern = [], @@ -472,18 +454,12 @@ : InstHexagon; let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in { - def PS_vselect: VSELInst<(outs VectorRegs:$dst), - (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), "", []>, - Requires<[HasV60T,UseHVXSgl]>; - def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst), - (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3), - "", []>, Requires<[HasV60T,UseHVXDbl]>; - def PS_wselect: VSELInst<(outs VecDblRegs:$dst), - (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3), "", []>, - Requires<[HasV60T,UseHVXSgl]>; - def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst), - (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3), - "", []>, Requires<[HasV60T,UseHVXDbl]>; + def PS_vselect: VSELInst<(outs HvxVR:$dst), + (ins PredRegs:$src1, HvxVR:$src2, HvxVR:$src3), "", []>, + Requires<[HasV60T,UseHVX]>; + def PS_wselect: VSELInst<(outs HvxVP:$dst), + (ins PredRegs:$src1, HvxVP:$src2, HvxVP:$src3), "", []>, + Requires<[HasV60T,UseHVX]>; } // Store predicate. Index: lib/Target/Hexagon/HexagonRegisterInfo.h =================================================================== --- lib/Target/Hexagon/HexagonRegisterInfo.h +++ lib/Target/Hexagon/HexagonRegisterInfo.h @@ -30,7 +30,7 @@ class HexagonRegisterInfo : public HexagonGenRegisterInfo { public: - HexagonRegisterInfo(); + HexagonRegisterInfo(unsigned HwMode); /// Code Generation virtual methods... const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) Index: lib/Target/Hexagon/HexagonRegisterInfo.cpp =================================================================== --- lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -41,8 +41,9 @@ using namespace llvm; -HexagonRegisterInfo::HexagonRegisterInfo() - : HexagonGenRegisterInfo(Hexagon::R31) {} +HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) + : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, + 0/*PC*/, HwMode) {} bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const { @@ -85,11 +86,9 @@ return Int64; case PredRegsRegClassID: return Pred; - case VectorRegsRegClassID: - case VectorRegs128BRegClassID: + case HvxVRRegClassID: return VecSgl; - case VecDblRegsRegClassID: - case VecDblRegs128BRegClassID: + case HvxVPRegClassID: return VecDbl; default: break; @@ -218,7 +217,7 @@ break; } - if (!HII.isValidOffset(Opc, RealOffset)) { + if (!HII.isValidOffset(Opc, RealOffset, this)) { // If the offset is not valid, calculate the address in a temporary // register and use it with offset 0. auto &MRI = MF.getRegInfo(); @@ -272,8 +271,7 @@ case Hexagon::CtrRegs64RegClassID: case Hexagon::DoubleRegsRegClassID: return ISub[GenIdx]; - case Hexagon::VecDblRegsRegClassID: - case Hexagon::VecDblRegs128BRegClassID: + case Hexagon::HvxVPRegClassID: return VSub[GenIdx]; } Index: lib/Target/Hexagon/HexagonRegisterInfo.td =================================================================== --- lib/Target/Hexagon/HexagonRegisterInfo.td +++ lib/Target/Hexagon/HexagonRegisterInfo.td @@ -170,7 +170,6 @@ def PKTCOUNTHI: Rc<19, "pktcounthi", ["c19"]>, DwarfRegNum<[86]>; def UTIMERLO: Rc<30, "utimerlo", ["c30"]>, DwarfRegNum<[97]>; def UTIMERHI: Rc<31, "utimerhi", ["c31"]>, DwarfRegNum<[98]>; -} // Control registers pairs. let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { @@ -219,6 +218,20 @@ def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>; def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>; def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>; +} + +// HVX types + +def VecI1 : VariableValueType<[Hvx64, Hvx128, DefaultMode], [v512i1, v1024i1, v1024i1]>; +def VecI8 : VariableValueType<[Hvx64, Hvx128, DefaultMode], [v64i8, v128i8, v64i8]>; +def VecI16 : VariableValueType<[Hvx64, Hvx128, DefaultMode], [v32i16, v64i16, v32i16]>; +def VecI32 : VariableValueType<[Hvx64, Hvx128, DefaultMode], [v16i32, v32i32, v16i32]>; +def VecI64 : VariableValueType<[Hvx64, Hvx128, DefaultMode], [v8i64, v16i64, v8i64]>; +def VecPI8 : VariableValueType<[Hvx64, Hvx128, DefaultMode], [v128i8, v256i8, v128i8]>; +def VecPI16 : VariableValueType<[Hvx64, Hvx128, DefaultMode], [v64i16, v128i16, v64i16]>; +def VecPI32 : VariableValueType<[Hvx64, Hvx128, DefaultMode], [v32i32, v64i32, v32i32]>; +def VecPI64 : VariableValueType<[Hvx64, Hvx128, DefaultMode], [v16i64, v32i64, v16i64]>; + // Register classes. // @@ -226,54 +239,43 @@ // allocation order... // def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, - (add (sequence "R%u", 0, 9), - (sequence "R%u", 12, 28), - R10, R11, R29, R30, R31)> { -} + (add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28), + R10, R11, R29, R30, R31)>; // Registers are listed in reverse order for allocation preference reasons. def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32, - (add R23, R22, R21, R20, R19, R18, R17, - R16, R7, R6, R5, R4, R3, R2, R1, R0)>; + (add R23, R22, R21, R20, R19, R18, R17, R16, + R7, R6, R5, R4, R3, R2, R1, R0)>; def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32, - (add R7, R6, R5, R4, R3, R2, R1, R0)> ; + (add R7, R6, R5, R4, R3, R2, R1, R0)> ; def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, - (add (sequence "D%u", 0, 4), - (sequence "D%u", 6, 13), D5, D14, D15)>; + (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>; def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64, - (add D11, D10, D9, D8, D3, D2, D1, - D0)>; - -def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512, - (add (sequence "V%u", 0, 31))>; + (add D11, D10, D9, D8, D3, D2, D1, D0)>; -def VecDblRegs : RegisterClass<"Hexagon", - [v128i8, v64i16, v32i32, v16i64], 1024, - (add (sequence "W%u", 0, 15))>; - -def VectorRegs128B : RegisterClass<"Hexagon", - [v128i8, v64i16, v32i32, v16i64], 1024, - (add (sequence "V%u", 0, 31))>; - -def VecDblRegs128B : RegisterClass<"Hexagon", - [v256i8,v128i16,v64i32,v32i64], 2048, - (add (sequence "W%u", 0, 15))>; +def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32, VecI64], 512, + (add (sequence "V%u", 0, 31))> { + let VRI = VariableRegInfo<[Hvx64, Hvx128, DefaultMode], + [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; +} -def VecPredRegs : RegisterClass<"Hexagon", [v512i1], 512, - (add (sequence "Q%u", 0, 3))>; +def HvxVP : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32, VecPI64], 1024, + (add (sequence "W%u", 0, 15))> { + let VRI = VariableRegInfo<[Hvx64, Hvx128, DefaultMode], + [RegInfo<1024,1024,1024>, RegInfo<2048,2048,2048>, RegInfo<1024,1024,1024>]>; +} -def VecPredRegs128B : RegisterClass<"Hexagon", [v1024i1], 1024, - (add (sequence "Q%u", 0, 3))>; +def HvxQR : RegisterClass<"Hexagon", [VecI1], 512, (add Q0, Q1, Q2, Q3)> { + let VRI = VariableRegInfo<[Hvx64, Hvx128, DefaultMode], + [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; +} +let Size = 32 in def PredRegs : RegisterClass<"Hexagon", - [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, - (add (sequence "P%u", 0, 3))> -{ - let Size = 32; -} + [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>; let Size = 32 in def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; @@ -297,9 +299,8 @@ // The function RegisterMatchesArch() uses this list for validation. let isAllocatable = 0 in def V62Regs : RegisterClass<"Hexagon", [i32], 32, - (add FRAMELIMIT, FRAMEKEY, C17_16, - PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT, - UTIMERLO, UTIMERHI, UTIMER)>; + (add FRAMELIMIT, FRAMEKEY, C17_16, PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT, + UTIMERLO, UTIMERHI, UTIMER)>; def HexagonCSR Index: lib/Target/Hexagon/HexagonSubtarget.h =================================================================== --- lib/Target/Hexagon/HexagonSubtarget.h +++ lib/Target/Hexagon/HexagonSubtarget.h @@ -17,6 +17,7 @@ #include "HexagonFrameLowering.h" #include "HexagonISelLowering.h" #include "HexagonInstrInfo.h" +#include "HexagonRegisterInfo.h" #include "HexagonSelectionDAGInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetSubtargetInfo.h" @@ -53,6 +54,7 @@ private: std::string CPUString; HexagonInstrInfo InstrInfo; + HexagonRegisterInfo RegInfo; HexagonTargetLowering TLInfo; HexagonSelectionDAGInfo TSInfo; HexagonFrameLowering FrameLowering; @@ -70,7 +72,7 @@ } const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; } const HexagonRegisterInfo *getRegisterInfo() const override { - return &InstrInfo.getRegisterInfo(); + return &RegInfo; } const HexagonTargetLowering *getTargetLowering() const override { return &TLInfo; Index: lib/Target/Hexagon/HexagonSubtarget.cpp =================================================================== --- lib/Target/Hexagon/HexagonSubtarget.cpp +++ lib/Target/Hexagon/HexagonSubtarget.cpp @@ -115,9 +115,8 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU), - InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), - FrameLowering() { - + InstrInfo(initializeSubtargetDependencies(CPU, FS)), + RegInfo(getHwMode()), TLInfo(TM, *this), FrameLowering() { initializeEnvironment(); // Initialize scheduling itinerary for the specified CPU. Index: lib/Target/Hexagon/HexagonVLIWPacketizer.cpp =================================================================== --- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -459,7 +459,7 @@ unsigned FrameSize = MF.getFrameInfo().getStackSize(); MachineOperand &Off = MI.getOperand(1); int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE); - if (HII->isValidOffset(Opc, NewOff)) { + if (HII->isValidOffset(Opc, NewOff, HRI)) { Off.setImm(NewOff); return true; } @@ -803,7 +803,7 @@ const MCInstrDesc& MCID = PI.getDesc(); const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF); - if (DisableVecDblNVStores && VecRC == &Hexagon::VecDblRegsRegClass) + if (DisableVecDblNVStores && VecRC == &Hexagon::HvxVPRegClass) return false; // predicate .new