Index: lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
===================================================================
--- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -330,8 +330,7 @@
   }
 
   bool isSCSrcB64() const {
-    return isRegOrInlineNoMods(AMDGPU::SReg_64_WITH_SUBREGSRegClassID,
-                               MVT::i64);
+    return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64);
   }
 
   bool isSCSrcF16() const {
@@ -347,8 +346,7 @@
   }
 
   bool isSCSrcF64() const {
-    return isRegOrInlineNoMods(AMDGPU::SReg_64_WITH_SUBREGSRegClassID,
-                               MVT::f64);
+    return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64);
   }
 
   bool isSSrcB32() const {
@@ -881,6 +879,10 @@
     return AMDGPU::isVI(getSTI());
   }
 
+  bool isGFX9() const {
+    return AMDGPU::isGFX9(getSTI());
+  }
+
   bool hasInv2PiInlineImm() const {
     return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];
   }
@@ -1459,6 +1461,10 @@
     .Case("tma_hi", AMDGPU::TMA_HI)
     .Case("tba_lo", AMDGPU::TBA_LO)
     .Case("tba_hi", AMDGPU::TBA_HI)
+    .Case("src_shared_base", AMDGPU::SRC_SHARED_BASE)
+    .Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT)
+    .Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE)
+    .Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT)
     .Default(0);
 }
 
@@ -2444,6 +2450,16 @@
 
 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
                                            unsigned RegNo) const {
+  if (!isGFX9()) {
+    switch (RegNo) {
+    case AMDGPU::SRC_SHARED_BASE:
+    case AMDGPU::SRC_SHARED_LIMIT:
+    case AMDGPU::SRC_PRIVATE_BASE:
+    case AMDGPU::SRC_PRIVATE_LIMIT:
+      return false;
+    }
+  }
+
   if (isCI())
     return true;
 
Index: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
===================================================================
--- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -259,6 +259,7 @@
 bool isSI(const MCSubtargetInfo &STI);
 bool isCI(const MCSubtargetInfo &STI);
 bool isVI(const MCSubtargetInfo &STI);
+bool isGFX9(const MCSubtargetInfo &STI);
 
 /// If \p Reg is a pseudo reg, return the correct hardware register given
 /// \p STI otherwise return \p Reg.
Index: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
===================================================================
--- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -529,6 +529,10 @@
   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
 }
 
+bool isGFX9(const MCSubtargetInfo &STI) {
+  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
+}
+
 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
 
   switch(Reg) {
Index: test/MC/AMDGPU/aperture-regs.s
===================================================================
--- /dev/null
+++ test/MC/AMDGPU/aperture-regs.s
@@ -0,0 +1,18 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx800 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX8 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GFX9 %s
+
+// GFX8: error: not a valid operand.
+// GFX9: s_mov_b64 s[0:1], src_shared_base ; encoding: [0xeb,0x01,0x80,0xbe]
+s_mov_b64 s[0:1], src_shared_base
+
+// GFX8: error: not a valid operand.
+// GFX9: s_mov_b64 s[2:3], src_shared_limit ; encoding: [0xec,0x01,0x82,0xbe]
+s_mov_b64 s[2:3], src_shared_limit
+
+// GFX8: error: not a valid operand.
+// GFX9: s_mov_b64 s[4:5], src_private_base ; encoding: [0xed,0x01,0x84,0xbe]
+s_mov_b64 s[4:5], src_private_base
+
+// GFX8: error: not a valid operand.
+// GFX9: s_mov_b64 s[6:7], src_private_limit ; encoding: [0xee,0x01,0x86,0xbe]
+s_mov_b64 s[6:7], src_private_limit