Index: lib/Target/PowerPC/PPCInstrInfo.h
===================================================================
--- lib/Target/PowerPC/PPCInstrInfo.h
+++ lib/Target/PowerPC/PPCInstrInfo.h
@@ -306,6 +306,15 @@
    return isSignOrZeroExtended(MI, false, depth);
   }
 
+  bool convertToImmediateForm(MachineInstr &MI) const;
+
+  // This is used to find the "true" source register for n
+  // Machine instruction. Returns the original SrcReg unless it is the target
+  // of a copy-like operation, in which case we chain backwards through all
+  // such operations to the ultimate source register.  If a
+  // physical register is encountered, we stop the search.
+  static unsigned lookThruCopyLike(unsigned SrcReg,
+                                   const MachineRegisterInfo *MRI);
 };
 
 }
Index: lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- lib/Target/PowerPC/PPCInstrInfo.cpp
+++ lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -37,6 +37,7 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/ADT/Statistic.h"
 
 using namespace llvm;
 
@@ -46,6 +47,9 @@
 #define GET_INSTRINFO_CTOR_DTOR
 #include "PPCGenInstrInfo.inc"
 
+STATISTIC(MissedConvertibleImmediateInstrs,
+          "Number of compare-immediate instructions fed by constants.");
+
 static cl::
 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
             cl::desc("Disable analysis for CTR loops"));
@@ -2128,3 +2132,317 @@
   return false;
 }
 
+unsigned PPCInstrInfo::lookThruCopyLike(unsigned SrcReg,
+                                        const MachineRegisterInfo *MRI) {
+  while (true) {
+    MachineInstr *MI = MRI->getVRegDef(SrcReg);
+    if (!MI->isCopyLike())
+      return SrcReg;
+
+    unsigned CopySrcReg;
+    if (MI->isCopy())
+      CopySrcReg = MI->getOperand(1).getReg();
+    else {
+      assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike");
+      CopySrcReg = MI->getOperand(2).getReg();
+    }
+
+    if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg))
+      return CopySrcReg;
+
+    SrcReg = CopySrcReg;
+  }
+}
+
+// If this instruction has an immediate form and one of its operands is a
+// result of a load-immediate, convert it to the immediate form if the constant
+// is in range.
+bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI) const {
+  MachineFunction *MF = MI.getParent()->getParent();
+  MachineRegisterInfo *MRI = &MF->getRegInfo();
+  MachineInstr *DefMI = nullptr;
+  unsigned ConstantOperand = ~0U;
+  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
+    if (!MI.getOperand(i).isReg())
+      continue;
+    unsigned Reg = MI.getOperand(i).getReg();
+    if (!TargetRegisterInfo::isVirtualRegister(Reg))
+      continue;
+    unsigned TrueReg = lookThruCopyLike(Reg, MRI);
+    if (TargetRegisterInfo::isVirtualRegister(TrueReg)) {
+      DefMI = MRI->getVRegDef(TrueReg);
+      if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
+        ConstantOperand = i;
+        break;
+      }
+    }
+  }
+  if (ConstantOperand == ~0U || !DefMI->getOperand(1).isImm())
+    return false;
+
+  int64_t Immediate = DefMI->getOperand(1).getImm();
+  // Sign-extend to 64-bits.
+  int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
+    (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
+
+  bool ReplaceWithLI = false;
+  bool Is64BitLI = false;
+  int64_t NewImm = 0;
+  unsigned Opc = MI.getOpcode();
+  switch (Opc) {
+  default: return false;
+
+  // FIXME: Immediate comparisons fed by a load-immediate. Any branches or
+  // selects it feeds can be converted to unconditional branches/selects.
+  case PPC::CMPWI:
+  case PPC::CMPLWI:
+  case PPC::CMPDI:
+  case PPC::CMPLDI:
+    MissedConvertibleImmediateInstrs++;
+    return false;
+
+  // Immediate forms - may simply be convertable to an LI.
+  case PPC::ADDI:
+  case PPC::ADDI8: {
+    // Does the sum fit in a 16-bit signed field?
+    int64_t Addend = MI.getOperand(2).getImm();
+    if (isInt<16>(Addend + SExtImm)) {
+      ReplaceWithLI = true;
+      Is64BitLI = Opc == PPC::ADDI8;
+      NewImm = Addend + SExtImm;
+      break;
+    }
+  }
+  case PPC::RLDICL:
+  case PPC::RLDICL_32:
+  case PPC::RLDICL_32_64: {
+    // Use APInt's rotate function.
+    int64_t SH = MI.getOperand(2).getImm();
+    int64_t MB = MI.getOperand(3).getImm();
+    APInt InVal(Opc == PPC::RLDICL ? 64 : 32, SExtImm, true);
+    InVal = InVal.rotl(SH);
+    uint64_t Mask = (1LU << (63 - MB + 1)) - 1;
+    InVal &= Mask;
+    // Can't replace negative values with an LI as that will sign-extend
+    // and not clear the left bits.
+    if (isUInt<16>(InVal.getSExtValue())) {
+      ReplaceWithLI = true;
+      Is64BitLI = Opc != PPC::RLDICL_32;
+      NewImm = InVal.getSExtValue();
+      break;
+    }
+    return false;
+  }
+  case PPC::ORI:
+  case PPC::ORI8:
+  case PPC::XORI:
+  case PPC::XORI8: {
+    int64_t LogicalImm = MI.getOperand(2).getImm();
+    int64_t Result = 0;
+    if (Opc == PPC::ORI || Opc == PPC::ORI8)
+      Result = LogicalImm | SExtImm;
+    else
+      Result = LogicalImm ^ SExtImm;
+    if (isInt<16>(Result)) {
+      ReplaceWithLI = true;
+      Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
+      NewImm = Result;
+      break;
+    }
+    return false;
+  }
+
+  // Additions - commutable.
+  case PPC::ADD4:
+  case PPC::ADD8: {
+    DEBUG(dbgs() << "Converted reg/reg instruction:\n");
+    DEBUG(MI.dump());
+    MachineOperand Op1 = MI.getOperand(1);
+    MachineOperand Op2 = MI.getOperand(2);
+    MI.setDesc(get(Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8));
+    MI.RemoveOperand(2);
+    MI.RemoveOperand(1);
+    MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+        .add(ConstantOperand == 1 ? Op2 : Op1)
+        .addImm(Immediate);
+    MRI->setRegClass(MI.getOperand(1).getReg(),
+                     Opc == PPC::ADD4 ? &PPC::GPRC_and_GPRC_NOR0RegClass :
+                     &PPC::G8RC_and_G8RC_NOX0RegClass);
+    DEBUG(dbgs() << "To reg/imm instruction:\n");
+    DEBUG(MI.dump());
+    return true;
+  }
+  // Subtraction, compares - non-commutable.
+  case PPC::SUBFC:
+  case PPC::SUBFC8: {
+    if (ConstantOperand != 2)
+      return false;
+    unsigned NewOpc = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
+    DEBUG(dbgs() << "Converted:\n");
+    DEBUG(MI.dump());
+    DEBUG(dbgs() << "Fed by:\n");
+    DEBUG(DefMI->dump());
+    MI.RemoveOperand(2);
+    MI.setDesc(get(NewOpc));
+    MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+        .addImm(Immediate);
+    DEBUG(dbgs() << "To:\n");
+    DEBUG(MI.dump());
+    return true;
+  }
+  case PPC::CMPLW:
+  case PPC::CMPLD:
+    if (!isUInt<16>(SExtImm))
+      return false;
+    LLVM_FALLTHROUGH;
+  case PPC::CMPW:
+  case PPC::CMPD: {
+    if (ConstantOperand != 2)
+      return false;
+    unsigned NewOpc = Opc == PPC::CMPLW ? PPC::CMPLWI :
+                      Opc == PPC::CMPLD ? PPC::CMPLDI :
+                      Opc == PPC::CMPW  ? PPC::CMPWI  : PPC::CMPDI;
+    DEBUG(dbgs() << "Converted:\n");
+    DEBUG(MI.dump());
+    DEBUG(dbgs() << "Fed by:\n");
+    DEBUG(DefMI->dump());
+    MI.RemoveOperand(2);
+    MI.setDesc(get(NewOpc));
+    MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+        .addImm(Immediate);
+    DEBUG(dbgs() << "To:\n");
+    DEBUG(MI.dump());
+    return true;
+  }
+
+  case PPC::SLD:
+  case PPC::SLDo: {
+    if (ConstantOperand == 2) {
+      DEBUG(dbgs() << "Converted:\n");
+      DEBUG(MI.dump());
+      DEBUG(dbgs() << "Fed by:\n");
+      DEBUG(DefMI->dump());
+      MI.RemoveOperand(2);
+      uint64_t SH = Immediate & 0x3F;
+      uint64_t ME = 63 - SH;
+      // According to the ISA, shifting by 64-127 is zero. It is important to
+      // keep in mind that only bits 57-63 are considered. So the result is zero
+      // if bit 57 is set in the shift register.
+      if (SExtImm & 0x40) {
+        ReplaceWithLI = true;
+        Is64BitLI = true;
+        NewImm = 0;
+        break;
+      }
+      // Shifting by zero is redundant.
+      if (SH == 0)
+        MI.setDesc(get(PPC::COPY));
+      else {
+        MI.setDesc(get(Opc == PPC::SLD ? PPC::RLDICR : PPC::RLDICRo));
+        MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+            .addImm(SH).addImm(ME);
+      }
+      DEBUG(dbgs() << "To:\n");
+      DEBUG(MI.dump());
+      return true;
+    }
+    break;
+  }
+  case PPC::SRD:
+  case PPC::SRDo:
+    if (ConstantOperand == 2) {
+      DEBUG(dbgs() << "Converted:\n");
+      DEBUG(MI.dump());
+      DEBUG(dbgs() << "Fed by:\n");
+      DEBUG(DefMI->dump());
+      MI.RemoveOperand(2);
+      uint64_t MB = Immediate & 0x3F;
+      uint64_t SH = 64 - MB;
+      // According to the ISA, shifting by 64-127 is zero. It is important to
+      // keep in mind that only bits 57-63 are considered. So the result is zero
+      // if bit 57 is set in the shift register.
+      if (SExtImm & 0x40) {
+        ReplaceWithLI = true;
+        Is64BitLI = true;
+        NewImm = 0;
+        break;
+      }
+      // Shifting by zero is redundant.
+      if (SH == 0)
+        MI.setDesc(get(PPC::COPY));
+      else {
+        MI.setDesc(get(Opc == PPC::SRD ? PPC::RLDICL : PPC::RLDICLo));
+        MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+            .addImm(SH).addImm(MB);
+      }
+      DEBUG(dbgs() << "To:\n");
+      DEBUG(MI.dump());
+      return true;
+    }
+    break;
+  case PPC::ANDo:
+  case PPC::AND8o:
+  case PPC::OR:
+  case PPC::OR8:
+  case PPC::XOR:
+  case PPC::XOR8: {
+    unsigned ImmOpc = 0;
+    switch (Opc) {
+    case PPC::ANDo:
+      ImmOpc = PPC::ANDIo;
+      break;
+    case PPC::AND8o:
+      ImmOpc = PPC::ANDIo8;
+      break;
+    case PPC::OR:
+      ImmOpc = PPC::ORI;
+      break;
+    case PPC::OR8:
+      ImmOpc = PPC::ORI8;
+      break;
+    case PPC::XOR:
+      ImmOpc = PPC::XORI;
+      break;
+    case PPC::XOR8:
+      ImmOpc = PPC::XORI8;
+      break;
+    }
+    if (((uint64_t)Immediate & ~0x7FFFuLL) == 0) {
+      DEBUG(dbgs() << "Converted reg/reg instruction:\n");
+      DEBUG(MI.dump());
+      MachineOperand Op1 = MI.getOperand(1);
+      MachineOperand Op2 = MI.getOperand(2);
+      MI.setDesc(get(ImmOpc));
+      MI.RemoveOperand(2);
+      MI.RemoveOperand(1);
+      MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+          .add(ConstantOperand == 1 ? Op2 : Op1)
+          .addImm(Immediate);
+      DEBUG(dbgs() << "To reg/imm instruction:\n");
+      DEBUG(MI.dump());
+      return true;
+    }
+  }
+  }
+
+  if (ReplaceWithLI) {
+    DEBUG(dbgs() << "Replacing instruction:\n");
+    DEBUG(MI.dump());
+    DEBUG(dbgs() << "Fed by:\n");
+    DEBUG(DefMI->dump());
+    // Remove existing operands.
+    for (int i = MI.getNumOperands() - 1; i > 0; i--)
+      MI.RemoveOperand(i);
+
+    // Replace the instruction.
+    MI.setDesc(get(Is64BitLI ? PPC::LI8 : PPC::LI));
+
+    // Set the immediate.
+    MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+        .addImm(NewImm);
+    DEBUG(dbgs() << "With:\n");
+    DEBUG(MI.dump());
+    return true;
+  }
+  return false;
+}
Index: lib/Target/PowerPC/PPCMIPeephole.cpp
===================================================================
--- lib/Target/PowerPC/PPCMIPeephole.cpp
+++ lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -72,10 +72,6 @@
   // Perform peepholes.
   bool simplifyCode(void);
 
-  // Find the "true" register represented by SrcReg (following chains
-  // of copies and subreg_to_reg operations).
-  unsigned lookThruCopyLike(unsigned SrcReg);
-
 public:
   // Main entry point for this pass.
   bool runOnMachineFunction(MachineFunction &MF) override {
@@ -100,6 +96,31 @@
   bool Simplified = false;
   MachineInstr* ToErase = nullptr;
 
+  // Fixed-point conversion of reg/reg instructions fed by load-immediate
+  // into reg/imm instructions. FIXME: This is expensive, control it with
+  // an option.
+  bool SomethingChanged = false;
+  do {
+    SomethingChanged = false;
+    for (MachineBasicBlock &MBB : *MF) {
+      for (MachineInstr &MI : MBB) {
+        if (MI.isDebugValue())
+          continue;
+
+        if (TII->convertToImmediateForm(MI)) {
+          // We don't erase anything in case the def has other uses. Let DCE
+          // remove it if it can be removed.
+          DEBUG(dbgs() << "Converted instruction to imm form: ");
+          DEBUG(MI.dump());
+          NumConvertedToImmediateForm++;
+          SomethingChanged = true;
+          Simplified = true;
+          continue;
+        }
+      }
+    }
+  } while (SomethingChanged);
+
   for (MachineBasicBlock &MBB : *MF) {
     for (MachineInstr &MI : MBB) {
 
@@ -134,8 +155,10 @@
           //   XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed.
           // We have to look through chains of COPY and SUBREG_TO_REG
           // to find the real source values for comparison.
-          unsigned TrueReg1 = lookThruCopyLike(MI.getOperand(1).getReg());
-          unsigned TrueReg2 = lookThruCopyLike(MI.getOperand(2).getReg());
+          unsigned TrueReg1 =
+            TII->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
+          unsigned TrueReg2 =
+            TII->lookThruCopyLike(MI.getOperand(2).getReg(), MRI);
 
           if (TrueReg1 == TrueReg2
               && TargetRegisterInfo::isVirtualRegister(TrueReg1)) {
@@ -149,7 +172,8 @@
             auto isConversionOfLoadAndSplat = [=]() -> bool {
               if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS)
                 return false;
-              unsigned DefReg = lookThruCopyLike(DefMI->getOperand(1).getReg());
+              unsigned DefReg =
+                TII->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
               if (TargetRegisterInfo::isVirtualRegister(DefReg)) {
                 MachineInstr *LoadMI = MRI->getVRegDef(DefReg);
                 if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX)
@@ -176,9 +200,9 @@
             if (DefOpc == PPC::XXPERMDI) {
               unsigned FeedImmed = DefMI->getOperand(3).getImm();
               unsigned FeedReg1
-                = lookThruCopyLike(DefMI->getOperand(1).getReg());
+                = TII->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
               unsigned FeedReg2
-                = lookThruCopyLike(DefMI->getOperand(2).getReg());
+                = TII->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI);
 
               if ((FeedImmed == 0 || FeedImmed == 3) && FeedReg1 == FeedReg2) {
                 DEBUG(dbgs()
@@ -236,7 +260,8 @@
       case PPC::XXSPLTW: {
         unsigned MyOpcode = MI.getOpcode();
         unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
-        unsigned TrueReg = lookThruCopyLike(MI.getOperand(OpNo).getReg());
+        unsigned TrueReg =
+          TII->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI);
         if (!TargetRegisterInfo::isVirtualRegister(TrueReg))
           break;
         MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
@@ -298,7 +323,8 @@
       }
       case PPC::XVCVDPSP: {
         // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant.
-        unsigned TrueReg = lookThruCopyLike(MI.getOperand(1).getReg());
+        unsigned TrueReg =
+          TII->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
         if (!TargetRegisterInfo::isVirtualRegister(TrueReg))
           break;
         MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
@@ -306,8 +332,10 @@
         // This can occur when building a vector of single precision or integer
         // values.
         if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
-          unsigned DefsReg1 = lookThruCopyLike(DefMI->getOperand(1).getReg());
-          unsigned DefsReg2 = lookThruCopyLike(DefMI->getOperand(2).getReg());
+          unsigned DefsReg1 =
+            TII->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
+          unsigned DefsReg2 =
+            TII->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI);
           if (!TargetRegisterInfo::isVirtualRegister(DefsReg1) ||
               !TargetRegisterInfo::isVirtualRegister(DefsReg2))
             break;
@@ -354,7 +382,7 @@
       }
       case PPC::EXTSW:
       case PPC::EXTSW_32:
-      case PPC::EXTSW_32_64:{
+      case PPC::EXTSW_32_64: {
         if (!EnableSExtElimination) break;
         unsigned NarrowReg = MI.getOperand(1).getReg();
         if (!TargetRegisterInfo::isVirtualRegister(NarrowReg))
@@ -441,36 +469,6 @@
   return Simplified;
 }
 
-// This is used to find the "true" source register for an
-// XXPERMDI instruction, since MachineCSE does not handle the
-// "copy-like" operations (Copy and SubregToReg).  Returns
-// the original SrcReg unless it is the target of a copy-like
-// operation, in which case we chain backwards through all
-// such operations to the ultimate source register.  If a
-// physical register is encountered, we stop the search.
-unsigned PPCMIPeephole::lookThruCopyLike(unsigned SrcReg) {
-
-  while (true) {
-
-    MachineInstr *MI = MRI->getVRegDef(SrcReg);
-    if (!MI->isCopyLike())
-      return SrcReg;
-
-    unsigned CopySrcReg;
-    if (MI->isCopy())
-      CopySrcReg = MI->getOperand(1).getReg();
-    else {
-      assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike");
-      CopySrcReg = MI->getOperand(2).getReg();
-    }
-
-    if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg))
-      return CopySrcReg;
-
-    SrcReg = CopySrcReg;
-  }
-}
-
 } // end default namespace
 
 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
Index: test/CodeGen/PowerPC/comparisonOps32.ll
===================================================================
--- test/CodeGen/PowerPC/comparisonOps32.ll
+++ test/CodeGen/PowerPC/comparisonOps32.ll
@@ -0,0 +1,449 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@ga = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @compOp1(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp1:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    subf r5, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %cmp1 = icmp ult i32 %a, %b
+  %. = select i1 %cmp1, i32 -1, i32 1
+  %retval.0 = select i1 %cmp, i32 0, i32 %.
+  ret i32 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @compOp2(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp2:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    subf r5, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %cmp1 = icmp ugt i32 %a, %b
+  %. = select i1 %cmp1, i32 1, i32 -1
+  %retval.0 = select i1 %cmp, i32 0, i32 %.
+  ret i32 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+; FIXME: the extsw is unnecessary but is in the DAG as well.
+define signext i32 @compOp3(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp3:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    subf r5, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r5
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %not.cmp1 = icmp ne i32 %a, %b
+  %. = sext i1 %not.cmp1 to i32
+  %retval.0 = select i1 %cmp, i32 1, i32 %.
+  ret i32 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+; FIXME: the extsw is unnecessary but is in the DAG as well.
+define signext i32 @compOp4(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp4:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    subf r5, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r5
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %cmp1 = icmp ult i32 %a, %b
+  %. = sext i1 %cmp1 to i32
+  %retval.0 = select i1 %cmp, i32 1, i32 %.
+  ret i32 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+; FIXME: the extsw is unnecessary but is in the DAG as well.
+define signext i32 @compOp5(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp5:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    subf r5, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r5
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %not.cmp1 = icmp ne i32 %a, %b
+  %. = zext i1 %not.cmp1 to i32
+  %retval.0 = select i1 %cmp, i32 -1, i32 %.
+  ret i32 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+; FIXME: this is still done with compares, we may fix that in the future
+define signext i32 @compOp6(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp6:
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %cmp1 = icmp ugt i32 %a, %b
+  %. = zext i1 %cmp1 to i32
+  %retval.0 = select i1 %cmp, i32 -1, i32 %.
+  ret i32 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @compOp7(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp7:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    subf r5, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %cmp1 = icmp ult i32 %a, %b
+  %cond = select i1 %cmp1, i32 -1, i32 1
+  %cond2 = select i1 %cmp, i32 0, i32 %cond
+  ret i32 %cond2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @compOp8(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp8:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    subf r5, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %cmp1 = icmp ugt i32 %a, %b
+  %cond = select i1 %cmp1, i32 1, i32 -1
+  %cond2 = select i1 %cmp, i32 0, i32 %cond
+  ret i32 %cond2
+}
+
+; Function Attrs: norecurse nounwind readnone
+; FIXME: the extsw is unnecessary but is in the DAG as well.
+define signext i32 @compOp9(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp9:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    subf r5, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r5
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %not.cmp1 = icmp ne i32 %a, %b
+  %cond = zext i1 %not.cmp1 to i32
+  %cond2 = select i1 %cmp, i32 -1, i32 %cond
+  ret i32 %cond2
+}
+
+; Function Attrs: norecurse nounwind readnone
+; FIXME: this is still done with compares, we may fix that in the future
+define signext i32 @compOp10(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp10:
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %cmp1 = icmp ugt i32 %a, %b
+  %cond = zext i1 %cmp1 to i32
+  %cond2 = select i1 %cmp, i32 -1, i32 %cond
+  ret i32 %cond2
+}
+
+; Function Attrs: norecurse nounwind readnone
+; FIXME: the extsw is unnecessary but is in the DAG as well.
+define signext i32 @compOp11(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp11:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    subf r5, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r5
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %not.cmp1 = icmp ne i32 %a, %b
+  %cond = sext i1 %not.cmp1 to i32
+  %cond2 = select i1 %cmp, i32 1, i32 %cond
+  ret i32 %cond2
+}
+
+; Function Attrs: norecurse nounwind readnone
+; FIXME: the extsw is unnecessary but is in the DAG as well.
+define signext i32 @compOp12(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: compOp12:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    subf r5, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r5
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %cmp1 = icmp ult i32 %a, %b
+  %cond = sext i1 %cmp1 to i32
+  %cond2 = select i1 %cmp, i32 1, i32 %cond
+  ret i32 %cond2
+}
+
+; Function Attrs: norecurse nounwind
+define void @store1(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store1:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    subf r6, r4, r3
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r6
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp eq i32 %a, %b
+  %cmp1.i = icmp ult i32 %a, %b
+  %..i = select i1 %cmp1.i, i32 -1, i32 1
+  %retval.0.i = select i1 %cmp.i, i32 0, i32 %..i
+  store i32 %retval.0.i, i32* @ga, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store2(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store2:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    subf r6, r4, r3
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r6
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp eq i32 %a, %b
+  %cmp1.i = icmp ugt i32 %a, %b
+  %..i = select i1 %cmp1.i, i32 1, i32 -1
+  %retval.0.i = select i1 %cmp.i, i32 0, i32 %..i
+  store i32 %retval.0.i, i32* @ga, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store3(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store3:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    subf r6, r4, r3
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r6
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ugt i32 %a, %b
+  %not.cmp1.i = icmp ne i32 %a, %b
+  %..i = sext i1 %not.cmp1.i to i32
+  %retval.0.i = select i1 %cmp.i, i32 1, i32 %..i
+  store i32 %retval.0.i, i32* @ga, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store4(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store4:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    subf r6, r4, r3
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r6
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ugt i32 %a, %b
+  %cmp1.i = icmp ult i32 %a, %b
+  %..i = sext i1 %cmp1.i to i32
+  %retval.0.i = select i1 %cmp.i, i32 1, i32 %..i
+  store i32 %retval.0.i, i32* @ga, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store5(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store5:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    subf r6, r4, r3
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r6
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ult i32 %a, %b
+  %not.cmp1.i = icmp ne i32 %a, %b
+  %..i = zext i1 %not.cmp1.i to i32
+  %retval.0.i = select i1 %cmp.i, i32 -1, i32 %..i
+  store i32 %retval.0.i, i32* @ga, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+; FIXME: this is still done with compares, we may fix that in the future
+define void @store6(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store6:
+entry:
+  %cmp.i = icmp ult i32 %a, %b
+  %cmp1.i = icmp ugt i32 %a, %b
+  %..i = zext i1 %cmp1.i to i32
+  %retval.0.i = select i1 %cmp.i, i32 -1, i32 %..i
+  store i32 %retval.0.i, i32* @ga, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store7(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store7:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    subf r6, r4, r3
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r6
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp eq i32 %a, %b
+  %cmp1.i = icmp ult i32 %a, %b
+  %cond.i = select i1 %cmp1.i, i32 -1, i32 1
+  %cond2.i = select i1 %cmp.i, i32 0, i32 %cond.i
+  store i32 %cond2.i, i32* @ga, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store8(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store8:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    subf r6, r4, r3
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r6
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp eq i32 %a, %b
+  %cmp1.i = icmp ugt i32 %a, %b
+  %cond.i = select i1 %cmp1.i, i32 1, i32 -1
+  %cond2.i = select i1 %cmp.i, i32 0, i32 %cond.i
+  store i32 %cond2.i, i32* @ga, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store9(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store9:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    subf r6, r4, r3
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r6
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ult i32 %a, %b
+  %not.cmp1.i = icmp ne i32 %a, %b
+  %cond.i = zext i1 %not.cmp1.i to i32
+  %cond2.i = select i1 %cmp.i, i32 -1, i32 %cond.i
+  store i32 %cond2.i, i32* @ga, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+; FIXME: this is still done with compares, we may fix that in the future
+define void @store10(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store10:
+entry:
+  %cmp.i = icmp ult i32 %a, %b
+  %cmp1.i = icmp ugt i32 %a, %b
+  %cond.i = zext i1 %cmp1.i to i32
+  %cond2.i = select i1 %cmp.i, i32 -1, i32 %cond.i
+  store i32 %cond2.i, i32* @ga, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store11(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store11:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    subf r6, r4, r3
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r6
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ugt i32 %a, %b
+  %not.cmp1.i = icmp ne i32 %a, %b
+  %cond.i = sext i1 %not.cmp1.i to i32
+  %cond2.i = select i1 %cmp.i, i32 1, i32 %cond.i
+  store i32 %cond2.i, i32* @ga, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store12(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: store12:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    subf r6, r4, r3
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r6
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ugt i32 %a, %b
+  %cmp1.i = icmp ult i32 %a, %b
+  %cond.i = sext i1 %cmp1.i to i32
+  %cond2.i = select i1 %cmp.i, i32 1, i32 %cond.i
+  store i32 %cond2.i, i32* @ga, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/comparisonOps64.ll
===================================================================
--- test/CodeGen/PowerPC/comparisonOps64.ll
+++ test/CodeGen/PowerPC/comparisonOps64.ll
@@ -0,0 +1,437 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@ga = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @compOp1(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp1:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %cmp1 = icmp ult i64 %a, %b
+  %. = select i1 %cmp1, i64 -1, i64 1
+  %retval.0 = select i1 %cmp, i64 0, i64 %.
+  ret i64 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @compOp2(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp2:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %cmp1 = icmp ugt i64 %a, %b
+  %. = select i1 %cmp1, i64 1, i64 -1
+  %retval.0 = select i1 %cmp, i64 0, i64 %.
+  ret i64 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @compOp3(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp3:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %not.cmp1 = icmp ne i64 %a, %b
+  %. = sext i1 %not.cmp1 to i64
+  %retval.0 = select i1 %cmp, i64 1, i64 %.
+  ret i64 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @compOp4(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp4:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %cmp1 = icmp ult i64 %a, %b
+  %. = sext i1 %cmp1 to i64
+  %retval.0 = select i1 %cmp, i64 1, i64 %.
+  ret i64 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @compOp5(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp5:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %not.cmp1 = icmp ne i64 %a, %b
+  %. = zext i1 %not.cmp1 to i64
+  %retval.0 = select i1 %cmp, i64 -1, i64 %.
+  ret i64 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+; FIXME: this is still done with compares, we may fix that in the future
+define i64 @compOp6(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp6:
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %cmp1 = icmp ugt i64 %a, %b
+  %. = zext i1 %cmp1 to i64
+  %retval.0 = select i1 %cmp, i64 -1, i64 %.
+  ret i64 %retval.0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @compOp7(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp7:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %cmp1 = icmp ult i64 %a, %b
+  %phitmp = select i1 %cmp1, i64 -1, i64 1
+  %cond2 = select i1 %cmp, i64 0, i64 %phitmp
+  ret i64 %cond2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @compOp8(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp8:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %cmp1 = icmp ugt i64 %a, %b
+  %phitmp = select i1 %cmp1, i64 1, i64 -1
+  %cond2 = select i1 %cmp, i64 0, i64 %phitmp
+  ret i64 %cond2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @compOp9(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp9:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %not.cmp1 = icmp ne i64 %a, %b
+  %phitmp = zext i1 %not.cmp1 to i64
+  %cond2 = select i1 %cmp, i64 -1, i64 %phitmp
+  ret i64 %cond2
+}
+
+; Function Attrs: norecurse nounwind readnone
+; FIXME: this is still done with compares, we may fix that in the future
+define i64 @compOp10(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp10:
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %cmp1 = icmp ugt i64 %a, %b
+  %phitmp = zext i1 %cmp1 to i64
+  %cond2 = select i1 %cmp, i64 -1, i64 %phitmp
+  ret i64 %cond2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @compOp11(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp11:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %not.cmp1 = icmp ne i64 %a, %b
+  %phitmp = sext i1 %not.cmp1 to i64
+  %cond2 = select i1 %cmp, i64 1, i64 %phitmp
+  ret i64 %cond2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @compOp12(i64 %a, i64 %b) {
+; CHECK-LABEL: compOp12:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r5, r3, r4
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    subfe r12, r4, r3
+; CHECK-NEXT:    subfe r3, r12, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %cmp1 = icmp ult i64 %a, %b
+  %phitmp = sext i1 %cmp1 to i64
+  %cond2 = select i1 %cmp, i64 1, i64 %phitmp
+  ret i64 %cond2
+}
+
+; Function Attrs: norecurse nounwind
+define void @store1(i64 %a, i64 %b) {
+; CHECK-LABEL: store1:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sub r6, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r6
+; CHECK-NEXT:    std r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp eq i64 %a, %b
+  %cmp1.i = icmp ult i64 %a, %b
+  %..i = select i1 %cmp1.i, i64 -1, i64 1
+  %retval.0.i = select i1 %cmp.i, i64 0, i64 %..i
+  store i64 %retval.0.i, i64* @ga, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store2(i64 %a, i64 %b) {
+; CHECK-LABEL: store2:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sub r6, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r6
+; CHECK-NEXT:    std r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp eq i64 %a, %b
+  %cmp1.i = icmp ugt i64 %a, %b
+  %..i = select i1 %cmp1.i, i64 1, i64 -1
+  %retval.0.i = select i1 %cmp.i, i64 0, i64 %..i
+  store i64 %retval.0.i, i64* @ga, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store3(i64 %a, i64 %b) {
+; CHECK-LABEL: store3:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sub r6, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r6
+; CHECK-NEXT:    std r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ugt i64 %a, %b
+  %not.cmp1.i = icmp ne i64 %a, %b
+  %..i = sext i1 %not.cmp1.i to i64
+  %retval.0.i = select i1 %cmp.i, i64 1, i64 %..i
+  store i64 %retval.0.i, i64* @ga, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store4(i64 %a, i64 %b) {
+; CHECK-LABEL: store4:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sub r6, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r6
+; CHECK-NEXT:    std r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ugt i64 %a, %b
+  %cmp1.i = icmp ult i64 %a, %b
+  %..i = sext i1 %cmp1.i to i64
+  %retval.0.i = select i1 %cmp.i, i64 1, i64 %..i
+  store i64 %retval.0.i, i64* @ga, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store5(i64 %a, i64 %b) {
+; CHECK-LABEL: store5:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sub r6, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r6
+; CHECK-NEXT:    std r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ult i64 %a, %b
+  %not.cmp1.i = icmp ne i64 %a, %b
+  %..i = zext i1 %not.cmp1.i to i64
+  %retval.0.i = select i1 %cmp.i, i64 -1, i64 %..i
+  store i64 %retval.0.i, i64* @ga, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+; FIXME: this is still done with compares, we may fix that in the future
+define void @store6(i64 %a, i64 %b) {
+; CHECK-LABEL: store6:
+entry:
+  %cmp.i = icmp ult i64 %a, %b
+  %cmp1.i = icmp ugt i64 %a, %b
+  %..i = zext i1 %cmp1.i to i64
+  %retval.0.i = select i1 %cmp.i, i64 -1, i64 %..i
+  store i64 %retval.0.i, i64* @ga, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store7(i64 %a, i64 %b) {
+; CHECK-LABEL: store7:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sub r6, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r6
+; CHECK-NEXT:    std r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp eq i64 %a, %b
+  %cmp1.i = icmp ult i64 %a, %b
+  %phitmp.i = select i1 %cmp1.i, i64 -1, i64 1
+  %cond2.i = select i1 %cmp.i, i64 0, i64 %phitmp.i
+  store i64 %cond2.i, i64* @ga, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store8(i64 %a, i64 %b) {
+; CHECK-LABEL: store8:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sub r6, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r6
+; CHECK-NEXT:    std r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp eq i64 %a, %b
+  %cmp1.i = icmp ugt i64 %a, %b
+  %phitmp.i = select i1 %cmp1.i, i64 1, i64 -1
+  %cond2.i = select i1 %cmp.i, i64 0, i64 %phitmp.i
+  store i64 %cond2.i, i64* @ga, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store9(i64 %a, i64 %b) {
+; CHECK-LABEL: store9:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sub r6, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r6
+; CHECK-NEXT:    std r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ult i64 %a, %b
+  %not.cmp1.i = icmp ne i64 %a, %b
+  %phitmp.i = zext i1 %not.cmp1.i to i64
+  %cond2.i = select i1 %cmp.i, i64 -1, i64 %phitmp.i
+  store i64 %cond2.i, i64* @ga, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+; FIXME: this is still done with compares, we may fix that in the future
+define void @store10(i64 %a, i64 %b) {
+; CHECK-LABEL: store10:
+entry:
+  %cmp.i = icmp ult i64 %a, %b
+  %cmp1.i = icmp ugt i64 %a, %b
+  %phitmp.i = zext i1 %cmp1.i to i64
+  %cond2.i = select i1 %cmp.i, i64 -1, i64 %phitmp.i
+  store i64 %cond2.i, i64* @ga, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store11(i64 %a, i64 %b) {
+; CHECK-LABEL: store11:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sub r6, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r6
+; CHECK-NEXT:    std r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ugt i64 %a, %b
+  %not.cmp1.i = icmp ne i64 %a, %b
+  %phitmp.i = sext i1 %not.cmp1.i to i64
+  %cond2.i = select i1 %cmp.i, i64 1, i64 %phitmp.i
+  store i64 %cond2.i, i64* @ga, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @store12(i64 %a, i64 %b) {
+; CHECK-LABEL: store12:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r6, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sub r6, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r6
+; CHECK-NEXT:    std r3, 0(r5)
+; CHECK-NEXT:    blr
+entry:
+  %cmp.i = icmp ugt i64 %a, %b
+  %cmp1.i = icmp ult i64 %a, %b
+  %phitmp.i = sext i1 %cmp1.i to i64
+  %cond2.i = select i1 %cmp.i, i64 1, i64 %phitmp.i
+  store i64 %cond2.i, i64* @ga, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/eliminate_ext.ll
===================================================================
--- test/CodeGen/PowerPC/eliminate_ext.ll
+++ test/CodeGen/PowerPC/eliminate_ext.ll
@@ -0,0 +1,206 @@
+; RUN: llc -verify-machineinstrs -O1 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -O1 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+
+define signext i32 @sext_test(i32 signext %a) {
+; We can eliminate extsw before and after the call for int_func.
+; CHECK-LABEL: sext_test:
+; CHECK-NOT: extsw
+; CHECK: bl int_func
+; CHECK-NOT: extsw
+entry:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  br i1 %tobool, label %return, label %if.then
+
+if.then:
+  %call = tail call signext i32 @int_func(i32 signext %a)
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %call, %if.then ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define signext i32 @sext_test2(i32 signext %a) {
+; We can eliminate extsw before the call for long_func.
+; We should not eliminate extsw after the call.
+; CHECK-LABEL: sext_test2:
+; CHECK-NOT: extsw
+; CHECK: bl long_func
+; CHECK: extsw
+entry:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  br i1 %tobool, label %return, label %if.then
+
+if.then:
+  %conv = sext i32 %a to i64
+  %call = tail call i64 @long_func(i64 %conv)
+  %conv1 = trunc i64 %call to i32
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %conv1, %if.then ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define zeroext i32 @zext_test(i32 zeroext %a) {
+; We can eliminate zero-extension before and after the call for uint_func.
+; CHECK-LABEL: zext_test:
+; CHECK-NOT: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+; CHECK: bl uint_func
+; CHECK-NOT: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+entry:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  br i1 %tobool, label %return, label %if.then
+
+if.then:
+  %call = tail call zeroext i32 @uint_func(i32 zeroext %a)
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %call, %if.then ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define zeroext i32 @zext_test2(i32 zeroext %a) {
+; We can eliminate zero-extension before the call for ulong_func.
+; CHECK-LABEL: zext_test2:
+; CHECK-NOT: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+; CHECK: bl ulong_func
+; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+entry:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  br i1 %tobool, label %return, label %if.then
+
+if.then:
+  %conv = zext i32 %a to i64
+  %call = tail call i64 @ulong_func(i64 %conv)
+  %conv1 = trunc i64 %call to i32
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %conv1, %if.then ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define signext i32 @sext_test3(i32 signext %a, i32 signext %b) {
+; We can eliminate extsw for output of li and rlwinm.
+; CHECK-LABEL: sext_test3:
+;	CHECK-DAG: li {{[0-9]+}}, 255
+;	CHECK-DAG: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 1, 15
+; CHECK-NOT: extsw
+; CHECK: bl int_func
+; CHECK-NOT: extsw
+entry:
+  %and2 = and i32 %a, 2
+  %tobool3 = icmp eq i32 %and2, 0
+  br i1 %tobool3, label %return, label %if.then4
+
+if.then4:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  %and1 = and i32 %b, 2147418112
+  %b.addr.0 = select i1 %tobool, i32 %and1, i32 255
+  %call = tail call signext i32 @int_func(i32 signext %b.addr.0)
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %call, %if.then4 ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define signext i32 @sext_test4(i32 signext %a, i32 signext %b) {
+; We can eliminate extsw for output of li and srawi.
+; CHECK-LABEL: sext_test4:
+;	CHECK-DAG: lis {{[0-9]+}}, 4660
+;	CHECK-DAG: srawi {{[0-9]+}}, {{[0-9]+}}, 3
+; CHECK-NOT: extsw
+; CHECK: bl int_func
+; CHECK-NOT: extsw
+entry:
+  %and1 = and i32 %a, 2
+  %tobool2 = icmp eq i32 %and1, 0
+  br i1 %tobool2, label %return, label %if.then3
+
+if.then3:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  %shr = ashr i32 %b, 3
+  %b.addr.0 = select i1 %tobool, i32 305397760, i32 %shr
+  %call = tail call signext i32 @int_func(i32 signext %b.addr.0)
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %call, %if.then3 ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define zeroext i32 @zext_test3(i32 zeroext %a, i32 zeroext %b) {
+; We can eliminate zero-extension for output of li and slwi.
+; CHECK-LABEL: zext_test3:
+;	CHECK-DAG: li {{[0-9]+}}, 255
+;	CHECK-DAG: slwi {{[0-9]+}}, {{[0-9]+}}, 3
+; CHECK-NOT: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+; CHECK: bl uint_func
+; CHECK-NOT: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+entry:
+  %and1 = and i32 %a, 2
+  %tobool2 = icmp eq i32 %and1, 0
+  br i1 %tobool2, label %return, label %if.then3
+
+if.then3:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  %shl = shl i32 %b, 3
+  %b.addr.0 = select i1 %tobool, i32 %shl, i32 255
+  %call = tail call zeroext i32 @uint_func(i32 zeroext %b.addr.0)
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %call, %if.then3 ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define zeroext i32 @zext_test4(i32 zeroext %a, i32 zeroext %b, i32* nocapture readonly %p) {
+; We can eliminate zero-extension for output of lwz and andi.
+; CHECK-LABEL: zext_test4:
+;	CHECK-DAG: 	lwz {{[0-9]+}}, 0(5)
+;	CHECK-DAG: 	andi. {{[0-9]+}}, {{[0-9]+}}, 4660
+; CHECK-NOT: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+; CHECK: bl uint_func
+; CHECK-NOT: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+entry:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  br i1 %tobool, label %if.else, label %if.then
+
+if.then:
+  %0 = load i32, i32* %p
+  br label %if.end
+
+if.else:
+  %and1 = and i32 %b, 4660
+  br label %if.end
+
+if.end:
+  %b.addr.0 = phi i32 [ %0, %if.then ], [ %and1, %if.else ]
+  %and2 = and i32 %a, 2
+  %tobool3 = icmp eq i32 %and2, 0
+  br i1 %tobool3, label %return, label %if.then4
+
+if.then4:
+  %call = tail call zeroext i32 @uint_func(i32 zeroext %b.addr.0)
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %call, %if.then4 ], [ 0, %if.end ]
+  ret i32 %retval.0
+}
+
+declare signext i32 @int_func(i32 signext)
+declare zeroext i32 @uint_func(i32 zeroext)
+declare i64 @long_func(i64)
+declare i64 @ulong_func(i64)
Index: test/CodeGen/PowerPC/setcc-logic.ll
===================================================================
--- test/CodeGen/PowerPC/setcc-logic.ll
+++ test/CodeGen/PowerPC/setcc-logic.ll
@@ -422,9 +422,9 @@
 define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
 ; CHECK-LABEL: ne_neg1_and_ne_zero:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    li 4, 1
 ; CHECK-NEXT:    addi 3, 3, 1
-; CHECK-NEXT:    subfc 3, 3, 4
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    subfic 3, 3, 1
 ; CHECK-NEXT:    subfe 3, 4, 4
 ; CHECK-NEXT:    neg 3, 3
 ; CHECK-NEXT:    blr
Index: test/CodeGen/PowerPC/testComparesi32geu.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesi32geu.ll
+++ test/CodeGen/PowerPC/testComparesi32geu.ll
@@ -0,0 +1,46 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i8 @fn1(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: fn1:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    li r4, 2
+; CHECK-NEXT:    clrlwi r3, r3, 24
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %a.off = add i8 %a, -1
+  %switch = icmp ult i8 %a.off, 2
+  %. = select i1 %switch, i8 0, i8 2
+  ret i8 %.
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i8 @fn2(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: fn2:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    li r4, 3
+; CHECK-NEXT:    clrlwi r3, r3, 24
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %a.off = add i8 %a, -1
+  %switch = icmp ule i8 %a.off, 2
+  %. = select i1 %switch, i8 0, i8 2
+  ret i8 %.
+}
Index: test/CodeGen/PowerPC/testComparesi32gtu.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesi32gtu.ll
+++ test/CodeGen/PowerPC/testComparesi32gtu.ll
@@ -0,0 +1,52 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+%struct.tree_common = type { i8, [3 x i8] }
+declare signext i32 @fn2(...) local_unnamed_addr #1
+
+; Function Attrs: nounwind
+define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
+; CHECK-LABEL: testCompare1:
+; CHECK:       # BB#0: # %entry
+; CHECK:         lbz r3, 0(r3)
+; CHECK-DAG:     clrlwi r3, r3, 31
+; CHECK-DAG:     clrldi r3, r3, 32
+; CHECK:         lbz  r4, 0(r4)
+; CHECK-DAG:     clrlwi r4, r4, 31
+; CHECK-DAG:     clrldi r4, r4, 32
+; CHECK:         subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+entry:
+  %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
+  %bf.clear = and i8 %bf.load, 1
+  %0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0
+  %bf.load1 = load i8, i8* %0, align 4
+  %bf.clear2 = and i8 %bf.load1, 1
+  %cmp = icmp ugt i8 %bf.clear, %bf.clear2
+  %conv = zext i1 %cmp to i32
+  %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
+  ret i32 undef
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: testCompare2:
+; CHECK:       # BB#0: # %entry
+; CHECK-DAG:     rlwinm r3, r3, 0, 31, 31
+; CHECK-DAG:     rlwinm r4, r4, 0, 31, 31
+; CHECK-DAG:     clrldi r3, r3, 32
+; CHECK-DAG:     clrldi r4, r4, 32
+; CHECK:         subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %and = and i32 %a, 1
+  %and1 = and i32 %b, 1
+  %cmp = icmp ugt i32 %and, %and1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
Index: test/CodeGen/PowerPC/testComparesi32leu.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesi32leu.ll
+++ test/CodeGen/PowerPC/testComparesi32leu.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rlwinm r3, r3, 0, 31, 31
+; CHECK-NEXT:    rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    clrldi r4, r4, 32
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = and i8 %a, 1
+  %1 = and i8 %b, 1
+  %cmp = icmp ule i8 %0, %1
+  %conv3 = zext i1 %cmp to i32
+  ret i32 %conv3
+}
Index: test/CodeGen/PowerPC/testComparesi32ltu.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesi32ltu.ll
+++ test/CodeGen/PowerPC/testComparesi32ltu.ll
@@ -0,0 +1,52 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+%struct.tree_common = type { i8, [3 x i8] }
+declare signext i32 @fn2(...) local_unnamed_addr #1
+
+; Function Attrs: nounwind
+define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
+; CHECK-LABEL: testCompare1:
+; CHECK:       # BB#0: # %entry
+; CHECK:         lbz r3, 0(r3)
+; CHECK-DAG:     clrlwi r3, r3, 31
+; CHECK-DAG:     clrldi r3, r3, 32
+; CHECK:         lbz  r4, 0(r4)
+; CHECK-DAG:     clrlwi r4, r4, 31
+; CHECK-DAG:     clrldi r4, r4, 32
+; CHECK:         subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+entry:
+  %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
+  %bf.clear = and i8 %bf.load, 1
+  %0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0
+  %bf.load1 = load i8, i8* %0, align 4
+  %bf.clear2 = and i8 %bf.load1, 1
+  %cmp = icmp ult i8 %bf.clear, %bf.clear2
+  %conv = zext i1 %cmp to i32
+  %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
+  ret i32 undef
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: testCompare2:
+; CHECK:       # BB#0: # %entry
+; CHECK-DAG:     rlwinm r3, r3, 0, 31, 31
+; CHECK-DAG:     rlwinm r4, r4, 0, 31, 31
+; CHECK-DAG:     clrldi r3, r3, 32
+; CHECK-DAG:     clrldi r4, r4, 32
+; CHECK:         subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %and = and i32 %a, 1
+  %and1 = and i32 %b, 1
+  %cmp = icmp ult i32 %and, %and1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
Index: test/CodeGen/PowerPC/testComparesieqsc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesieqsc.ll
+++ test/CodeGen/PowerPC/testComparesieqsc.ll
@@ -0,0 +1,126 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesieqsc.c'
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ieqsc:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ieqsc_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsc_z(i8 signext %a) {
+; CHECK-LABEL: test_ieqsc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_ieqsc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ieqsc_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ieqsc_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_ieqsc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_ieqsc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesieqsi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesieqsi.ll
+++ test/CodeGen/PowerPC/testComparesieqsi.ll
@@ -0,0 +1,126 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesieqsi.c'
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ieqsi:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ieqsi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsi_z(i32 signext %a) {
+; CHECK-LABEL: test_ieqsi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_ieqsi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ieqsi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ieqsi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_ieqsi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_ieqsi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesieqsll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesieqsll.ll
+++ test/CodeGen/PowerPC/testComparesieqsll.ll
@@ -0,0 +1,134 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesieqsll.c'
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll_z(i64 %a) {
+; CHECK-LABEL: test_ieqsll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll_sext_z(i64 %a) {
+; CHECK-LABEL: test_ieqsll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_z_store(i64 %a) {
+; CHECK-LABEL: test_ieqsll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_ieqsll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesieqss.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesieqss.ll
+++ test/CodeGen/PowerPC/testComparesieqss.ll
@@ -0,0 +1,126 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesieqss.c'
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_ieqss:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_ieqss_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqss_z(i16 signext %a) {
+; CHECK-LABEL: test_ieqss_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_ieqss_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_ieqss_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_ieqss_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqss_z_store(i16 signext %a) {
+; CHECK-LABEL: test_ieqss_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_ieqss_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiequc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiequc.ll
+++ test/CodeGen/PowerPC/testComparesiequc.ll
@@ -0,0 +1,142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesiequc.c'
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iequc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iequc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_iequc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_iequc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iequc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iequc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_iequc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_iequc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiequi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiequi.ll
+++ test/CodeGen/PowerPC/testComparesiequi.ll
@@ -0,0 +1,126 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesiequi.c'
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iequi:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iequi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequi_z(i32 zeroext %a) {
+; CHECK-LABEL: test_iequi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequi_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_iequi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iequi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iequi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequi_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_iequi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequi_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_iequi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiequll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiequll.ll
+++ test/CodeGen/PowerPC/testComparesiequll.ll
@@ -0,0 +1,134 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesiequll.c'
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll_z(i64 %a) {
+; CHECK-LABEL: test_iequll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll_sext_z(i64 %a) {
+; CHECK-LABEL: test_iequll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_z_store(i64 %a) {
+; CHECK-LABEL: test_iequll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_iequll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiequs.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiequs.ll
+++ test/CodeGen/PowerPC/testComparesiequs.ll
@@ -0,0 +1,142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesiequs.c'
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iequs:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iequs_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequs_z(i16 zeroext %a) {
+; CHECK-LABEL: test_iequs_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequs_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_iequs_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iequs_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iequs_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequs_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_iequs_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequs_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_iequs_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesigesc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigesc.ll
+++ test/CodeGen/PowerPC/testComparesigesc.ll
@@ -0,0 +1,124 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igesc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igesc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_igesc_z(i8 signext %a) {
+; CHECK-LABEL: test_igesc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_igesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_igesc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_igesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igesc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igesc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_igesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igesc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rlwinm r3, r3, 25, 31, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_igesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igesc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 7
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesigesi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigesi.ll
+++ test/CodeGen/PowerPC/testComparesigesi.ll
@@ -0,0 +1,124 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igesi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igesi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_igesi_z(i32 signext %a) {
+; CHECK-LABEL: test_igesi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_igesi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_igesi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_igesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igesi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igesi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_igesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igesi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_igesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igesi_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesigesll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigesll.ll
+++ test/CodeGen/PowerPC/testComparesigesll.ll
@@ -0,0 +1,128 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define signext i32 @test_igesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_igesll_z(i64 %a) {
+; CHECK-LABEL: test_igesll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_igesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_igesll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_igesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r3, 63
+; CHECK:    subfc r3, r4, r3
+; CHECK:    rldicl r3, r4, 1, 63
+; CHECK:    adde r3, r6, r3
+; CHECK:    std r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_igesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    adde r3, r6, r3
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_igesll_z_store(i64 %a) {
+; CHECK-LABEL: test_igesll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_igesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_igesll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    std r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesigess.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigess.ll
+++ test/CodeGen/PowerPC/testComparesigess.ll
@@ -0,0 +1,124 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igess:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igess_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_igess_z(i16 signext %a) {
+; CHECK-LABEL: test_igess_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_igess_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_igess_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_igess_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igess_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igess_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_igess_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igess_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rlwinm r3, r3, 17, 31, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_igess_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igess_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 15
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesigeuc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigeuc.ll
+++ test/CodeGen/PowerPC/testComparesigeuc.ll
@@ -0,0 +1,112 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: test_igeuc:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeuc_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr  
+  
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeuc_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: @test_igeuc_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr  
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeuc_sext_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv2 = sext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: @test_igeuc_sext_z
+; CHECK: li r3, -1
+; CHECK-NEXT: blr  
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK_LABEL: test_igeuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-TBD-LABEL: @test_igeuc_sext_store
+; CHECK-TBD: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-TBD: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-TBD: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-TBD: stb  [[REG3]]
+; CHECK-TBD: blr    
+}
+
+; Function Attrs : norecurse nounwind
+define void @test_igeuc_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: @test_igeuc_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: stb [[REG1]]
+; CHECK: blr    
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeuc_sext_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: @test_igeuc_sext_z_store
+; CHECK: li [[REG1:r[0-9]+]], 255
+; CHECK: stb [[REG1]]
+; CHECK: blr
+}
Index: test/CodeGen/PowerPC/testComparesigeui.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigeui.ll
+++ test/CodeGen/PowerPC/testComparesigeui.ll
@@ -0,0 +1,112 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+; CHECK-LABEL: test_igeui:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeui_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr    
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeui_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %sub = zext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeui_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeui_sext_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeui_sext_z
+; CHECK: li r3, -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob
+  ret void
+; CHECK_LABEL: test_igeuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_igeui_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stw  [[REG3]]
+; CHECK: blr    
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeui_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  store i32 %conv1, i32* @glob
+  ret void
+; CHECK-LABEL: @test_igeui_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: stw [[REG1]]
+; CHECK: blr  
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeui_sext_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0 
+  %conv1 = sext i1 %cmp to i32
+  store i32 %conv1, i32* @glob
+  ret void
+; CHECK-LABEL: @test_igeui_sext_z_store
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: stw [[REG1]]
+; CHECK: blr  
+}
+
Index: test/CodeGen/PowerPC/testComparesigeull.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigeull.ll
+++ test/CodeGen/PowerPC/testComparesigeull.ll
@@ -0,0 +1,111 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeull(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+; CHECK-LABEL: test_igeull:
+; CHECK: subfc {{r[0-9]+}}, r4, r3
+; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4
+; CHECK-NEXT: addi r3, [[REG1]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeull_sext(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeull_sext
+; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
+; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
+; CHECK: not r3, [[REG2]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeull_z(i64 %a) {
+entry:
+  %cmp = icmp uge i64 %a, 0
+  %sub = zext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeull_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeull_sext_z(i64 %a) {
+entry:
+  %cmp = icmp uge i64 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeull_sext_z
+; CHECK: li r3, -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeull_store(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: test_igeull_store:
+; CHECK: subfc {{r[0-9]+}}, r4, r3
+; CHECK: subfe [[REG1:r[0-9]+]], r4, r4
+; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeull_sext_store(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: @test_igeull_sext_store
+; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
+; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
+; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
+; CHECK: std [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeull_z_store(i64 %a) {
+entry:
+  %cmp = icmp uge i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: @test_igeull_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: std [[REG1]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeull_sext_z_store(i64 %a) {
+entry:
+  %cmp = icmp uge i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: @test_igeull_sext_z_store
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: std [[REG1]]
+; CHECK: blr
+}
Index: test/CodeGen/PowerPC/testComparesigeus.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigeus.ll
+++ test/CodeGen/PowerPC/testComparesigeus.ll
@@ -0,0 +1,113 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: test_igeus:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeus_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeus_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: @test_igeus_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeus_sext_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: @test_igeus_sext_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK_LABEL: test_igeus_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_igeus_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: sth  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeus_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_igeus_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: sth [[REG1]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeus_sext_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_igeus_sext_z_store
+; CHECK: lis [[REG1:r[0-9]+]], 0
+; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535
+; CHECK: sth [[REG2]]
+; CHECK: blr
+}
+
Index: test/CodeGen/PowerPC/testComparesigtsc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigtsc.ll
+++ test/CodeGen/PowerPC/testComparesigtsc.ll
@@ -0,0 +1,116 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_z(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_sext_z:
+; CHECK: neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG2]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_sext_z_store:
+; CHECK:       neg [[REG2:r[0-9]+]], r3
+; CHECK:       sradi {{r[0-9]+}}, [[REG2]], 63
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesigtsi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigtsi.ll
+++ test/CodeGen/PowerPC/testComparesigtsi.ll
@@ -0,0 +1,116 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_z(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_sext_z:
+; CHECK:  neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG2]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_sext_z_store:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesigtsll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigtsll.ll
+++ test/CodeGen/PowerPC/testComparesigtsll.ll
@@ -0,0 +1,134 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igtsll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
+; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK-NEXT:    xori r3, [[REG4]], 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igtsll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
+; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK-NEXT:    xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK-NEXT:    neg r3, [[REG5]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsll_z(i64 %a) {
+; CHECK-LABEL: test_igtsll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    nor r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsll_sext_z(i64 %a) {
+; CHECK-LABEL: test_igtsll_sext_z:
+; CHECK:    addi [[REG1:r[0-9]+]], r3, -1
+; CHECK-NEXT:    nor [[REG2:r[0-9]+]], [[REG1]], r3
+; CHECK-NEXT:    sradi r3, [[REG2]], 63
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igtsll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
+; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
+; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK-NOT:     neg
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igtsll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
+; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
+; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK:         neg {{r[0-9]+}}, [[REG5]]
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtsll_z_store(i64 %a) {
+; CHECK-LABEL: test_igtsll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r5, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_igtsll_sext_z_store:
+; CHECK:    addi [[REG1:r[0-9]+]], r3, -1
+; CHECK:    nor [[REG2:r[0-9]+]], [[REG1]], r3
+; CHECK:    sradi [[REG3:r[0-9]+]], [[REG2]], 63
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesigtss.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigtss.ll
+++ test/CodeGen/PowerPC/testComparesigtss.ll
@@ -0,0 +1,117 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_z(i16 signext %a) {
+; CHECK-LABEL: test_igtss_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_igtss_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK:    neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT:    sradi r3, [[REG2]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtss_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igtss_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igtss_sext_z_store:
+; CHECK:       neg [[REG2:r[0-9]+]], r3
+; CHECK:       sradi {{r[0-9]+}}, [[REG2]], 63
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesigtuc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigtuc.ll
+++ test/CodeGen/PowerPC/testComparesigtuc.ll
@@ -0,0 +1,114 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc:
+; CHECK:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc_store:
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesigtui.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigtui.ll
+++ test/CodeGen/PowerPC/testComparesigtui.ll
@@ -0,0 +1,115 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui:
+; CHECK:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui_store:
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
Index: test/CodeGen/PowerPC/testComparesigtull.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigtull.ll
+++ test/CodeGen/PowerPC/testComparesigtull.ll
@@ -0,0 +1,126 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igtull:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NEXT:    neg r3, [[REG2]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igtull_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    subfe r3, [[REG2:r[0-9]+]], [[REG2]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtull_z(i64 %a) {
+; CHECK-LABEL: test_igtull_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtull_sext_z(i64 %a) {
+; CHECK-LABEL: test_igtull_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtull_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igtull_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK:         subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NEXT:    neg {{r[0-9]+}}, [[REG2]]
+; CHECK:         blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtull_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igtull_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK:         subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NOT:     neg
+; CHECK:         blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtull_z_store(i64 %a) {
+; CHECK-LABEL: test_igtull_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtull_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_igtull_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
Index: test/CodeGen/PowerPC/testComparesigtus.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesigtus.ll
+++ test/CodeGen/PowerPC/testComparesigtus.ll
@@ -0,0 +1,117 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus:
+; CHECK:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus_store:
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK:         blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK:         blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
Index: test/CodeGen/PowerPC/testComparesilesc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesilesc.ll
+++ test/CodeGen/PowerPC/testComparesilesc.ll
@@ -0,0 +1,128 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ilesc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ilesc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ilesc_z(i8 signext %a) {
+; CHECK-LABEL: test_ilesc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_ilesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_ilesc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ilesc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ilesc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ilesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_ilesc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ilesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_ilesc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesilesi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesilesi.ll
+++ test/CodeGen/PowerPC/testComparesilesi.ll
@@ -0,0 +1,128 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ilesi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ilesi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ilesi_z(i32 signext %a) {
+; CHECK-LABEL: test_ilesi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ilesi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_ilesi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ilesi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ilesi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ilesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_ilesi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ilesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_ilesi_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesilesll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesilesll.ll
+++ test/CodeGen/PowerPC/testComparesilesll.ll
@@ -0,0 +1,130 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define signext i32 @test_ilesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ilesll_z(i64 %a) {
+; CHECK-LABEL: test_ilesll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    or r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ilesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_ilesll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    or r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ilesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r4, 63
+; CHECK:    subfc r4, r3, r4
+; CHECK:    rldicl r3, r3, 1, 63
+; CHECK:    adde r3, r6, r3
+; CHECK:    std r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_ilesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r4, 63
+; CHECK-DAG:    rldicl r3, r3, 1, 63
+; CHECK-DAG:    subfc r4, r3, r4
+; CHECK:    adde r3, r6, r3
+; CHECK:    neg r3, r3
+; CHECK:    std r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_ilesll_z_store(i64 %a) {
+; CHECK-LABEL: test_ilesll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    or r3, r5, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_ilesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_ilesll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    or r3, r5, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiless.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiless.ll
+++ test/CodeGen/PowerPC/testComparesiless.ll
@@ -0,0 +1,128 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iless:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iless_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_iless_z(i16 signext %a) {
+; CHECK-LABEL: test_iless_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_iless_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_iless_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_iless_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iless_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iless_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iless_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iless_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iless_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iless_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesileuc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesileuc.ll
+++ test/CodeGen/PowerPC/testComparesileuc.ll
@@ -0,0 +1,119 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: test_ileuc:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileuc_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileuc_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+; CHECK-LABEL: test_ileuc_z:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi r3, [[REG1]], 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileuc_sext_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp ule i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileuc_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: test_ileuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: @test_ileuc_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stb  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileuc_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob
+  ret void
+; CHECK-LABEL: test_ileuc_z_store:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileuc_sext_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob
+  ret void
+; CHECK-LABEL: @test_ileuc_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: stb [[REG4]]
+; CHECK: blr
+}
+
Index: test/CodeGen/PowerPC/testComparesileui.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesileui.ll
+++ test/CodeGen/PowerPC/testComparesileui.ll
@@ -0,0 +1,119 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = zext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: test_ileui:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileui_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileui_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = zext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: test_ileui_z:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi r3, [[REG1]], 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileui_sext_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileui_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi r3, [[REG3]], 63
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = zext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: test_ileui_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_ileui_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stw  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileui_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = zext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: test_ileui_z_store:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileui_sext_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_ileui_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: stw [[REG4]]
+; CHECK: blr
+}
+
Index: test/CodeGen/PowerPC/testComparesileull.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesileull.ll
+++ test/CodeGen/PowerPC/testComparesileull.ll
@@ -0,0 +1,115 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileull(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+; CHECK-LABEL: test_ileull:
+; CHECK: subfc {{r[0-9]+}}, r3, r4
+; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3
+; CHECK-NEXT: addi r3, [[REG1]], 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileull_sext(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileull_sext
+; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
+; CHECK: not r3, [[REG2]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileull_z(i64 %a) {
+entry:
+  %cmp = icmp ule i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+; CHECK-LABEL: test_ileull_z
+; CHECK: cntlzd [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileull_sext_z(i64 %a) {
+entry:
+  %cmp = icmp ule i64 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileull_sext_z
+; CHECK: addic [[REG1:r[0-9]+]], r3, -1
+; CHECK: subfe r3, [[REG1]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileull_store(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: test_ileull_store:
+; CHECK: subfc {{r[0-9]+}}, r3, r4
+; CHECK: subfe [[REG1:r[0-9]+]], r3, r3
+; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileull_sext_store(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: @test_ileull_sext_store
+; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
+; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
+; CHECK: std [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileull_z_store(i64 %a) {
+entry:
+  %cmp = icmp ule i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: test_ileull_z_store:
+; CHECK: cntlzd [[REG1:r[0-9]+]], r3
+; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileull_sext_z_store(i64 %a) {
+entry:
+  %cmp = icmp ule i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: @test_ileull_sext_z_store
+; CHECK: addic [[REG1:r[0-9]+]], r3, -1
+; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
+; CHECK: std [[REG2]]
+; CHECK: blr
+}
+
Index: test/CodeGen/PowerPC/testComparesileus.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesileus.ll
+++ test/CodeGen/PowerPC/testComparesileus.ll
@@ -0,0 +1,119 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: test_ileus:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileus_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileus_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+; CHECK-LABEL: test_ileus_z:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi r3, [[REG1]], 5
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileus_sext_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileus_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: test_ileus_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_ileus_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: sth  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileus_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob
+  ret void
+; CHECK-LABEL: test_ileus_z_store:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileus_sext_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob
+  ret void
+; CHECK-LABEL: @test_ileus_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: sth [[REG4]]
+; CHECK: blr
+}
+
Index: test/CodeGen/PowerPC/testComparesiltsc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiltsc.ll
+++ test/CodeGen/PowerPC/testComparesiltsc.ll
@@ -0,0 +1,83 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_iltsc_sext_z:
+; CHECK:       srawi r3, r3, 31
+; CHECK-NEXT:  blr
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_iltsc_sext_z_store:
+; CHECK: srwi {{r[0-9]+}}, r3, 7
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiltsi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiltsi.ll
+++ test/CodeGen/PowerPC/testComparesiltsi.ll
@@ -0,0 +1,85 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_iltsi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_iltsi_sext_z_store:
+; CHECK:    srawi {{r[0-9]+}}, r3, 31
+; CHECK:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiltsll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiltsll.ll
+++ test/CodeGen/PowerPC/testComparesiltsll.ll
@@ -0,0 +1,99 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iltsll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
+; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK-NEXT:    xori r3, [[REG4]], 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iltsll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
+; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK-NEXT:    xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK-NEXT:    neg r3, [[REG5]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsll_sext_z(i64 %a) {
+; CHECK-LABEL: test_iltsll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iltsll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
+; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
+; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK-NOT:     neg {{r[0-9]+}}, [[REG5]]
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iltsll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
+; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
+; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK:         neg {{r[0-9]+}}, [[REG5]]
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_iltsll_sext_z_store:
+; CHECK:    sradi r3, r3, 63
+entry:
+  %cmp = icmp slt i64 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  store i64 %conv2, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiltss.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiltss.ll
+++ test/CodeGen/PowerPC/testComparesiltss.ll
@@ -0,0 +1,83 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_iltss_sext_z:
+; CHECK:       srawi r3, r3, 31
+; CHECK-NEXT:  blr
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iltss_sext_z_store:
+; CHECK:       srwi {{r[0-9]+}}, r3, 15
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %sub = sext i1 %cmp to i16
+  store i16 %sub, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiltuc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiltuc.ll
+++ test/CodeGen/PowerPC/testComparesiltuc.ll
@@ -0,0 +1,56 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc:
+; CHECK:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc_store:
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:    rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiltui.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiltui.ll
+++ test/CodeGen/PowerPC/testComparesiltui.ll
@@ -0,0 +1,56 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui:
+; CHECK:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui_store:
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiltull.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiltull.ll
+++ test/CodeGen/PowerPC/testComparesiltull.ll
@@ -0,0 +1,108 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iltull:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc [[REG:r[1-9]+]], r4, r3
+; CHECK-NEXT:    subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NEXT:    neg r3, [[REG2]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iltull_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    subfe r3, [[REG2:r[0-9]+]], [[REG2]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltull_z(i64 %a) {
+; CHECK-LABEL: test_iltull_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  ret i32 0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltull_sext_z(i64 %a) {
+; CHECK-LABEL: test_iltull_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  ret i32 0
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltull_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iltull_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subfc [[REG:r[0-9]+]], r4, r3
+; CHECK:         subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NEXT:    neg {{r[0-9]+}}, [[REG2]]
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltull_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iltull_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subfc [[REG:r[0-9]+]], r4, r3
+; CHECK:         subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NOT:     neg
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltull_z_store(i64 %a) {
+; CHECK-LABEL: test_iltull_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         li [[REG:r[0-9]+]], 0
+; CHECK:         std [[REG]], 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store i64 0, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltull_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_iltull_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         li [[REG:r[0-9]+]], 0
+; CHECK:         std [[REG]], 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store i64 0, i64* @glob, align 8
+  ret void
+}
+
Index: test/CodeGen/PowerPC/testComparesiltus.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiltus.ll
+++ test/CodeGen/PowerPC/testComparesiltus.ll
@@ -0,0 +1,56 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus:
+; CHECK:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus_store:
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesinesc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesinesc.ll
+++ test/CodeGen/PowerPC/testComparesinesc.ll
@@ -0,0 +1,121 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define signext i32 @test_inesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_inesc:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_inesc_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_inesc_z(i8 signext %a) {
+; CHECK-LABEL: test_inesc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_inesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_inesc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_inesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_inesc_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_inesc_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_inesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_inesc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_inesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_inesc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesinesi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesinesi.ll
+++ test/CodeGen/PowerPC/testComparesinesi.ll
@@ -0,0 +1,121 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define signext i32 @test_inesi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_inesi:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_inesi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_inesi_z(i32 signext %a) {
+; CHECK-LABEL: test_inesi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_inesi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_inesi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_inesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_inesi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_inesi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_inesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_inesi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_inesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_inesi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesinesll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesinesll.ll
+++ test/CodeGen/PowerPC/testComparesinesll.ll
@@ -0,0 +1,125 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define signext i32 @test_inesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_inesll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_inesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_inesll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_inesll_z(i64 %a) {
+; CHECK-LABEL: test_inesll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_inesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_inesll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_inesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_inesll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r5, r3, -1
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_inesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_inesll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_inesll_z_store(i64 %a) {
+; CHECK-LABEL: test_inesll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_inesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_inesll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesiness.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesiness.ll
+++ test/CodeGen/PowerPC/testComparesiness.ll
@@ -0,0 +1,121 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @test_iness(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iness:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iness_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_iness_z(i16 signext %a) {
+; CHECK-LABEL: test_iness_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_iness_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_iness_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_iness_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iness_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iness_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iness_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iness_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iness_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iness_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iness_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesineuc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesineuc.ll
+++ test/CodeGen/PowerPC/testComparesineuc.ll
@@ -0,0 +1,136 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ineuc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ineuc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ineuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_ineuc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_ineuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_ineuc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ineuc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ineuc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ineuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_ineuc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ineuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_ineuc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesineui.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesineui.ll
+++ test/CodeGen/PowerPC/testComparesineui.ll
@@ -0,0 +1,121 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ineui:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ineui_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ineui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_ineui_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ineui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_ineui_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ineui_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ineui_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ineui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_ineui_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ineui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_ineui_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesineull.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesineull.ll
+++ test/CodeGen/PowerPC/testComparesineull.ll
@@ -0,0 +1,125 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define signext i32 @test_ineull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ineull:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ineull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ineull_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ineull_z(i64 %a) {
+; CHECK-LABEL: test_ineull_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ineull_sext_z(i64 %a) {
+; CHECK-LABEL: test_ineull_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ineull_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ineull_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r5, r3, -1
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_ineull_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ineull_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_ineull_z_store(i64 %a) {
+; CHECK-LABEL: test_ineull_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_ineull_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_ineull_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesineus.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesineus.ll
+++ test/CodeGen/PowerPC/testComparesineus.ll
@@ -0,0 +1,137 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ineus:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ineus_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ineus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_ineus_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_ineus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_ineus_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ineus_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ineus_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_ineus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_ineus_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_ineus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_ineus_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testCompareslleqsc.ll
===================================================================
--- test/CodeGen/PowerPC/testCompareslleqsc.ll
+++ test/CodeGen/PowerPC/testCompareslleqsc.ll
@@ -0,0 +1,126 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c'
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lleqsc:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lleqsc_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsc_z(i8 signext %a) {
+; CHECK-LABEL: test_lleqsc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_lleqsc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lleqsc_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lleqsc_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_lleqsc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_lleqsc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testCompareslleqsi.ll
===================================================================
--- test/CodeGen/PowerPC/testCompareslleqsi.ll
+++ test/CodeGen/PowerPC/testCompareslleqsi.ll
@@ -0,0 +1,125 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lleqsi:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lleqsi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsi_z(i32 signext %a) {
+; CHECK-LABEL: test_lleqsi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_lleqsi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lleqsi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lleqsi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_lleqsi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECKNEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_lleqsi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testCompareslleqsll.ll
===================================================================
--- test/CodeGen/PowerPC/testCompareslleqsll.ll
+++ test/CodeGen/PowerPC/testCompareslleqsll.ll
@@ -0,0 +1,133 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll_z(i64 %a) {
+; CHECK-LABEL: test_lleqsll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll_sext_z(i64 %a) {
+; CHECK-LABEL: test_lleqsll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_z_store(i64 %a) {
+; CHECK-LABEL: test_lleqsll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_lleqsll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testCompareslleqss.ll
===================================================================
--- test/CodeGen/PowerPC/testCompareslleqss.ll
+++ test/CodeGen/PowerPC/testCompareslleqss.ll
@@ -0,0 +1,125 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_lleqss:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_lleqss_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqss_z(i16 signext %a) {
+; CHECK-LABEL: test_lleqss_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_lleqss_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_lleqss_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_lleqss_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqss_z_store(i16 signext %a) {
+; CHECK-LABEL: test_lleqss_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_lleqss_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllequc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllequc.ll
+++ test/CodeGen/PowerPC/testComparesllequc.ll
@@ -0,0 +1,141 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llequc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llequc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llequc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llequc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llequc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llequc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llequc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llequc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllequi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllequi.ll
+++ test/CodeGen/PowerPC/testComparesllequi.ll
@@ -0,0 +1,125 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llequi:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llequi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequi_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llequi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequi_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llequi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llequi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llequi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequi_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llequi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequi_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llequi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllequll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllequll.ll
+++ test/CodeGen/PowerPC/testComparesllequll.ll
@@ -0,0 +1,133 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll_z(i64 %a) {
+; CHECK-LABEL: test_llequll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll_sext_z(i64 %a) {
+; CHECK-LABEL: test_llequll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_z_store(i64 %a) {
+; CHECK-LABEL: test_llequll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llequll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllequs.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllequs.ll
+++ test/CodeGen/PowerPC/testComparesllequs.ll
@@ -0,0 +1,141 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llequs:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llequs_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequs_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llequs_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequs_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llequs_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llequs_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llequs_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequs_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llequs_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequs_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llequs_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllgesc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgesc.ll
+++ test/CodeGen/PowerPC/testComparesllgesc.ll
@@ -0,0 +1,124 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgesc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgesc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgesc_z(i8 signext %a) {
+; CHECK-LABEL: test_llgesc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_llgesc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgesc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgesc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llgesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llgesc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rlwinm r3, r3, 25, 31, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llgesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llgesc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 7
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllgesi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgesi.ll
+++ test/CodeGen/PowerPC/testComparesllgesi.ll
@@ -0,0 +1,124 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesi_z(i32 signext %a) {
+; CHECK-LABEL: test_llgesi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_llgesi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llgesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llgesi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llgesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llgesi_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllgesll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgesll.ll
+++ test/CodeGen/PowerPC/testComparesllgesll.ll
@@ -0,0 +1,128 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define i64 @test_llgesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesll_z(i64 %a) {
+; CHECK-LABEL: test_llgesll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_llgesll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llgesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r3, 63
+; CHECK:    subfc r3, r4, r3
+; CHECK:    rldicl r3, r4, 1, 63
+; CHECK:    adde r3, r6, r3
+; CHECK:    std r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llgesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    adde r3, r6, r3
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llgesll_z_store(i64 %a) {
+; CHECK-LABEL: test_llgesll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llgesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llgesll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllgess.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgess.ll
+++ test/CodeGen/PowerPC/testComparesllgess.ll
@@ -0,0 +1,124 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define i64 @test_llgess(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgess:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgess_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgess_z(i16 signext %a) {
+; CHECK-LABEL: test_llgess_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgess_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_llgess_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @test_llgess_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgess_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgess_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llgess_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llgess_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rlwinm r3, r3, 17, 31, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llgess_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llgess_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 15
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllgeuc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgeuc.ll
+++ test/CodeGen/PowerPC/testComparesllgeuc.ll
@@ -0,0 +1,112 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: test_llgeuc:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeuc_sext(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: @test_llgeuc_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeuc_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeuc_z
+; CHECK: li r3, 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeuc_sext_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeuc_sext_z
+; CHECK: li r3, -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK_LABEL: test_llgeuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: @test_llgeuc_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stb  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeuc_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv1 = zext i1 %cmp to i8
+  store i8 %conv1, i8* @glob
+  ret void
+; CHECK-LABEL: @test_llgeuc_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: stb [[REG1]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeuc_sext_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv1 = sext i1 %cmp to i8
+  store i8 %conv1, i8* @glob
+  ret void
+; CHECK-LABEL: @test_llgeuc_sext_z_store
+; CHECK: li [[REG1:r[0-9]+]], 255
+; CHECK: stb [[REG1]]
+; CHECK: blr
+}
+
Index: test/CodeGen/PowerPC/testComparesllgeui.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgeui.ll
+++ test/CodeGen/PowerPC/testComparesllgeui.ll
@@ -0,0 +1,112 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: test_llgeui:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeui_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr    
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeui_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeui_z
+; CHECK: li r3, 1
+; CHECK: blr    
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeui_sext_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeui_sext_z
+; CHECK: li r3, -1
+; CHECK-NEXT: blr    
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob
+  ret void
+; CHECK_LABEL: test_igeuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_llgeui_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stw  [[REG3]]
+; CHECK: blr  
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeui_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %sub = zext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_llgeui_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: stw [[REG1]]
+; CHECK: blr  
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeui_sext_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_llgeui_sext_z_store
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: stw [[REG1]]
+; CHECK: blr  
+}
+
Index: test/CodeGen/PowerPC/testComparesllgeull.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgeull.ll
+++ test/CodeGen/PowerPC/testComparesllgeull.ll
@@ -0,0 +1,110 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeull(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: test_llgeull:
+; CHECK: subfc {{r[0-9]+}}, r4, r3
+; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4
+; CHECK-NEXT: addi r3, [[REG1]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeull_sext(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeull_sext
+; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
+; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
+; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeull_z(i64 %a) {
+entry:
+  %cmp = icmp uge i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeull_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeull_sext_z(i64 %a) {
+entry:
+  %cmp = icmp uge i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeull_sext_z
+; CHECK: li r3, -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeull_store(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: test_llgeull_store:
+; CHECK: subfc {{r[0-9]+}}, r4, r3
+; CHECK: subfe [[REG1:r[0-9]+]], r4, r4
+; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeull_sext_store(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: @test_llgeull_sext_store
+; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
+; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
+; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
+; CHECK: std [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeull_z_store(i64 %a) {
+entry:
+  %cmp = icmp uge i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: @test_llgeull_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: std [[REG1]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeull_sext_z_store(i64 %a) {
+entry:
+  store i64 -1, i64* @glob
+  ret void
+; CHECK-LABEL: @test_llgeull_sext_z_store
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: std [[REG1]]
+; CHECK: blr
+}
+
Index: test/CodeGen/PowerPC/testComparesllgeus.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgeus.ll
+++ test/CodeGen/PowerPC/testComparesllgeus.ll
@@ -0,0 +1,113 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: test_llgeus:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeus_sext(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: @test_llgeus_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeus_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeus_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeus_sext_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeus_sext_z
+; CHECK: li r3, -1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK_LABEL: test_llgeus_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_llgeus_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: sth  [[REG3]]
+; CHECK: blr    
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeus_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv1 = zext i1 %cmp to i16
+  store i16 %conv1, i16* @glob
+  ret void
+; CHECK-LABEL: @test_llgeus_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: sth [[REG1]]
+; CHECK: blr  
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeus_sext_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv1 = sext i1 %cmp to i16
+  store i16 %conv1, i16* @glob
+  ret void
+; CHECK-LABEL: @test_llgeus_sext_z_store
+; CHECK: lis [[REG1:r[0-9]+]], 0
+; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535
+; CHECK: sth [[REG2]]
+; CHECK: blr  
+}
+
Index: test/CodeGen/PowerPC/testComparesllgtsc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgtsc.ll
+++ test/CodeGen/PowerPC/testComparesllgtsc.ll
@@ -0,0 +1,116 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgtsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgtsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsc_z(i8 signext %a) {
+; CHECK-LABEL: test_llgtsc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_llgtsc_sext_z:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgtsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgtsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_llgtsc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llgtsc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llgtsc_sext_z_store:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllgtsi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgtsi.ll
+++ test/CodeGen/PowerPC/testComparesllgtsi.ll
@@ -0,0 +1,116 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgtsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgtsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsi_z(i32 signext %a) {
+; CHECK-LABEL: test_llgtsi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_llgtsi_sext_z:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgtsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgtsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_llgtsi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llgtsi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llgtsi_sext_z_store:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllgtsll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgtsll.ll
+++ test/CodeGen/PowerPC/testComparesllgtsll.ll
@@ -0,0 +1,134 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgtsll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
+; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK-NEXT:    xori r3, [[REG4]], 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgtsll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
+; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK-NEXT:    xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK-NEXT:    neg r3, [[REG5]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsll_z(i64 %a) {
+; CHECK-LABEL: test_llgtsll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    nor r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsll_sext_z(i64 %a) {
+; CHECK-LABEL: test_llgtsll_sext_z:
+; CHECK:       addi [[REG1:r[0-9]+]], r3, -1
+; CHECK-NEXT:  nor [[REG2:r[0-9]+]], [[REG1]], r3
+; CHECK-NEXT:  sradi r3, [[REG2]], 63
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgtsll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
+; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
+; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK-NOT:     neg 
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgtsll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
+; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
+; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK:         neg {{r[0-9]+}}, [[REG5]]
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_llgtsll_z_store(i64 %a) {
+; CHECK-LABEL: test_llgtsll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r5, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llgtsll_sext_z_store:
+; CHECK:    addi [[REG1:r[0-9]+]], r3, -1
+; CHECK:    nor [[REG2:r[0-9]+]], [[REG1]], r3
+; CHECK:    sradi [[REG3:r[0-9]+]], [[REG2]], 63
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllgtss.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgtss.ll
+++ test/CodeGen/PowerPC/testComparesllgtss.ll
@@ -0,0 +1,117 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgtss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgtss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtss_z(i16 signext %a) {
+; CHECK-LABEL: test_llgtss_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_llgtss_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg [[REG:r[0-9]+]], r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgtss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgtss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_llgtss_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llgtss_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llgtss_sext_z_store:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllgtuc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgtuc.ll
+++ test/CodeGen/PowerPC/testComparesllgtuc.ll
@@ -0,0 +1,114 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc:
+; CHECK:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc_store:
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllgtui.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgtui.ll
+++ test/CodeGen/PowerPC/testComparesllgtui.ll
@@ -0,0 +1,114 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui:
+; CHECK-NOT:     clrldi
+; CHECK:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui_store:
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllgtull.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgtull.ll
+++ test/CodeGen/PowerPC/testComparesllgtull.ll
@@ -0,0 +1,124 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgtull:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NEXT:    neg r3, [[REG2]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgtull_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    subfe r3, [[REG2:r[0-9]+]], [[REG2]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtull_z(i64 %a) {
+; CHECK-LABEL: test_llgtull_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtull_sext_z(i64 %a) {
+; CHECK-LABEL: test_llgtull_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtull_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgtull_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK:         subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NEXT:    neg {{r[0-9]+}}, [[REG2]]
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtull_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgtull_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK:         subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NOT:     neg
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtull_z_store(i64 %a) {
+; CHECK-LABEL: test_llgtull_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtull_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llgtull_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
Index: test/CodeGen/PowerPC/testComparesllgtus.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllgtus.ll
+++ test/CodeGen/PowerPC/testComparesllgtus.ll
@@ -0,0 +1,127 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
Index: test/CodeGen/PowerPC/testCompareslllesc.ll
===================================================================
--- test/CodeGen/PowerPC/testCompareslllesc.ll
+++ test/CodeGen/PowerPC/testCompareslllesc.ll
@@ -0,0 +1,129 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define i64 @test_lllesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lllesc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lllesc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_lllesc_z(i8 signext %a) {
+; CHECK-LABEL: test_lllesc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_lllesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_lllesc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lllesc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lllesc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_lllesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_lllesc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_lllesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_lllesc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testCompareslllesi.ll
===================================================================
--- test/CodeGen/PowerPC/testCompareslllesi.ll
+++ test/CodeGen/PowerPC/testCompareslllesi.ll
@@ -0,0 +1,129 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define i64 @test_lllesi(i32 signext %a, i32 signext %b)  {
+; CHECK-LABEL: test_lllesi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b)  {
+; CHECK-LABEL: test_lllesi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_lllesi_z(i32 signext %a)  {
+; CHECK-LABEL: test_lllesi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_lllesi_sext_z(i32 signext %a)  {
+; CHECK-LABEL: test_lllesi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lllesi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lllesi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_lllesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_lllesi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_lllesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_lllesi_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testCompareslllesll.ll
===================================================================
--- test/CodeGen/PowerPC/testCompareslllesll.ll
+++ test/CodeGen/PowerPC/testCompareslllesll.ll
@@ -0,0 +1,138 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_lllesll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll_sext(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_lllesll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll_z(i64 %a)  {
+; CHECK-LABEL: test_lllesll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    or r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll_sext_z(i64 %a)  {
+; CHECK-LABEL: test_lllesll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    or r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lllesll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r4, 63
+; CHECK:    subfc r4, r3, r4
+; CHECK:    rldicl r3, r3, 1, 63
+; CHECK:    adde r3, r6, r3
+; CHECK:    std r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lllesll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r4, 63
+; CHECK-DAG:    rldicl r3, r3, 1, 63
+; CHECK-DAG:    subfc r4, r3, r4
+; CHECK:    adde r3, r6, r3
+; CHECK:    neg r3, r3
+; CHECK:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_z_store(i64 %a) {
+; CHECK-LABEL: test_lllesll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    or r3, r5, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_lllesll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    or r3, r5, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllless.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllless.ll
+++ test/CodeGen/PowerPC/testComparesllless.ll
@@ -0,0 +1,129 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define i64 @test_llless(i16 signext %a, i16 signext %b)  {
+; CHECK-LABEL: test_llless:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llless_sext(i16 signext %a, i16 signext %b)  {
+; CHECK-LABEL: test_llless_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llless_z(i16 signext %a)  {
+; CHECK-LABEL: test_llless_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_llless_sext_z(i16 signext %a)  {
+; CHECK-LABEL: test_llless_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llless_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llless_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llless_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llless_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llless_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llless_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llless_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllleuc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllleuc.ll
+++ test/CodeGen/PowerPC/testComparesllleuc.ll
@@ -0,0 +1,118 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: test_llleuc:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleuc_sext(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: @test_llleuc_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleuc_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp ule i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+; CHECK-LABEL: test_llleuc_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleuc_sext_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp ule i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+; CHECK-LABEL: @test_llleuc_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: test_llleuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: @test_llleuc_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stb  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleuc_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp ule i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob
+  ret void
+; CHECK-LABEL: test_llleuc_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi {{r[0-9]}}, r3, 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleuc_sext_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp ule i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob
+  ret void
+; CHECK-LABEL: @test_llleuc_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: stb [[REG4]]
+; CHECK: blr
+}
Index: test/CodeGen/PowerPC/testComparesllleui.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllleui.ll
+++ test/CodeGen/PowerPC/testComparesllleui.ll
@@ -0,0 +1,119 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: test_llleui:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleui_sext(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llleui_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleui_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp ule i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: test_llleui_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleui_sext_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp ule i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llleui_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi r3, [[REG3]], 63
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob
+  ret void
+; CHECK-LABEL: test_llleui_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_llleui_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stw  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleui_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp ule i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob
+  ret void
+; CHECK-LABEL: test_llleui_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleui_sext_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp ule i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_llleui_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: stw [[REG4]]
+; CHECK: blr
+}
+
Index: test/CodeGen/PowerPC/testComparesllleull.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllleull.ll
+++ test/CodeGen/PowerPC/testComparesllleull.ll
@@ -0,0 +1,115 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleull(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: test_llleull:
+; CHECK: subfc {{r[0-9]+}}, r3, r4
+; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3
+; CHECK-NEXT: addi r3, [[REG1]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleull_sext(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llleull_sext
+; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
+; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleull_z(i64 %a) {
+entry:
+  %cmp = icmp ule i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: test_llleull_z
+; CHECK: cntlzd [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleull_sext_z(i64 %a) {
+entry:
+  %cmp = icmp ule i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llleull_sext_z
+; CHECK: addic [[REG1:r[0-9]+]], r3, -1
+; CHECK: subfe r3, [[REG1]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleull_store(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: test_llleull_store:
+; CHECK: subfc {{r[0-9]+}}, r3, r4
+; CHECK: subfe [[REG1:r[0-9]+]], r3, r3
+; CHECK: addi r3, [[REG1]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleull_sext_store(i64 %a, i64 %b) {
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: @test_llleull_sext_store
+; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
+; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
+; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
+; CHECK: std [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleull_z_store(i64 %a) {
+entry:
+  %cmp = icmp ule i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: test_llleull_z_store:
+; CHECK: cntlzd [[REG1:r[0-9]+]], r3
+; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleull_sext_z_store(i64 %a) {
+entry:
+  %cmp = icmp ule i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob
+  ret void
+; CHECK-LABEL: @test_llleull_sext_z_store
+; CHECK: addic [[REG1:r[0-9]+]], r3, -1
+; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
+; CHECK: std [[REG2]]
+; CHECK: blr
+}
+
Index: test/CodeGen/PowerPC/testComparesllleus.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllleus.ll
+++ test/CodeGen/PowerPC/testComparesllleus.ll
@@ -0,0 +1,119 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: test_llleus:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleus_sext(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: @test_llleus_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleus_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+; CHECK-LABEL: test_llleus_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleus_sext_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+; CHECK-LABEL: @test_llleus_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: test_llleus_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_llleus_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: sth  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleus_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob
+  ret void
+; CHECK-LABEL: test_llleus_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleus_sext_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob
+  ret void
+; CHECK-LABEL: @test_llleus_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: sth [[REG4]]
+; CHECK: blr
+}
+
Index: test/CodeGen/PowerPC/testComparesllltsc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllltsc.ll
+++ test/CodeGen/PowerPC/testComparesllltsc.ll
@@ -0,0 +1,85 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llltsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llltsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_llltsc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llltsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llltsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llltsc_sext_z_store:
+; CHECK:    srwi {{r[0-9]+}}, r3, 7
+; CHECK:    blr
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllltsi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllltsi.ll
+++ test/CodeGen/PowerPC/testComparesllltsi.ll
@@ -0,0 +1,84 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llltsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llltsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsi_sext_z(i32 signext %a)  {
+; CHECK-LABEL: test_llltsi_sext_z:
+; CHECK:       srawi r3, r3, 31
+; CHECK-NEXT:  blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llltsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llltsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llltsi_sext_z_store:
+; CHECK:    srawi r3, r3, 31
+; CHECK:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %conv1 = sext i1 %cmp to i32
+  store i32 %conv1, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllltsll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllltsll.ll
+++ test/CodeGen/PowerPC/testComparesllltsll.ll
@@ -0,0 +1,99 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llltsll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
+; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK-NEXT:    xori r3, [[REG4]], 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llltsll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
+; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK-NEXT:    xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK-NEXT:    neg r3, [[REG5]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsll_sext_z(i64 %a) {
+; CHECK-LABEL: test_llltsll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 0
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llltsll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
+; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
+; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK-NOT:     neg
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llltsll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
+; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
+; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
+; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
+; CHECK:         neg {{r[0-9]+}}, [[REG5]]
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llltsll_sext_z_store:
+; CHECK:    sradi r3, r3, 63
+entry:
+  %cmp = icmp slt i64 %a, 0
+  %sub = sext i1 %cmp to i64
+  store i64 %sub, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllltss.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllltss.ll
+++ test/CodeGen/PowerPC/testComparesllltss.ll
@@ -0,0 +1,84 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llltss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llltss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_llltss_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    srawi r3, r3, 31
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llltss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llltss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llltss_sext_z_store:
+; CHECK: srwi r3, r3, 15
+; CHECK: blr
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllltuc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllltuc.ll
+++ test/CodeGen/PowerPC/testComparesllltuc.ll
@@ -0,0 +1,60 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllltui.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllltui.ll
+++ test/CodeGen/PowerPC/testComparesllltui.ll
@@ -0,0 +1,110 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui:
+; CHECK:       # BB#0: # %entry
+; CHECK-NOT:     clrldi
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rldicl r3, r3, 0, 32
+; CHECK-NEXT:    rldicl r4, r4, 0, 32
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  ret i64 0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  ret i64 0
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NOT:     clrldi
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NOT:     clrldi
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         li [[REG:r[0-9]+]], 0
+; CHECK:         stw [[REG]], 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store i32 0, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         li [[REG:r[0-9]+]], 0
+; CHECK:         stw [[REG]], 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store i32 0, i32* @glob, align 4
+  ret void
+}
+
Index: test/CodeGen/PowerPC/testComparesllltull.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllltull.ll
+++ test/CodeGen/PowerPC/testComparesllltull.ll
@@ -0,0 +1,108 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llltull:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc [[REG:r[1-9]+]], r4, r3
+; CHECK-NEXT:    subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NEXT:    neg r3, [[REG2]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llltull_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    subfe r3, [[REG2:r[0-9]+]], [[REG2]]
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltull_z(i64 %a) {
+; CHECK-LABEL: test_llltull_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  ret i64 0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltull_sext_z(i64 %a) {
+; CHECK-LABEL: test_llltull_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  ret i64 0
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltull_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llltull_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subfc [[REG:r[0-9]+]], r4, r3
+; CHECK:         subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NEXT:    neg {{r[0-9]+}}, [[REG2]]
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltull_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llltull_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subfc [[REG:r[0-9]+]], r4, r3
+; CHECK:         subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
+; CHECK-NOT:     neg
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltull_z_store(i64 %a) {
+; CHECK-LABEL: test_llltull_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         li [[REG:r[0-9]+]], 0
+; CHECK:         std [[REG]], 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store i64 0, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltull_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llltull_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         li [[REG:r[0-9]+]], 0
+; CHECK:         std [[REG]], 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store i64 0, i64* @glob, align 8
+  ret void
+}
+
Index: test/CodeGen/PowerPC/testComparesllltus.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllltus.ll
+++ test/CodeGen/PowerPC/testComparesllltus.ll
@@ -0,0 +1,59 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus_store:
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllnesc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllnesc.ll
+++ test/CodeGen/PowerPC/testComparesllnesc.ll
@@ -0,0 +1,121 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define i64 @test_llnesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llnesc:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llnesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llnesc_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llnesc_z(i8 signext %a) {
+; CHECK-LABEL: test_llnesc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_llnesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_llnesc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llnesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llnesc_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llnesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llnesc_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llnesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llnesc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llnesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llnesc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllnesi.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllnesi.ll
+++ test/CodeGen/PowerPC/testComparesllnesi.ll
@@ -0,0 +1,121 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define i64 @test_llnesi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llnesi:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llnesi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llnesi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llnesi_z(i32 signext %a) {
+; CHECK-LABEL: test_llnesi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llnesi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_llnesi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llnesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llnesi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llnesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llnesi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llnesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llnesi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llnesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llnesi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllnesll.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllnesll.ll
+++ test/CodeGen/PowerPC/testComparesllnesll.ll
@@ -0,0 +1,125 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define i64 @test_llnesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llnesll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llnesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llnesll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llnesll_z(i64 %a) {
+; CHECK-LABEL: test_llnesll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llnesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_llnesll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llnesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llnesll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r5, r3, -1
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llnesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llnesll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llnesll_z_store(i64 %a) {
+; CHECK-LABEL: test_llnesll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llnesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llnesll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllness.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllness.ll
+++ test/CodeGen/PowerPC/testComparesllness.ll
@@ -0,0 +1,121 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define i64 @test_llness(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llness:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llness_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llness_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llness_z(i16 signext %a) {
+; CHECK-LABEL: test_llness_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_llness_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_llness_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llness_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llness_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llness_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llness_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llness_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llness_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llness_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llness_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllneuc.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllneuc.ll
+++ test/CodeGen/PowerPC/testComparesllneuc.ll
@@ -0,0 +1,137 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define i64 @test_llneuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llneuc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llneuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llneuc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llneuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llneuc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_llneuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llneuc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llneuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llneuc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llneuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llneuc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llneuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llneuc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llneuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llneuc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllneui.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllneui.ll
+++ test/CodeGen/PowerPC/testComparesllneui.ll
@@ -0,0 +1,121 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define i64 @test_llneui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llneui:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llneui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llneui_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llneui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llneui_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llneui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llneui_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llneui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llneui_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llneui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llneui_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llneui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llneui_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llneui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llneui_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllneull.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllneull.ll
+++ test/CodeGen/PowerPC/testComparesllneull.ll
@@ -0,0 +1,125 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define i64 @test_llneull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llneull:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llneull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llneull_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llneull_z(i64 %a) {
+; CHECK-LABEL: test_llneull_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llneull_sext_z(i64 %a) {
+; CHECK-LABEL: test_llneull_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llneull_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llneull_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r5, r3, -1
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llneull_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llneull_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llneull_z_store(i64 %a) {
+; CHECK-LABEL: test_llneull_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llneull_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llneull_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfic r3, r3, 0
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
Index: test/CodeGen/PowerPC/testComparesllneus.ll
===================================================================
--- test/CodeGen/PowerPC/testComparesllneus.ll
+++ test/CodeGen/PowerPC/testComparesllneus.ll
@@ -0,0 +1,137 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define i64 @test_llneus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llneus:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llneus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llneus_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llneus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llneus_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_llneus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llneus_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llneus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llneus_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llneus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llneus_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llneus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llneus_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llneus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llneus_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
Index: test/CodeGen/PowerPC/testSelectSetCCEQ.ll
===================================================================
--- test/CodeGen/PowerPC/testSelectSetCCEQ.ll
+++ test/CodeGen/PowerPC/testSelectSetCCEQ.ll
@@ -0,0 +1,131 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi64:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi32:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i64 @set_flagi64_z(i64 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi64_z:
+; CHECK:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32_z(i32 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi32_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32_z:
+; CHECK:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64_z(i32 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
Index: test/CodeGen/PowerPC/testSelectSetCCGE.ll
===================================================================
--- test/CodeGen/PowerPC/testSelectSetCCGE.ll
+++ test/CodeGen/PowerPC/testSelectSetCCGE.ll
@@ -0,0 +1,142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    rldicl r7, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r6, r7
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32(i32 signext %a, i32 signext %b, i32 %flags) {
+; CHECK-LABEL: set_flagi32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    rldicl r7, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r6, r7
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64(i32 signext %a, i32 signext %b, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i64 @set_flagi64_z(i64 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi64_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    li r5, 8
+; CHECK-NEXT:    rldicl r3, r3, 4, 60
+; CHECK-NEXT:    andc r3, r5, r3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32_z(i32 signext %a, i32 %flags) {
+; CHECK-LABEL: set_flagi32_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    srwi r3, r3, 28
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    rlwinm r3, r3, 0, 28, 28
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64_z(i32 signext %a, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
Index: test/CodeGen/PowerPC/testSelectSetCCGT.ll
===================================================================
--- test/CodeGen/PowerPC/testSelectSetCCGT.ll
+++ test/CodeGen/PowerPC/testSelectSetCCGT.ll
@@ -0,0 +1,143 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r4, 63
+; CHECK-NEXT:    rldicl r7, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r7, r6
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32(i32 signext %a, i32 signext %b, i32 %flags) {
+; CHECK-LABEL: set_flagi32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r4, 63
+; CHECK-NEXT:    rldicl r7, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r7, r6
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64(i32 signext %a, i32 signext %b, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i64 @set_flagi64_z(i64 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi64_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    nor r3, r5, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32_z(i32 signext %a, i32 %flags) {
+; CHECK-LABEL: set_flagi32_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    nor r3, r5, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64_z(i32 signext %a, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
Index: test/CodeGen/PowerPC/testSelectSetCCLE.ll
===================================================================
--- test/CodeGen/PowerPC/testSelectSetCCLE.ll
+++ test/CodeGen/PowerPC/testSelectSetCCLE.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r4, 63
+; CHECK-NEXT:    rldicl r7, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r6, r7
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32(i32 signext %a, i32 signext %b, i32 %flags) {
+; CHECK-LABEL: set_flagi32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r4, 63
+; CHECK-NEXT:    rldicl r7, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r6, r7
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64(i32 signext %a, i32 signext %b, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i64 @set_flagi64_z(i64 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi64_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    or r3, r5, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32_z(i32 signext %a, i32 %flags) {
+; CHECK-LABEL: set_flagi32_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    or r3, r5, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64_z(i32 signext %a, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
Index: test/CodeGen/PowerPC/testSelectSetCCLT.ll
===================================================================
--- test/CodeGen/PowerPC/testSelectSetCCLT.ll
+++ test/CodeGen/PowerPC/testSelectSetCCLT.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    rldicl r7, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r7, r6
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32(i32 signext %a, i32 signext %b, i32 zeroext %flags) {
+; CHECK-LABEL: set_flagi32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32(i64 %a, i64 %b, i32 zeroext %flags) {
+; CHECK-LABEL: set_flagi64i32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    rldicl r7, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r7, r6
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64(i32 signext %a, i32 signext %b, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i64 @set_flagi64_z(i64 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi64_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rotldi r3, r3, 1
+; CHECK-NEXT:    rldic r3, r3, 3, 60
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32_z(i32 signext %a, i32 %flags) {
+; CHECK-LABEL: set_flagi32_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rlwinm r3, r3, 4, 28, 28
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64_z(i32 signext %a, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
Index: test/CodeGen/PowerPC/testSelectSetCCNE.ll
===================================================================
--- test/CodeGen/PowerPC/testSelectSetCCNE.ll
+++ test/CodeGen/PowerPC/testSelectSetCCNE.ll
@@ -0,0 +1,135 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi64:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi32:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    addic r4, r3, -1
+; CHECK-NEXT:    subfe r3, r4, r3
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i64 @set_flagi64_z(i64 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi64_z:
+; CHECK:    addic r5, r3, -1
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32_z(i32 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi32_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32_z:
+; CHECK:    addic r5, r3, -1
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64_z(i32 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
Index: test/CodeGen/PowerPC/testSelectSetCCUGE.ll
===================================================================
--- test/CodeGen/PowerPC/testSelectSetCCUGE.ll
+++ test/CodeGen/PowerPC/testSelectSetCCUGE.ll
@@ -0,0 +1,131 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    clrldi r4, r4, 32
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    clrldi r4, r4, 32
+; CHECK-NEXT:    li r6, 8
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 4, 60
+; CHECK-NEXT:    andc r3, r6, r3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i64 @set_flagi64_z(i64 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi64_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    ori r3, r4, 8
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32_z(i32 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi32_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    ori r3, r4, 8
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    ori r3, r4, 8
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64_z(i32 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    ori r3, r4, 8
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
Index: test/CodeGen/PowerPC/testSelectSetCCUGT.ll
===================================================================
--- test/CodeGen/PowerPC/testSelectSetCCUGT.ll
+++ test/CodeGen/PowerPC/testSelectSetCCUGT.ll
@@ -0,0 +1,133 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi64:
+; CHECK:    subfc r3, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi32:
+; CHECK:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32:
+; CHECK:    subfc r3, r3, r4
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64:
+; CHECK:    clrldi r4, r4, 32
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rotldi r3, r3, 1
+; CHECK-NEXT:    rldic r3, r3, 3, 60
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i64 @set_flagi64_z(i64 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi64_z:
+; CHECK:    addic r5, r3, -1
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32_z(i32 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi32_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32_z:
+; CHECK:    addic r5, r3, -1
+; CHECK-NEXT:    subfe r3, r5, r3
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64_z(i32 %a, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, 0
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
Index: test/CodeGen/PowerPC/testSelectSetCCULE.ll
===================================================================
--- test/CodeGen/PowerPC/testSelectSetCCULE.ll
+++ test/CodeGen/PowerPC/testSelectSetCCULE.ll
@@ -0,0 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    clrldi r4, r4, 32
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    clrldi r4, r4, 32
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    li r6, 8
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 4, 60
+; CHECK-NEXT:    andc r3, r6, r3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
Index: test/CodeGen/PowerPC/testSelectSetCCULT.ll
===================================================================
--- test/CodeGen/PowerPC/testSelectSetCCULT.ll
+++ test/CodeGen/PowerPC/testSelectSetCCULT.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r4, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
+
+define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    clrldi r4, r4, 32
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
+; CHECK-LABEL: set_flagi64i32:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subfc r4, r4, r3
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    slwi r3, r3, 3
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 3
+  %or = or i32 %shl, %flags
+  ret i32 %or
+}
+
+define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
+; CHECK-LABEL: set_flagi32i64:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    clrldi r4, r4, 32
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rotldi r3, r3, 1
+; CHECK-NEXT:    rldic r3, r3, 3, 60
+; CHECK-NEXT:    or r3, r3, r5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv = zext i1 %cmp to i64
+  %shl = shl nuw nsw i64 %conv, 3
+  %or = or i64 %shl, %flags
+  ret i64 %or
+}
Index: test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
===================================================================
--- test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
+++ test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
@@ -70,8 +70,7 @@
 ; CHECK-LABEL: @getf
 ; CHECK-P7-LABEL: @getf
 ; CHECK-BE-LABEL: @getf
-; CHECK: li [[IMMREG:[0-9]+]], 3
-; CHECK: xor [[TRUNCREG:[0-9]+]], [[IMMREG]], 5
+; CHECK: xori [[TRUNCREG:[0-9]+]], 5, 3
 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[TRUNCREG]]
 ; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
 ; CHECK: xscvspdpn 1,