Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp =================================================================== --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -2648,7 +2648,14 @@ // Produces a sign/zero extended result of comparing whether a 64-bit value is // greater than or equal to zero. SDValue PPCDAGToDAGISel::getSETGE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext) { - return SDValue(); + SDValue Not = + SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, LHS, LHS), 0); + if (IsSext) + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Not, + getI64Imm(31, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Not, + getI64Imm(1, dl), getI64Imm(63, dl)), + 0); } // Produces a sign/zero extended result of comparing whether a 32-bit value is @@ -2670,7 +2677,18 @@ // Produces a sign/zero extended result of comparing whether a 64-bit value is // less than or equal to zero. SDValue PPCDAGToDAGISel::getSETLE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext) { - return SDValue(); + SDValue Addi = + SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS, + getI64Imm(~0ULL, dl)), 0); + SDValue Or = + SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64, + Addi, LHS), 0); + if (IsSext) + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Or, + getI64Imm(63, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + Or, getI64Imm(1, dl), + getI64Imm(63, dl)), 0); } static void swapAndReset(SDValue &LHS, SDValue &RHS, bool &IsRHSZero, @@ -2896,7 +2914,116 @@ SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, int64_t RHSValue, SDLoc dl) { - return SDValue(); + bool IsRHSZero = RHSValue == 0; + bool IsRHSOne = RHSValue == 1; + bool IsRHSNegOne = RHSValue == -1LL; + switch (CC) { + default: llvm_unreachable("Unknown condition!"); + case ISD::SETEQ: { + SDValue Xor = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0); + SDValue Clz = + SDValue(CurDAG->getMachineNode(PPC::CNTLZD, dl, MVT::i64, Xor), 0); + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Clz, + getI64Imm(58, dl), getI64Imm(63, dl)), + 0); + } + case ISD::SETNE: { + SDValue Xor = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0); + SDValue AC = + SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue, + Xor, getI32Imm(~0U, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, AC, + Xor, AC.getValue(1)), 0); + } + case ISD::SETGE: { + if (IsRHSZero) + return getSETGE0I64InGPR(LHS, dl, false); + swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne); + LLVM_FALLTHROUGH; + } + case ISD::SETLE: { + if (IsRHSZero) + return getSETLE0I64InGPR(LHS, dl, false); + SDValue ShiftL = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS, + getI64Imm(1, dl), getI64Imm(63, dl)), 0); + SDValue ShiftR = + SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS, + getI64Imm(63, dl)), 0); + SDValue SubtractCarry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + LHS, RHS), 1); + return SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue, + ShiftR, ShiftL, SubtractCarry), 0); + } + case ISD::SETGT: { + if (IsRHSNegOne) + return getSETGE0I64InGPR(LHS, dl, false); + if (IsRHSZero) { + SDValue Addi = + SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS, + getI64Imm(~0ULL, dl)), 0); + SDValue Nor = + SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Addi, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Nor, + getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + } + swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne); + LLVM_FALLTHROUGH; + } + case ISD::SETLT: { + if (IsRHSOne) + return getSETLE0I64InGPR(LHS, dl, false); + if (IsRHSZero) + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS, + getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + SDValue SRADINode = + SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, + LHS, getI64Imm(63, dl)), 0); + SDValue SRDINode = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + RHS, getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + SDValue SUBFC8Carry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + RHS, LHS), 1); + SDValue ADDE8Node = + SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue, + SRDINode, SRADINode, SUBFC8Carry), 0); + return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, + ADDE8Node, getI64Imm(1, dl)), 0); + } + case ISD::SETUGE: + swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne); + LLVM_FALLTHROUGH; + case ISD::SETULE: { + SDValue SUBFC8Carry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + LHS, RHS), 1); + SDValue SUBFE8Node = + SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue, + LHS, LHS, SUBFC8Carry), 0); + return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, + SUBFE8Node, getI64Imm(1, dl)), 0); + } + case ISD::SETUGT: + swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne); + LLVM_FALLTHROUGH; + case ISD::SETULT: { + SDValue SubtractCarry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + RHS, LHS), 1); + SDValue ExtSub = + SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, + LHS, LHS, SubtractCarry), 0); + return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, + ExtSub), 0); + } + } } /// Produces a sign-extended result of comparing two 64-bit values according to @@ -2904,7 +3031,118 @@ SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, int64_t RHSValue, SDLoc dl) { - return SDValue(); + bool IsRHSZero = RHSValue == 0; + bool IsRHSOne = RHSValue == 1; + bool IsRHSNegOne = RHSValue == -1LL; + switch (CC) { + default: llvm_unreachable("Unknown condition!"); + case ISD::SETEQ: { + SDValue AddInput = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0); + SDValue Addic = + SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue, + AddInput, getI32Imm(~0U, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, Addic, + Addic, Addic.getValue(1)), 0); + } + case ISD::SETNE: { + SDValue Xor = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0); + SDValue SC = + SDValue(CurDAG->getMachineNode(PPC::SUBFIC8, dl, MVT::i64, MVT::Glue, + Xor, getI32Imm(0, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, SC, + SC, SC.getValue(1)), 0); + } + case ISD::SETGE: { + if (IsRHSZero) + return getSETGE0I64InGPR(LHS, dl, true); + swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne); + LLVM_FALLTHROUGH; + } + case ISD::SETLE: { + if (IsRHSZero) + return getSETLE0I64InGPR(LHS, dl, true); + SDValue ShiftR = + SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS, + getI64Imm(63, dl)), 0); + SDValue ShiftL = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS, + getI64Imm(1, dl), getI64Imm(63, dl)), 0); + SDValue SubtractCarry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + LHS, RHS), 1); + SDValue Adde = + SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue, + ShiftR, ShiftL, SubtractCarry), 0); + return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, Adde), 0); + } + case ISD::SETGT: { + if (IsRHSNegOne) + return getSETGE0I64InGPR(LHS, dl, true); + if (IsRHSZero) { + SDValue Add = + SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS, + getI64Imm(-1, dl)), 0); + SDValue Nor = + SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Add, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Nor, + getI64Imm(63, dl)), 0); + } + swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne); + LLVM_FALLTHROUGH; + } + case ISD::SETLT: { + if (IsRHSOne) + return getSETLE0I64InGPR(LHS, dl, true); + if (IsRHSZero) { + llvm_unreachable("Should be transformed upstream!"); + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, LHS, + getI64Imm(63, dl)), 0); + } + SDValue SRADINode = + SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, + LHS, getI64Imm(63, dl)), 0); + SDValue SRDINode = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + RHS, getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + SDValue SUBFC8Carry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + RHS, LHS), 1); + SDValue ADDE8Node = + SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, + SRDINode, SRADINode, SUBFC8Carry), 0); + SDValue XORI8Node = + SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, + ADDE8Node, getI64Imm(1, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, + XORI8Node), 0); + } + case ISD::SETUGE: + swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne); + LLVM_FALLTHROUGH; + case ISD::SETULE: { + SDValue SubtractCarry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + LHS, RHS), 1); + SDValue ExtSub = + SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue, LHS, + LHS, SubtractCarry), 0); + return SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, + ExtSub, ExtSub), 0); + } + case ISD::SETUGT: + swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne); + LLVM_FALLTHROUGH; + case ISD::SETULT: { + SDValue SubCarry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + RHS, LHS), 1); + return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, + LHS, LHS, SubCarry), 0); + } + } } /// Returns an equivalent of a SETCC node but with the result the same width as Index: test/CodeGen/PowerPC/expand-isel.ll =================================================================== --- test/CodeGen/PowerPC/expand-isel.ll +++ test/CodeGen/PowerPC/expand-isel.ll @@ -212,13 +212,12 @@ ret i32 %retval.0 ; CHECK-LABEL: @testComplexISEL -; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]] -; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NEXT: [[TRUE]] -; CHECK-NEXT: addi r3, r12, 0 -; CHECK-NEXT: [[SUCCESSOR]] -; CHECK-NEXT: clrldi r3, r3, 32 -; CHECK-NEXT: blr +; CHECK-DAG: [[LI:r[0-9]+]], 1 +; CHECK-DAG: cmplwi [[LD:r[0-9]+]], 0 +; CHECK: bnelr cr0 +; CHECK: xor [[XOR:r[0-9]+]] +; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]] +; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63 } !1 = !{!2, !2, i64 0} Index: test/CodeGen/PowerPC/optcmp.ll =================================================================== --- test/CodeGen/PowerPC/optcmp.ll +++ test/CodeGen/PowerPC/optcmp.ll @@ -127,8 +127,12 @@ ret i64 %conv1 ; CHECK: @foo2l -; CHECK: sld. 4, 3, 4 -; CHECK: std 4, 0(5) +; CHECK: sld 4, 3, 4 +; CHECK-NEXT: addi 3, 4, -1 +; CHECK-NEXT: std 4, 0(5) +; CHECK-NEXT: nor 3, 3, 4 +; CHECK-NEXT: rldicl 3, 3, 1, 63 +; CHECK-NEXT: blr } define double @food(double %a, double %b, double* nocapture %c) #0 { Index: test/CodeGen/PowerPC/setcc-logic.ll =================================================================== --- test/CodeGen/PowerPC/setcc-logic.ll +++ test/CodeGen/PowerPC/setcc-logic.ll @@ -422,11 +422,11 @@ define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) { ; CHECK-LABEL: ne_neg1_and_ne_zero: ; CHECK: # BB#0: +; CHECK-NEXT: li 4, 1 ; CHECK-NEXT: addi 3, 3, 1 -; CHECK-NEXT: li 4, 0 -; CHECK-NEXT: li 12, 1 -; CHECK-NEXT: cmpldi 3, 1 -; CHECK-NEXT: isel 3, 12, 4, 1 +; CHECK-NEXT: subfc 3, 3, 4 +; CHECK-NEXT: subfe 3, 4, 4 +; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: blr %cmp1 = icmp ne i64 %x, -1 %cmp2 = icmp ne i64 %x, 0 Index: test/CodeGen/PowerPC/testComparesieqsll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesieqsll.ll @@ -0,0 +1,134 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; ModuleID = 'ComparisonTestCases/testComparesieqsll.c' + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ieqsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_ieqsll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_ieqsll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ieqsll_z(i64 %a) { +; CHECK-LABEL: test_ieqsll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ieqsll_sext_z(i64 %a) { +; CHECK-LABEL: test_ieqsll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_ieqsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_ieqsll_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_ieqsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_ieqsll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_ieqsll_z_store(i64 %a) { +; CHECK-LABEL: test_ieqsll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_ieqsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_ieqsll_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesiequll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesiequll.ll @@ -0,0 +1,134 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; ModuleID = 'ComparisonTestCases/testComparesiequll.c' + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iequll(i64 %a, i64 %b) { +; CHECK-LABEL: test_iequll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iequll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_iequll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iequll_z(i64 %a) { +; CHECK-LABEL: test_iequll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iequll_sext_z(i64 %a) { +; CHECK-LABEL: test_iequll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_iequll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_iequll_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iequll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_iequll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iequll_z_store(i64 %a) { +; CHECK-LABEL: test_iequll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iequll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_iequll_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesigesll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesigesll.ll @@ -0,0 +1,128 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i64 0, align 8 + +define signext i32 @test_igesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r5, r3, 63 +; CHECK-NEXT: rldicl r6, r4, 1, 63 +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_igesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r5, r3, 63 +; CHECK-NEXT: rldicl r6, r4, 1, 63 +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define signext i32 @test_igesll_z(i64 %a) { +; CHECK-LABEL: test_igesll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_igesll_sext_z(i64 %a) { +; CHECK-LABEL: test_igesll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: not r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_igesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi r6, r3, 63 +; CHECK: subfc r3, r4, r3 +; CHECK: rldicl r3, r4, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_igesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r6, r3, 63 +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: rldicl r3, r4, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: adde r3, r6, r3 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_igesll_z_store(i64 %a) { +; CHECK-LABEL: test_igesll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_igesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_igesll_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: not r3, r3 +; CHECK-NEXT: std r3, +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesigeull.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesigeull.ll @@ -0,0 +1,111 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +; CHECK-LABEL: test_igeull: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not r3, [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %sub = zext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeull_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull_sext_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeull_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_igeull_store: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK: addi {{r[0-9]+}}, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_igeull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_z_store(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_igeull_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: std [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_sext_z_store(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_igeull_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: std [[REG1]] +; CHECK: blr +} Index: test/CodeGen/PowerPC/testComparesigtsll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesigtsll.ll @@ -0,0 +1,134 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; FIXME +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll_z(i64 %a) { +; CHECK-LABEL: test_igtsll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: nor r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll_sext_z(i64 %a) { +; CHECK-LABEL: test_igtsll_sext_z: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK-NEXT: sradi r3, [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_igtsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; FIXME +; Function Attrs: norecurse nounwind +define void @test_igtsll_z_store(i64 %a) { +; CHECK-LABEL: test_igtsll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: nor r3, r5, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_igtsll_sext_z_store: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesigtull.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesigtull.ll @@ -0,0 +1,126 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtull(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtull: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtull_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtull_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: subfe r3, [[REG2:r[0-9]+]], [[REG2]] +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtull_z(i64 %a) { +; CHECK-LABEL: test_igtull_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtull_sext_z(i64 %a) { +; CHECK-LABEL: test_igtull_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_igtull_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtull_store: +; CHECK: # BB#0: # %entry +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NEXT: neg {{r[0-9]+}}, [[REG2]] +; CHECK: blr +entry: + %cmp = icmp ugt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtull_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtull_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NOT: neg +; CHECK: blr +entry: + %cmp = icmp ugt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtull_z_store(i64 %a) { +; CHECK-LABEL: test_igtull_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtull_sext_z_store(i64 %a) { +; CHECK-LABEL: test_igtull_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + Index: test/CodeGen/PowerPC/testComparesilesll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesilesll.ll @@ -0,0 +1,130 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i64 0, align 8 + +define signext i32 @test_ilesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_ilesll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r5, r4, 63 +; CHECK-NEXT: rldicl r6, r3, 1, 63 +; CHECK-NEXT: subfc r12, r3, r4 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_ilesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_ilesll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r5, r4, 63 +; CHECK-NEXT: rldicl r6, r3, 1, 63 +; CHECK-NEXT: subfc r12, r3, r4 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define signext i32 @test_ilesll_z(i64 %a) { +; CHECK-LABEL: test_ilesll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: or r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_ilesll_sext_z(i64 %a) { +; CHECK-LABEL: test_ilesll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: or r3, r4, r3 +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_ilesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_ilesll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi r6, r4, 63 +; CHECK: subfc r4, r3, r4 +; CHECK: rldicl r3, r3, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3, +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ilesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_ilesll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi r6, r4, 63 +; CHECK-DAG: rldicl r3, r3, 1, 63 +; CHECK-DAG: subfc r4, r3, r4 +; CHECK: adde r3, r6, r3 +; CHECK: neg r3, r3 +; CHECK: std r3, +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ilesll_z_store(i64 %a) { +; CHECK-LABEL: test_ilesll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: or r3, r5, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ilesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_ilesll_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: or r3, r5, r3 +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesileull.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesileull.ll @@ -0,0 +1,115 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +; CHECK-LABEL: test_ileull: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not r3, [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +; CHECK-LABEL: test_ileull_z +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull_sext_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileull_sext_z +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe r3, [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_ileull_store: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK: addi {{r[0-9]+}}, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_ileull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_ileull_z_store: +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_sext_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_ileull_sext_z_store +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: std [[REG2]] +; CHECK: blr +} + Index: test/CodeGen/PowerPC/testComparesiltsll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesiltsll.ll @@ -0,0 +1,99 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsll_sext_z(i64 %a) { +; CHECK-LABEL: test_iltsll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_iltsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_iltsll_sext_z_store: +; CHECK: sradi r3, r3, 63 +entry: + %cmp = icmp slt i64 %a, 0 + %conv2 = sext i1 %cmp to i64 + store i64 %conv2, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesiltull.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesiltull.ll @@ -0,0 +1,108 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltull(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltull: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfc [[REG:r[1-9]+]], r4, r3 +; CHECK-NEXT: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltull_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltull_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfc [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: subfe r3, [[REG2:r[0-9]+]], [[REG2]] +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltull_z(i64 %a) { +; CHECK-LABEL: test_iltull_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: li r3, 0 +; CHECK-NEXT: blr +entry: + ret i32 0 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltull_sext_z(i64 %a) { +; CHECK-LABEL: test_iltull_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: li r3, 0 +; CHECK-NEXT: blr +entry: + ret i32 0 +} + +; Function Attrs: norecurse nounwind +define void @test_iltull_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltull_store: +; CHECK: # BB#0: # %entry +; CHECK: subfc [[REG:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NEXT: neg {{r[0-9]+}}, [[REG2]] +entry: + %cmp = icmp ult i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltull_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltull_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: subfc [[REG:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NOT: neg +entry: + %cmp = icmp ult i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltull_z_store(i64 %a) { +; CHECK-LABEL: test_iltull_z_store: +; CHECK: # BB#0: # %entry +; CHECK: li [[REG:r[0-9]+]], 0 +; CHECK: std [[REG]], 0(r3) +; CHECK-NEXT: blr +entry: + store i64 0, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltull_sext_z_store(i64 %a) { +; CHECK-LABEL: test_iltull_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK: li [[REG:r[0-9]+]], 0 +; CHECK: std [[REG]], 0(r3) +; CHECK-NEXT: blr +entry: + store i64 0, i64* @glob, align 8 + ret void +} + Index: test/CodeGen/PowerPC/testComparesinesll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesinesll.ll @@ -0,0 +1,125 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +define signext i32 @test_inesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_inesll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_inesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_inesll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define signext i32 @test_inesll_z(i64 %a) { +; CHECK-LABEL: test_inesll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_inesll_sext_z(i64 %a) { +; CHECK-LABEL: test_inesll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_inesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_inesll_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_inesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_inesll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_inesll_z_store(i64 %a) { +; CHECK-LABEL: test_inesll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_inesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_inesll_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesineull.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesineull.ll @@ -0,0 +1,125 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +define signext i32 @test_ineull(i64 %a, i64 %b) { +; CHECK-LABEL: test_ineull: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_ineull_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_ineull_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define signext i32 @test_ineull_z(i64 %a) { +; CHECK-LABEL: test_ineull_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_ineull_sext_z(i64 %a) { +; CHECK-LABEL: test_ineull_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_ineull_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_ineull_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ineull_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_ineull_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ineull_z_store(i64 %a) { +; CHECK-LABEL: test_ineull_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ineull_sext_z_store(i64 %a) { +; CHECK-LABEL: test_ineull_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testCompareslleqsll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testCompareslleqsll.ll @@ -0,0 +1,133 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lleqsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_lleqsll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lleqsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_lleqsll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lleqsll_z(i64 %a) { +; CHECK-LABEL: test_lleqsll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lleqsll_sext_z(i64 %a) { +; CHECK-LABEL: test_lleqsll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind +define void @test_lleqsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_lleqsll_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_lleqsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_lleqsll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_lleqsll_z_store(i64 %a) { +; CHECK-LABEL: test_lleqsll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_lleqsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_lleqsll_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesllequll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesllequll.ll @@ -0,0 +1,133 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llequll(i64 %a, i64 %b) { +; CHECK-LABEL: test_llequll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llequll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llequll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llequll_z(i64 %a) { +; CHECK-LABEL: test_llequll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llequll_sext_z(i64 %a) { +; CHECK-LABEL: test_llequll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind +define void @test_llequll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llequll_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llequll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llequll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llequll_z_store(i64 %a) { +; CHECK-LABEL: test_llequll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llequll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llequll_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r3, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp eq i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesllgesll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesllgesll.ll @@ -0,0 +1,128 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i64 0, align 8 + +define i64 @test_llgesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgesll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r5, r3, 63 +; CHECK-NEXT: rldicl r6, r4, 1, 63 +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llgesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgesll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r5, r3, 63 +; CHECK-NEXT: rldicl r6, r4, 1, 63 +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llgesll_z(i64 %a) { +; CHECK-LABEL: test_llgesll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llgesll_sext_z(i64 %a) { +; CHECK-LABEL: test_llgesll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: not r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define void @test_llgesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgesll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi r6, r3, 63 +; CHECK: subfc r3, r4, r3 +; CHECK: rldicl r3, r4, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3, +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llgesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgesll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r6, r3, 63 +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: rldicl r3, r4, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: adde r3, r6, r3 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llgesll_z_store(i64 %a) { +; CHECK-LABEL: test_llgesll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llgesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llgesll_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: not r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesllgeull.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesllgeull.ll @@ -0,0 +1,110 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llgeull: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeull_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull_sext_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeull_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_llgeull_store: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK: addi {{r[0-9]+}}, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llgeull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_z_store(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llgeull_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: std [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_sext_z_store(i64 %a) { +entry: + store i64 -1, i64* @glob + ret void +; CHECK-LABEL: @test_llgeull_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: std [[REG1]] +; CHECK: blr +} + Index: test/CodeGen/PowerPC/testComparesllgtsll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesllgtsll.ll @@ -0,0 +1,134 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; FIXME +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll_z(i64 %a) { +; CHECK-LABEL: test_llgtsll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: nor r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll_sext_z(i64 %a) { +; CHECK-LABEL: test_llgtsll_sext_z: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK-NEXT: sradi r3, [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind +define void @test_llgtsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; FIXME +; Function Attrs: norecurse nounwind +define void @test_llgtsll_z_store(i64 %a) { +; CHECK-LABEL: test_llgtsll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: nor r3, r5, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llgtsll_sext_z_store: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesllgtull.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesllgtull.ll @@ -0,0 +1,124 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtull(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtull: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtull_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtull_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: subfe r3, [[REG2:r[0-9]+]], [[REG2]] +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtull_z(i64 %a) { +; CHECK-LABEL: test_llgtull_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtull_sext_z(i64 %a) { +; CHECK-LABEL: test_llgtull_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind +define void @test_llgtull_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtull_store: +; CHECK: # BB#0: # %entry +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NEXT: neg {{r[0-9]+}}, [[REG2]] +entry: + %cmp = icmp ugt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtull_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtull_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NOT: neg +entry: + %cmp = icmp ugt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtull_z_store(i64 %a) { +; CHECK-LABEL: test_llgtull_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtull_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llgtull_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + Index: test/CodeGen/PowerPC/testCompareslllesll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testCompareslllesll.ll @@ -0,0 +1,138 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lllesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_lllesll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r5, r4, 63 +; CHECK-NEXT: rldicl r6, r3, 1, 63 +; CHECK-NEXT: subfc r12, r3, r4 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lllesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_lllesll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r5, r4, 63 +; CHECK-NEXT: rldicl r6, r3, 1, 63 +; CHECK-NEXT: subfc r12, r3, r4 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lllesll_z(i64 %a) { +; CHECK-LABEL: test_lllesll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: or r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lllesll_sext_z(i64 %a) { +; CHECK-LABEL: test_lllesll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: or r3, r4, r3 +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind +define void @test_lllesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_lllesll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi r6, r4, 63 +; CHECK: subfc r4, r3, r4 +; CHECK: rldicl r3, r3, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3, +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_lllesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_lllesll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi r6, r4, 63 +; CHECK-DAG: rldicl r3, r3, 1, 63 +; CHECK-DAG: subfc r4, r3, r4 +; CHECK: adde r3, r6, r3 +; CHECK: neg r3, r3 +; CHECK: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_lllesll_z_store(i64 %a) { +; CHECK-LABEL: test_lllesll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: or r3, r5, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_lllesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_lllesll_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: or r3, r5, r3 +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesllleull.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesllleull.ll @@ -0,0 +1,115 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llleull: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llleull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llleull_z +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull_sext_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llleull_sext_z +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe r3, [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_llleull_store: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llleull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_llleull_z_store: +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_sext_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llleull_sext_z_store +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: std [[REG2]] +; CHECK: blr +} + Index: test/CodeGen/PowerPC/testComparesllltsll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesllltsll.ll @@ -0,0 +1,99 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltsll_sext_z(i64 %a) { +; CHECK-LABEL: test_llltsll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 0 + %sub = sext i1 %cmp to i64 + ret i64 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_llltsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llltsll_sext_z_store: +; CHECK: sradi r3, r3, 63 +entry: + %cmp = icmp slt i64 %a, 0 + %sub = sext i1 %cmp to i64 + store i64 %sub, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesllltull.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesllltull.ll @@ -0,0 +1,108 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltull(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltull: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfc [[REG:r[1-9]+]], r4, r3 +; CHECK-NEXT: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltull_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltull_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfc [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: subfe r3, [[REG2:r[0-9]+]], [[REG2]] +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltull_z(i64 %a) { +; CHECK-LABEL: test_llltull_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: li r3, 0 +; CHECK-NEXT: blr +entry: + ret i64 0 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltull_sext_z(i64 %a) { +; CHECK-LABEL: test_llltull_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: li r3, 0 +; CHECK-NEXT: blr +entry: + ret i64 0 +} + +; Function Attrs: norecurse nounwind +define void @test_llltull_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltull_store: +; CHECK: # BB#0: # %entry +; CHECK: subfc [[REG:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NEXT: neg {{r[0-9]+}}, [[REG2]] +entry: + %cmp = icmp ult i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltull_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltull_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: subfc [[REG:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]] +; CHECK-NOT: neg +entry: + %cmp = icmp ult i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltull_z_store(i64 %a) { +; CHECK-LABEL: test_llltull_z_store: +; CHECK: # BB#0: # %entry +; CHECK: li [[REG:r[0-9]+]], 0 +; CHECK: std [[REG]], 0(r3) +; CHECK-NEXT: blr +entry: + store i64 0, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltull_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llltull_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK: li [[REG:r[0-9]+]], 0 +; CHECK: std [[REG]], 0(r3) +; CHECK-NEXT: blr +entry: + store i64 0, i64* @glob, align 8 + ret void +} + Index: test/CodeGen/PowerPC/testComparesllnesll.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesllnesll.ll @@ -0,0 +1,125 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +define i64 @test_llnesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_llnesll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llnesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llnesll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llnesll_z(i64 %a) { +; CHECK-LABEL: test_llnesll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llnesll_sext_z(i64 %a) { +; CHECK-LABEL: test_llnesll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define void @test_llnesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llnesll_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llnesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llnesll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llnesll_z_store(i64 %a) { +; CHECK-LABEL: test_llnesll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llnesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llnesll_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} Index: test/CodeGen/PowerPC/testComparesllneull.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/testComparesllneull.ll @@ -0,0 +1,125 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +define i64 @test_llneull(i64 %a, i64 %b) { +; CHECK-LABEL: test_llneull: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llneull_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llneull_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llneull_z(i64 %a) { +; CHECK-LABEL: test_llneull_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llneull_sext_z(i64 %a) { +; CHECK-LABEL: test_llneull_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define void @test_llneull_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llneull_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llneull_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llneull_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llneull_z_store(i64 %a) { +; CHECK-LABEL: test_llneull_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llneull_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llneull_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +}