Index: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td @@ -3893,6 +3893,7 @@ let Inst{11-0} = imm; } +let AddedComplexity = 1 in def : ARMPat<(and GPR:$src, mod_imm_not:$imm), (BICri GPR:$src, mod_imm_not:$imm)>; Index: llvm/trunk/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll +++ llvm/trunk/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll @@ -19,7 +19,7 @@ call void @llvm.va_start(i8* %g1) ; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7 -; CHECK: bfc [[REG]], #0, #3 +; CHECK: bic [[REG]], [[REG]], #7 %0 = va_arg i8** %g, double call void @llvm.va_end(i8* %g1) Index: llvm/trunk/test/CodeGen/ARM/bfi.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/bfi.ll +++ llvm/trunk/test/CodeGen/ARM/bfi.ll @@ -77,7 +77,7 @@ define i32 @f7(i32 %x, i32 %y) { ; CHECK-LABEL: f7: -; CHECK: bfi r1, r0, #4, #1 +; CHECK: bfi r0, r2, #4, #1 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 %and = and i32 %x, 4 %or = or i32 %y2, 16 @@ -88,8 +88,8 @@ define i32 @f8(i32 %x, i32 %y) { ; CHECK-LABEL: f8: -; CHECK: bfi r1, r0, #4, #1 -; CHECK: bfi r1, r0, #5, #1 +; CHECK: bfi r0, r2, #4, #1 +; CHECK: bfi r0, r2, #5, #1 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 %and = and i32 %x, 4 %or = or i32 %y2, 48 @@ -111,7 +111,7 @@ define i32 @f10(i32 %x, i32 %y) { ; CHECK-LABEL: f10: -; CHECK: bfi r1, r0, #4, #2 +; CHECK: bfi r0, r2, #4, #2 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 %and = and i32 %x, 4 %or = or i32 %y2, 32 @@ -128,7 +128,7 @@ define i32 @f11(i32 %x, i32 %y) { ; CHECK-LABEL: f11: -; CHECK: bfi r1, r0, #4, #3 +; CHECK: bfi r0, r2, #4, #3 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 %and = and i32 %x, 4 %or = or i32 %y2, 32 @@ -150,7 +150,7 @@ define i32 @f12(i32 %x, i32 %y) { ; CHECK-LABEL: f12: -; CHECK: bfi r1, r0, #4, #1 +; CHECK: bfi r0, r2, #4, #1 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 %and = and i32 %x, 4 %or = or i32 %y2, 16 Index: llvm/trunk/test/CodeGen/ARM/bic.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/bic.ll +++ llvm/trunk/test/CodeGen/ARM/bic.ll @@ -1,17 +1,24 @@ ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @f1(i32 %a, i32 %b) { +; CHECK-LABEL: f1: +; CHECK: bic r0, r0, r1 %tmp = xor i32 %b, 4294967295 %tmp1 = and i32 %a, %tmp ret i32 %tmp1 } -; CHECK: bic r0, r0, r1 - define i32 @f2(i32 %a, i32 %b) { +; CHECK-LABEL: f2: +; CHECK: bic r0, r0, r1 %tmp = xor i32 %b, 4294967295 %tmp1 = and i32 %tmp, %a ret i32 %tmp1 } -; CHECK: bic r0, r0, r1 +define i32 @f3(i32 %a) { +; CHECK-LABEL: f3: +; CHECK: bic r0, r0, #255 + %tmp = and i32 %a, -256 + ret i32 %tmp +} Index: llvm/trunk/test/CodeGen/ARM/fp16-promote.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/fp16-promote.ll +++ llvm/trunk/test/CodeGen/ARM/fp16-promote.ll @@ -597,7 +597,7 @@ ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_fabs: ; CHECK-LIBCALL: bl __aeabi_h2f -; CHECK-LIBCALL: bfc +; CHECK-LIBCALL: bic ; CHECK-LIBCALL: bl __aeabi_f2h define void @test_fabs(half* %p) { %a = load half, half* %p, align 2 @@ -687,7 +687,7 @@ ; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-VFP-LIBCALL: vbsl -; CHECK-NOVFP: bfc +; CHECK-NOVFP: bic ; CHECK-NOVFP: and ; CHECK-NOVFP: orr ; CHECK-LIBCALL: bl __aeabi_f2h Index: llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll +++ llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll @@ -35,7 +35,7 @@ ; CHECK-NOT: vldr ; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0] ; CHECK-NOT: b LBB -; CHECK: bfc [[REG2]], #31, #1 +; CHECK: bic [[REG2]], [[REG2]], #-2147483648 ; CHECK: cmp [[REG1]], #0 ; CHECK: cmpeq [[REG2]], #0 ; CHECK-NOT: vcmp.f32 Index: llvm/trunk/test/CodeGen/ARM/softfp-fabs-fneg.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/softfp-fabs-fneg.ll +++ llvm/trunk/test/CodeGen/ARM/softfp-fabs-fneg.ll @@ -14,8 +14,7 @@ define float @g(float %a) { ; CHECK-LABEL: g: - ; CHECK-THUMB: bic r0, r0, #-2147483648 - ; CHECK-ARM: bfc r0, #31, #1 + ; CHECK: bic r0, r0, #-2147483648 ; CHECK-NEXT: bx lr %x = call float @llvm.fabs.f32(float %a) readnone ret float %x Index: llvm/trunk/test/CodeGen/ARM/va_arg.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/va_arg.ll +++ llvm/trunk/test/CodeGen/ARM/va_arg.ll @@ -4,8 +4,8 @@ ; CHECK-LABEL: test1: ; CHECK-NOT: bfc ; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7 -; CHECK: bfc [[REG]], #0, #3 -; CHECK-NOT: bfc +; CHECK: bic {{(r[0-9]+)|(lr)}}, [[REG]], #7 +; CHECK-NOT: bic define i64 @test1(i32 %i, ...) nounwind optsize { entry: @@ -20,8 +20,8 @@ ; CHECK-LABEL: test2: ; CHECK-NOT: bfc ; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7 -; CHECK: bfc [[REG]], #0, #3 -; CHECK-NOT: bfc +; CHECK: bic {{(r[0-9]+)|(lr)}}, [[REG]], #7 +; CHECK-NOT: bic ; CHECK: bx lr define double @test2(i32 %a, i32* %b, ...) nounwind optsize {