Index: lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- lib/Target/AArch64/AArch64ISelLowering.cpp +++ lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4510,7 +4510,12 @@ SelectionDAG &DAG) const { unsigned Reg = StringSwitch(RegName) .Case("sp", AArch64::SP) + .Case("x18", AArch64::X18) + .Case("w18", AArch64::W18) .Default(0); + if ((Reg == AArch64::X18 || Reg == AArch64::W18) && + !Subtarget->isX18Reserved()) + Reg = 0; if (Reg) return Reg; report_fatal_error(Twine("Invalid register name \"" Index: test/CodeGen/AArch64/aarch64-named-reg-w18.ll =================================================================== --- /dev/null +++ test/CodeGen/AArch64/aarch64-named-reg-w18.ll @@ -0,0 +1,14 @@ +; RUN: not llc -mtriple=aarch64-fuchsia -o - %s 2>&1 | FileCheck %s --check-prefix=ERROR +; RUN: llc -mtriple=aarch64-fuchsia -mattr=+reserve-x18 -o - %s + +define void @set_w18(i32 %x) { +entry: +; FIXME: Include an allocatable-specific error message +; ERROR: Invalid register name "w18". + tail call void @llvm.write_register.i32(metadata !0, i32 %x) + ret void +} + +declare void @llvm.write_register.i32(metadata, i32) nounwind + +!0 = !{!"w18"} Index: test/CodeGen/AArch64/aarch64-named-reg-x18.ll =================================================================== --- /dev/null +++ test/CodeGen/AArch64/aarch64-named-reg-x18.ll @@ -0,0 +1,14 @@ +; RUN: not llc -mtriple=aarch64-fuchsia -o - %s 2>&1 | FileCheck %s --check-prefix=ERROR +; RUN: llc -mtriple=aarch64-fuchsia -mattr=+reserve-x18 -o - %s + +define void @set_x18(i64 %x) { +entry: +; FIXME: Include an allocatable-specific error message +; ERROR: Invalid register name "x18". + tail call void @llvm.write_register.i64(metadata !0, i64 %x) + ret void +} + +declare void @llvm.write_register.i64(metadata, i64) nounwind + +!0 = !{!"x18"}