Index: lib/Analysis/AliasAnalysis.cpp
===================================================================
--- lib/Analysis/AliasAnalysis.cpp
+++ lib/Analysis/AliasAnalysis.cpp
@@ -332,8 +332,8 @@
 
 ModRefInfo AAResults::getModRefInfo(const LoadInst *L,
                                     const MemoryLocation &Loc) {
-  // Be conservative in the face of volatile/atomic.
-  if (!L->isUnordered())
+  // Be conservative in the face of atomic.
+  if (isStrongerThan(L->getOrdering(), AtomicOrdering::Unordered))
     return MRI_ModRef;
 
   // If the load address doesn't alias the given address, it doesn't read
@@ -347,8 +347,8 @@
 
 ModRefInfo AAResults::getModRefInfo(const StoreInst *S,
                                     const MemoryLocation &Loc) {
-  // Be conservative in the face of volatile/atomic.
-  if (!S->isUnordered())
+    // Be conservative in the face of atomic.
+  if (isStrongerThan(S->getOrdering(), AtomicOrdering::Unordered))
     return MRI_ModRef;
 
   if (Loc.Ptr) {
Index: test/Transforms/NewGVN/volatile-nonvolatile.ll
===================================================================
--- test/Transforms/NewGVN/volatile-nonvolatile.ll
+++ test/Transforms/NewGVN/volatile-nonvolatile.ll
@@ -1,4 +1,3 @@
-; XFAIL: *
 ; RUN: opt -tbaa -newgvn -S < %s | FileCheck %s
 
 %struct.t = type { i32* }
Index: test/Transforms/Util/MemorySSA/many-dom-backedge.ll
===================================================================
--- test/Transforms/Util/MemorySSA/many-dom-backedge.ll
+++ test/Transforms/Util/MemorySSA/many-dom-backedge.ll
@@ -11,7 +11,7 @@
   br label %loopbegin
 
 loopbegin:
-; CHECK: 8 = MemoryPhi({entry,liveOnEntry},{sw.epilog,6})
+; CHECK: 6 = MemoryPhi({entry,liveOnEntry},{sw.epilog,8})
 ; CHECK-NEXT: %n =
   %n = phi i32 [ 0, %entry ], [ %1, %sw.epilog ]
   %m = alloca i32, align 4
@@ -23,42 +23,42 @@
   ]
 
 sw.bb:
-; CHECK: 1 = MemoryDef(8)
+; CHECK: 1 = MemoryDef(6)
 ; CHECK-NEXT: store i32 1
   store i32 1, i32* %m, align 4
   br label %sw.epilog
 
 sw.bb1:
-; CHECK: 2 = MemoryDef(8)
+; CHECK: 2 = MemoryDef(6)
 ; CHECK-NEXT: store i32 2
   store i32 2, i32* %m, align 4
   br label %sw.epilog
 
 sw.bb2:
-; CHECK: 3 = MemoryDef(8)
+; CHECK: 3 = MemoryDef(6)
 ; CHECK-NEXT: store i32 3
   store i32 3, i32* %m, align 4
   br label %sw.epilog
 
 sw.bb3:
-; CHECK: 9 = MemoryPhi({loopbegin,8},{sw.almostexit,6})
-; CHECK: 4 = MemoryDef(9)
+; CHECK: 7 = MemoryPhi({loopbegin,6},{sw.almostexit,8})
+; CHECK: 4 = MemoryDef(7)
 ; CHECK-NEXT: store i32 4
   store i32 4, i32* %m, align 4
   br label %sw.epilog
 
 sw.default:
-; CHECK: 5 = MemoryDef(8)
+; CHECK: 5 = MemoryDef(6)
 ; CHECK-NEXT: store i32 5
   store i32 5, i32* %m, align 4
   br label %sw.epilog
 
 sw.epilog:
-; CHECK: 10 = MemoryPhi({sw.default,5},{sw.bb3,4},{sw.bb,1},{sw.bb1,2},{sw.bb2,3})
-; CHECK-NEXT: MemoryUse(10)
+; CHECK: 8 = MemoryPhi({sw.default,5},{sw.bb3,4},{sw.bb,1},{sw.bb1,2},{sw.bb2,3})
+; CHECK-NEXT: MemoryUse(8)
 ; CHECK-NEXT: %0 =
   %0 = load i32, i32* %m, align 4
-; CHECK: 6 = MemoryDef(10)
+; CHECK: MemoryUse(liveOnEntry)
 ; CHECK-NEXT: %1 =
   %1 = load volatile i32, i32* %p, align 4
   %2 = icmp eq i32 %0, %1
@@ -69,7 +69,7 @@
   br i1 %3, label %exit, label %sw.bb3
 
 exit:
-; CHECK: 7 = MemoryDef(6)
+; CHECK: MemoryUse(liveOnEntry)
 ; CHECK-NEXT: %4 = load volatile i32
   %4 = load volatile i32, i32* %p, align 4
   %5 = add i32 %4, %1
Index: test/Transforms/Util/MemorySSA/many-doms.ll
===================================================================
--- test/Transforms/Util/MemorySSA/many-doms.ll
+++ test/Transforms/Util/MemorySSA/many-doms.ll
@@ -10,7 +10,7 @@
   br label %loopbegin
 
 loopbegin:
-; CHECK: 7 = MemoryPhi({entry,liveOnEntry},{sw.epilog,6})
+; CHECK: 6 = MemoryPhi({entry,liveOnEntry},{sw.epilog,7})
 ; CHECK-NEXT: %n =
   %n = phi i32 [ 0, %entry ], [ %1, %sw.epilog ]
   %m = alloca i32, align 4
@@ -22,41 +22,41 @@
   ]
 
 sw.bb:
-; CHECK: 1 = MemoryDef(7)
+; CHECK: 1 = MemoryDef(6)
 ; CHECK-NEXT: store i32 1
   store i32 1, i32* %m, align 4
   br label %sw.epilog
 
 sw.bb1:
-; CHECK: 2 = MemoryDef(7)
+; CHECK: 2 = MemoryDef(6)
 ; CHECK-NEXT: store i32 2
   store i32 2, i32* %m, align 4
   br label %sw.epilog
 
 sw.bb2:
-; CHECK: 3 = MemoryDef(7)
+; CHECK: 3 = MemoryDef(6)
 ; CHECK-NEXT: store i32 3
   store i32 3, i32* %m, align 4
   br label %sw.epilog
 
 sw.bb3:
-; CHECK: 4 = MemoryDef(7)
+; CHECK: 4 = MemoryDef(6)
 ; CHECK-NEXT: store i32 4
   store i32 4, i32* %m, align 4
   br label %sw.epilog
 
 sw.default:
-; CHECK: 5 = MemoryDef(7)
+; CHECK: 5 = MemoryDef(6)
 ; CHECK-NEXT: store i32 5
   store i32 5, i32* %m, align 4
   br label %sw.epilog
 
 sw.epilog:
-; CHECK: 8 = MemoryPhi({sw.default,5},{sw.bb,1},{sw.bb1,2},{sw.bb2,3},{sw.bb3,4})
-; CHECK-NEXT: MemoryUse(8)
+; CHECK: 7 = MemoryPhi({sw.default,5},{sw.bb,1},{sw.bb1,2},{sw.bb2,3},{sw.bb3,4})
+; CHECK-NEXT: MemoryUse(7)
 ; CHECK-NEXT: %0 =
   %0 = load i32, i32* %m, align 4
-; CHECK: 6 = MemoryDef(8)
+; CHECK: MemoryUse(liveOnEntry)
 ; CHECK-NEXT: %1 =
   %1 = load volatile i32, i32* %p, align 4
   %2 = icmp eq i32 %0, %1
Index: test/Transforms/Util/MemorySSA/volatile-clobber.ll
===================================================================
--- test/Transforms/Util/MemorySSA/volatile-clobber.ll
+++ test/Transforms/Util/MemorySSA/volatile-clobber.ll
@@ -1,7 +1,7 @@
 ; RUN: opt -basicaa -print-memoryssa -verify-memoryssa -analyze < %s 2>&1 | FileCheck %s
 ; RUN: opt -aa-pipeline=basic-aa -passes='print<memoryssa>,verify<memoryssa>' -disable-output < %s 2>&1 | FileCheck %s
 ;
-; Ensures that volatile stores/loads count as MemoryDefs
+; Ensures that volatile stores/loads do not count as MemoryDefs just because they are volatile.
 
 ; CHECK-LABEL: define i32 @foo
 define i32 @foo() {
@@ -12,39 +12,40 @@
 ; CHECK: 2 = MemoryDef(1)
 ; CHECK-NEXT: store volatile i32 8
   store volatile i32 8, i32* %1, align 4
-; CHECK: 3 = MemoryDef(2)
+; CHECK: MemoryUse(2)
 ; CHECK-NEXT: %2 = load volatile i32
   %2 = load volatile i32, i32* %1, align 4
-; CHECK: 4 = MemoryDef(3)
+; CHECK: MemoryUse(2)
 ; CHECK-NEXT: %3 = load volatile i32
   %3 = load volatile i32, i32* %1, align 4
   %4 = add i32 %3, %2
   ret i32 %4
 }
 
-; Ensuring that we don't automatically hoist nonvolatile loads around volatile
-; loads
+; Ensuring that we can see past volatile loads
+; MemorySSA does not try to ensure ordering
+; only aliasing.
 ; CHECK-LABEL define void @volatile_only
 define void @volatile_only(i32* %arg1, i32* %arg2) {
   ; Trivially NoAlias/MustAlias
   %a = alloca i32
   %b = alloca i32
 
-; CHECK: 1 = MemoryDef(liveOnEntry)
+; CHECK: MemoryUse(liveOnEntry)
 ; CHECK-NEXT: load volatile i32, i32* %a
   load volatile i32, i32* %a
 ; CHECK: MemoryUse(liveOnEntry)
 ; CHECK-NEXT: load i32, i32* %b
   load i32, i32* %b
-; CHECK: MemoryUse(1)
+; CHECK: MemoryUse(liveOnEntry)
 ; CHECK-NEXT: load i32, i32* %a
   load i32, i32* %a
 
   ; MayAlias
-; CHECK: 2 = MemoryDef(1)
+; CHECK: MemoryUse(liveOnEntry)
 ; CHECK-NEXT: load volatile i32, i32* %arg1
   load volatile i32, i32* %arg1
-; CHECK: MemoryUse(2)
+; CHECK: MemoryUse(liveOnEntry)
 ; CHECK-NEXT: load i32, i32* %arg2
   load i32, i32* %arg2