Index: lib/CodeGen/GlobalISel/LegalizerInfo.cpp =================================================================== --- lib/CodeGen/GlobalISel/LegalizerInfo.cpp +++ lib/CodeGen/GlobalISel/LegalizerInfo.cpp @@ -75,8 +75,11 @@ // Nothing is going to go well with types that aren't a power of 2 yet, so // don't even try because we might make things worse. - if (!isPowerOf2_64(Aspect.Type.getSizeInBits())) - return std::make_pair(Unsupported, LLT()); + LLT Ty = Aspect.Type; + unsigned SizeInBits = + Ty.isVector() ? Ty.getElementType().getSizeInBits() : Ty.getSizeInBits(); + if (!isPowerOf2_64(SizeInBits)) + return std::make_pair(Unsupported, LLT()); // FIXME: the long-term plan calls for expansion in terms of load/store (if // they're not legal). @@ -91,7 +94,6 @@ return findLegalAction(Aspect, Action); unsigned Opcode = Aspect.Opcode; - LLT Ty = Aspect.Type; if (!Ty.isVector()) { auto DefaultAction = DefaultActions.find(Aspect.Opcode); if (DefaultAction != DefaultActions.end() && DefaultAction->second == Legal) Index: test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir =================================================================== --- /dev/null +++ test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir @@ -0,0 +1,29 @@ +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + target triple = "aarch64--" + define void @test_legalize_merge_v3s32() { + ret void + } +... +--- +name: test_legalize_merge_v3s32 +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %w0, %w1, %w2 + ; CHECK-LABEL: name: test_legalize_merge_v3s32 + ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %w1 + ; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %w2 + ; CHECK: (<3 x s32>) = G_MERGE_VALUES [[ARG1]](s32), [[ARG2]](s32), [[ARG3]](s32) + %0(s32) = COPY %w0 + %1(s32) = COPY %w1 + %2(s32) = COPY %w2 + %3(<3 x s32>) = G_MERGE_VALUES %0(s32), %1(s32), %2(s32) +...