Index: llvm/trunk/lib/Target/AMDGPU/DSInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/DSInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/DSInstructions.td @@ -203,20 +203,28 @@ let has_data1 = 0; } -class DS_1A_GDS : DS_Pseudo { +class DS_GWS +: DS_Pseudo { - let has_vdst = 0; - let has_data0 = 0; - let has_data1 = 0; - let has_offset = 0; - let has_offset0 = 0; - let has_offset1 = 0; + let has_vdst = 0; + let has_addr = 0; + let has_data0 = 0; + let has_data1 = 0; - let has_gds = 0; - let gdsValue = 1; + let has_gds = 0; + let gdsValue = 1; + let AsmMatchConverter = "cvtDSGds"; +} + +class DS_GWS_0D +: DS_GWS; + +class DS_GWS_1D +: DS_GWS { + + let has_data0 = 1; } class DS_VOID : DS_Pseudo, AtomicNoRet<"ds_wrxchg2st64_b64", 1>; -def DS_GWS_INIT : DS_1A_GDS<"ds_gws_init">; -def DS_GWS_SEMA_V : DS_1A_GDS<"ds_gws_sema_v">; -def DS_GWS_SEMA_BR : DS_1A_GDS<"ds_gws_sema_br">; -def DS_GWS_SEMA_P : DS_1A_GDS<"ds_gws_sema_p">; -def DS_GWS_BARRIER : DS_1A_GDS<"ds_gws_barrier">; +def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">; +def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">; +def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">; +def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">; +def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">; def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">; def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">; @@ -405,7 +413,7 @@ def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">; def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">; def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">; -def DS_AND_SRC2_B32 : DS_1A<"ds_and_src_b32">; +def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">; def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">; def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">; def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">; @@ -448,25 +456,22 @@ def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>; } -let SubtargetPredicate = isSICI in { def DS_CONSUME : DS_0A_RET<"ds_consume">; def DS_APPEND : DS_0A_RET<"ds_append">; def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">; -} //===----------------------------------------------------------------------===// // Instruction definitions for CI and newer. //===----------------------------------------------------------------------===// -// Remaining instructions: -// DS_GWS_SEMA_RELEASE_ALL -// DS_WRAP_RTN_B32 -// DS_CNDXCHG32_RTN_B64 -// DS_CONDXCHG32_RTN_B128 let SubtargetPredicate = isCIVI in { -def DS_WRAP_RTN_F32 : DS_1A1D_RET <"ds_wrap_rtn_f32">, - AtomicNoRet<"ds_wrap_f32", 1>; +def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>; + +def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>, + AtomicNoRet<"", 1>; + +def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">; let mayStore = 0 in { def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>; @@ -678,8 +683,10 @@ def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>; def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>; -// FIXME: this instruction is actually CI/VI -def DS_WRAP_RTN_F32_si : DS_Real_si<0x34, DS_WRAP_RTN_F32>; +// These instruction are CI/VI only +def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>; +def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>; +def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>; def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>; def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>; @@ -820,11 +827,11 @@ def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>; def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>; def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>; -def DS_GWS_INIT_vi : DS_Real_vi<0x19, DS_GWS_INIT>; -def DS_GWS_SEMA_V_vi : DS_Real_vi<0x1a, DS_GWS_SEMA_V>; -def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>; -def DS_GWS_SEMA_P_vi : DS_Real_vi<0x1c, DS_GWS_SEMA_P>; -def DS_GWS_BARRIER_vi : DS_Real_vi<0x1d, DS_GWS_BARRIER>; +def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>; +def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>; +def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>; +def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>; +def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>; def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>; def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>; def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>; @@ -847,7 +854,7 @@ def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>; def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>; def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>; -def DS_WRAP_RTN_F32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_F32>; +def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>; def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>; def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>; def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>; @@ -856,6 +863,9 @@ def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>; def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>; def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>; +def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>; +def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>; +def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>; def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>; def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>; def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>; @@ -897,6 +907,8 @@ def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>; def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>; def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>; +def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>; +def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>; def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>; def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>; def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>; Index: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp +++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp @@ -113,7 +113,7 @@ raw_ostream &O) { uint16_t Imm = MI->getOperand(OpNo).getImm(); if (Imm != 0) { - O << " offset:"; + O << ((OpNo == 0)? "offset:" : " offset:"); printU16ImmDecOperand(MI, OpNo, O); } } Index: llvm/trunk/test/MC/AMDGPU/ds.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/ds.s +++ llvm/trunk/test/MC/AMDGPU/ds.s @@ -140,24 +140,32 @@ // VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00] ds_gws_init v2 gds -// SICI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x00,0x00,0x00] -// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00] +// SICI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x00,0x02,0x00,0x00] +// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00] -ds_gws_sema_v v2 gds -// SICI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x00] -// VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00] +ds_gws_init v3 offset:12345 gds +// SICI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x66,0xd8,0x00,0x03,0x00,0x00] +// VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x00,0x03,0x00,0x00] + +ds_gws_sema_v gds +// SICI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00] +// VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00] + +ds_gws_sema_v offset:257 gds +// SICI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x6a,0xd8,0x00,0x00,0x00,0x00] +// VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00] ds_gws_sema_br v2 gds -// SICI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x00] -// VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd8,0x02,0x00,0x00,0x00] +// SICI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x6e,0xd8,0x00,0x02,0x00,0x00] +// VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x00,0x02,0x00,0x00] -ds_gws_sema_p v2 gds -// SICI: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x72,0xd8,0x02,0x00,0x00,0x00] -// VI: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x39,0xd8,0x02,0x00,0x00,0x00] +ds_gws_sema_p gds +// SICI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00] +// VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00] ds_gws_barrier v2 gds -// SICI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x76,0xd8,0x02,0x00,0x00,0x00] -// VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd8,0x02,0x00,0x00,0x00] +// SICI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x76,0xd8,0x00,0x02,0x00,0x00] +// VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x00,0x02,0x00,0x00] ds_write_b8 v2, v4 // SICI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x04,0x00,0x00] @@ -284,17 +292,17 @@ // VI: ds_read_u16 v8, v2 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x00,0x00,0x08] -//ds_consume v8 -// FIXMESICI: ds_consume v8 ; encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x08] -// FIXMEVI: ds_consume v8 ; encoding: [0x00,0x00,0x7a,0xd8,0x00,0x00,0x00,0x08] - -//ds_append v8 -// FIXMESICI: ds_append v8 ; encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x08] -// FIXMEVI: ds_append v8 ; encoding: [0x00,0x00,0x7c,0xd8,0x00,0x00,0x00,0x08] - -//ds_ordered_count v8, v2 gds -// FIXMESICI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0xfe,0xd8,0x02,0x00,0x00,0x08] -// FIXMEVI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0x7f,0xd8,0x02,0x00,0x00,0x08] +ds_consume v8 +// SICI: ds_consume v8 ; encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x08] +// VI: ds_consume v8 ; encoding: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x08] + +ds_append v8 +// SICI: ds_append v8 ; encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x08] +// VI: ds_append v8 ; encoding: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x08] + +ds_ordered_count v8, v2 gds +// SICI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0xfe,0xd8,0x02,0x00,0x00,0x08] +// VI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0x7f,0xd9,0x02,0x00,0x00,0x08] ds_add_u64 v2, v[4:5] // SICI: ds_add_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x00,0xd9,0x02,0x04,0x00,0x00] Index: llvm/trunk/test/MC/AMDGPU/expressions.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/expressions.s +++ llvm/trunk/test/MC/AMDGPU/expressions.s @@ -11,7 +11,7 @@ // Use a token with the same name as a global ds_gws_init v2 gds -// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00] +// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00] // Use a global with the same name as a token s_mov_b32 s0, gds Index: llvm/trunk/test/MC/AMDGPU/gfx7_asm_all.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/gfx7_asm_all.s +++ llvm/trunk/test/MC/AMDGPU/gfx7_asm_all.s @@ -456,19 +456,25 @@ // CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0x00] ds_gws_init v1 gds -// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x00,0x00,0x00] +// CHECK: [0x00,0x00,0x66,0xd8,0x00,0x01,0x00,0x00] -ds_gws_sema_v v1 gds -// CHECK: [0x00,0x00,0x6a,0xd8,0x01,0x00,0x00,0x00] +ds_gws_sema_v gds +// CHECK: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00] ds_gws_sema_br v1 gds -// CHECK: [0x00,0x00,0x6e,0xd8,0x01,0x00,0x00,0x00] +// CHECK: [0x00,0x00,0x6e,0xd8,0x00,0x01,0x00,0x00] -ds_gws_sema_p v1 gds -// CHECK: [0x00,0x00,0x72,0xd8,0x01,0x00,0x00,0x00] +ds_gws_sema_p gds +// CHECK: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00] ds_gws_barrier v1 gds -// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x00] +// CHECK: [0x00,0x00,0x76,0xd8,0x00,0x01,0x00,0x00] + +ds_gws_sema_release_all offset:65535 gds +// CHECK: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00] + +ds_gws_sema_release_all gds +// CHECK: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00] ds_write_b8 v1, v2 offset:65535 // CHECK: [0xff,0xff,0x78,0xd8,0x01,0x02,0x00,0x00] @@ -2660,6 +2666,24 @@ ds_max_src2_f64 v1 offset:65535 gds // CHECK: [0xff,0xff,0x4e,0xdb,0x01,0x00,0x00,0x00] +ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535 +// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff] + +ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535 gds +// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x03,0xff] + +ds_wrap_rtn_b32 v255, v1, v2, v3 +// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x03,0xff] + +ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] +// CHECK: [0x00,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05] + +ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] gds +// CHECK: [0x00,0x00,0xfa,0xd9,0x01,0x02,0x00,0x05] + +ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535 +// CHECK: [0xff,0xff,0xf8,0xd9,0x01,0xfe,0x00,0x05] + exp mrt0, v0, v0, v0, v0 // CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] Index: llvm/trunk/test/MC/AMDGPU/gfx8_asm_all.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/gfx8_asm_all.s +++ llvm/trunk/test/MC/AMDGPU/gfx8_asm_all.s @@ -2678,6 +2678,90 @@ ds_max_src2_f64 v1 offset:65535 gds // CHECK: [0xff,0xff,0xa7,0xd9,0x01,0x00,0x00,0x00] +ds_and_src2_b32 v1 +// CHECK: [0x00,0x00,0x12,0xd9,0x01,0x00,0x00,0x00] + +ds_and_src2_b32 v1 gds +// CHECK: [0x00,0x00,0x13,0xd9,0x01,0x00,0x00,0x00] + +ds_and_src2_b32 v255 offset:65535 +// CHECK: [0xff,0xff,0x12,0xd9,0xff,0x00,0x00,0x00] + +ds_append v5 +// CHECK: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05] + +ds_append v5 gds +// CHECK: [0x00,0x00,0x7d,0xd9,0x00,0x00,0x00,0x05] + +ds_append v255 offset:65535 +// CHECK: [0xff,0xff,0x7c,0xd9,0x00,0x00,0x00,0xff] + +ds_consume v5 +// CHECK: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05] + +ds_consume v5 gds +// CHECK: [0x00,0x00,0x7b,0xd9,0x00,0x00,0x00,0x05] + +ds_consume v255 offset:65535 +// CHECK: [0xff,0xff,0x7a,0xd9,0x00,0x00,0x00,0xff] + +ds_ordered_count v5, v1 gds +// CHECK: [0x00,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05] + +ds_ordered_count v5, v255 offset:65535 gds +// CHECK: [0xff,0xff,0x7f,0xd9,0xff,0x00,0x00,0x05] + +ds_ordered_count v5, v255 gds +// CHECK: [0x00,0x00,0x7f,0xd9,0xff,0x00,0x00,0x05] + +ds_gws_barrier v1 gds +// CHECK: [0x00,0x00,0x3b,0xd9,0x00,0x01,0x00,0x00] + +ds_gws_barrier v255 offset:65535 gds +// CHECK: [0xff,0xff,0x3b,0xd9,0x00,0xff,0x00,0x00] + +ds_gws_init v1 gds +// CHECK: [0x00,0x00,0x33,0xd9,0x00,0x01,0x00,0x00] + +ds_gws_init v255 offset:65535 gds +// CHECK: [0xff,0xff,0x33,0xd9,0x00,0xff,0x00,0x00] + +ds_gws_sema_br v1 gds +// CHECK: [0x00,0x00,0x37,0xd9,0x00,0x01,0x00,0x00] + +ds_gws_sema_br v255 offset:65535 gds +// CHECK: [0xff,0xff,0x37,0xd9,0x00,0xff,0x00,0x00] + +ds_gws_sema_p offset:65535 gds +// CHECK: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00] + +ds_gws_sema_p gds +// CHECK: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00] + +ds_gws_sema_release_all offset:65535 gds +// CHECK: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00] + +ds_gws_sema_release_all gds +// CHECK: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00] + +ds_gws_sema_v offset:65535 gds +// CHECK: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00] + +ds_gws_sema_v gds +// CHECK: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00] + +ds_wrap_rtn_b32 v5, v255, v2, v3 gds +// CHECK: [0x00,0x00,0x69,0xd8,0xff,0x02,0x03,0x05] + +ds_wrap_rtn_b32 v5, v255, v2, v255 offset:65535 +// CHECK: [0xff,0xff,0x68,0xd8,0xff,0x02,0xff,0x05] + +ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535 gds +// CHECK: [0xff,0xff,0xfd,0xd8,0x01,0xfe,0x00,0x05] + +ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] +// CHECK: [0x00,0x00,0xfc,0xd8,0x01,0xfe,0x00,0x05] + exp mrt0, v0, v0, v0, v0 // CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] Index: llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt +++ llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt @@ -81,20 +81,26 @@ # VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00] 0x00 0x00 0x26 0xd8 0x02 0x04 0x00 0x00 -# VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00] -0x00 0x00 0x33 0xd8 0x02 0x00 0x00 0x00 +# VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00] +0x00 0x00 0x33 0xd9 0x00 0x02 0x00,0x00 -# VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00] -0x00 0x00 0x35 0xd8 0x02 0x00 0x00 0x00 +# VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x00,0x03,0x00,0x00] +0x39 0x30 0x33 0xd9 0x00 0x03 0x00 0x00 -# VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd8,0x02,0x00,0x00,0x00] -0x00 0x00 0x37 0xd8 0x02 0x00 0x00 0x00 +# VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00] +0x00 0x00 0x35 0xd9 0x00 0x00 0x00 0x00 -# VI: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x39,0xd8,0x02,0x00,0x00,0x00] -0x00 0x00 0x39 0xd8 0x02 0x00 0x00 0x00 +# VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00] +0x01 0x01 0x35 0xd9 0x00 0x00 0x00 0x00 -# VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd8,0x02,0x00,0x00,0x00] -0x00 0x00 0x3b 0xd8 0x02 0x00 0x00 0x00 +# VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x00,0x02,0x00,0x00] +0x00 0x00 0x37 0xd9 0x00 0x02 0x00 0x00 + +# VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00] +0x00 0x00 0x39 0xd9 0x00 0x00 0x00 0x00 + +# VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x00,0x02,0x00,0x00] +0x00 0x00 0x3b 0xd9 0x00 0x02 0x00 0x00 # VI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x3c,0xd8,0x02,0x04,0x00,0x00] 0x00 0x00 0x3c 0xd8 0x02 0x04 0x00 0x00