Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6968,12 +6968,11 @@
       SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, DL, VT, LN0->getChain(),
                                        LN0->getBasePtr(), N0.getValueType(),
                                        LN0->getMemOperand());
-      CombineTo(N, ExtLoad);
       SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
                                   N0.getValueType(), ExtLoad);
-      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
       ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL, ISD::SIGN_EXTEND);
-      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
+      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
+      return CombineTo(N, ExtLoad); // Return N so it doesn't get rechecked!
     }
   }
 
@@ -7285,12 +7284,9 @@
 
       SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
                                   N0.getValueType(), ExtLoad);
+      ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), ISD::ZERO_EXTEND);
       CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
-
-      ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
-                      ISD::ZERO_EXTEND);
-      CombineTo(N, ExtLoad);
-      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
+      return CombineTo(N, ExtLoad); // Return N so it doesn't get rechecked!
     }
   }
 
Index: lib/Target/ARM/ARMFeatures.h
===================================================================
--- lib/Target/ARM/ARMFeatures.h
+++ lib/Target/ARM/ARMFeatures.h
@@ -72,8 +72,13 @@
   case ARM::tSTRr:
   case ARM::tSTRspi:
   case ARM::tTST:
+  case ARM::t2MVNr:
+  case ARM::t2MVNi:
+  case ARM::t2MOVr:
+  case ARM::t2MOVi:
+  case ARM::t2MOVi16:
     return true;
-// there are some "conditionally deprecated" opcodes
+  // there are some "conditionally deprecated" opcodes
   case ARM::tADDspr:
   case ARM::tBLXr:
     return Instr->getOperand(2).getReg() != ARM::PC;
@@ -90,6 +95,9 @@
     return Instr->getOperand(0).getReg() != ARM::PC &&
            Instr->getOperand(1).getReg() != ARM::PC;
   }
+
+
+
 }
 
 }