Index: lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
===================================================================
--- lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
+++ lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
@@ -84,7 +84,7 @@
       return;
     }
   }
-  
+
   if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
     O << "\tmr ";
@@ -94,7 +94,7 @@
     printAnnotation(O, Annot);
     return;
   }
-  
+
   if (MI->getOpcode() == PPC::RLDICR ||
       MI->getOpcode() == PPC::RLDICR_32) {
     unsigned char SH = MI->getOperand(2).getImm();
@@ -161,7 +161,7 @@
       return;
     }
   }
-  
+
   if (!printAliasInstr(MI, O))
     printInstruction(MI, O);
   printAnnotation(O, Annot);
@@ -259,7 +259,7 @@
     }
     llvm_unreachable("Invalid predicate code");
   }
-  
+
   assert(StringRef(Modifier) == "reg" &&
          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
   printOperand(MI, OpNo+1, O);
@@ -448,9 +448,24 @@
 
 /// stripRegisterPrefix - This method strips the character prefix from a
 /// register name so that only the number is left.  Used by for linux asm.
-static const char *stripRegisterPrefix(const char *RegName) {
-  if (FullRegNames || ShowVSRNumsAsVR)
+static const char *stripRegisterPrefix(const char *RegName, unsigned RegNum,
+                                       unsigned RegEncoding) {
+  if (FullRegNames || ShowVSRNumsAsVR) {
+    if (RegNum >= PPC::CR0EQ && RegNum <= PPC::CR7UN) {
+      const char *CRBits[] =
+      { "lt", "gt", "eq", "un",
+        "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
+        "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
+        "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
+        "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
+        "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
+        "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
+        "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
+      };
+      return CRBits[RegEncoding];
+    }
     return RegName;
+  }
 
   switch (RegName[0]) {
   case 'r':
@@ -462,7 +477,7 @@
     return RegName + 1;
   case 'c': if (RegName[1] == 'r') return RegName + 2;
   }
-  
+
   return RegName;
 }
 
@@ -490,17 +505,17 @@
     const char *RegName = getRegisterName(Reg);
     // The linux and AIX assembler does not take register prefixes.
     if (!isDarwinSyntax())
-      RegName = stripRegisterPrefix(RegName);
-    
+      RegName = stripRegisterPrefix(RegName, Reg, MRI.getEncodingValue(Reg));
+
     O << RegName;
     return;
   }
-  
+
   if (Op.isImm()) {
     O << Op.getImm();
     return;
   }
-  
+
   assert(Op.isExpr() && "unknown operand kind in printOperand");
   Op.getExpr()->print(O, &MAI);
 }
Index: test/CodeGen/PowerPC/expand-contiguous-isel.ll
===================================================================
--- test/CodeGen/PowerPC/expand-contiguous-isel.ll
+++ test/CodeGen/PowerPC/expand-contiguous-isel.ll
@@ -122,7 +122,7 @@
 ; CHECK-LABEL: @_Z3fn1N4llvm9StringRefE
 ; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]]
 ; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]]
-; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK: bc 12, eq, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
 ; CHECK-NEXT: addi {{r[0-9]+}}, {{r[0-9]+}}, 0
Index: test/CodeGen/PowerPC/expand-isel.ll
===================================================================
--- test/CodeGen/PowerPC/expand-isel.ll
+++ test/CodeGen/PowerPC/expand-isel.ll
@@ -12,7 +12,7 @@
 ; CHECK-LABEL: @testExpandISELToIfElse
 ; CHECK: addi r5, r3, 1
 ; CHECK-NEXT: cmpwi cr0, r3, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
@@ -32,7 +32,7 @@
 
 ; CHECK-LABEL: @testExpandISELToIf
 ; CHECK: cmpwi	 r3, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: blr
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r3, r4, 0
@@ -48,7 +48,7 @@
 
 ; CHECK-LABEL: @testExpandISELToElse
 ; CHECK: cmpwi	 r3, 0
-; CHECK-NEXT: bclr 12, 1, 0
+; CHECK-NEXT: bclr 12, gt, 0
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: blr
 }
@@ -95,7 +95,7 @@
 
 ; CHECK-LABEL: @testExpandISELsTo2ORIs2ADDIs
 ; CHECK: cmpwi r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: ori r12, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
@@ -121,7 +121,7 @@
 
 ; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r3, r4, 0
 ; CHECK-NEXT: ori r12, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
@@ -148,7 +148,7 @@
 
 ; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK: ori r5, r6, 0
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
@@ -176,7 +176,7 @@
 
 ; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
 ; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r4, r3, 0
@@ -212,7 +212,7 @@
   ret i32 %retval.0
 
 ; CHECK-LABEL: @testComplexISEL
-; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK: bc 12, eq, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r3, r12, 0