Index: lib/Transforms/InstCombine/InstCombineCalls.cpp =================================================================== --- lib/Transforms/InstCombine/InstCombineCalls.cpp +++ lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -2389,10 +2389,30 @@ case Intrinsic::x86_avx512_mask_cmp_pd_512: case Intrinsic::x86_avx512_mask_cmp_ps_128: case Intrinsic::x86_avx512_mask_cmp_ps_256: - case Intrinsic::x86_avx512_mask_cmp_ps_512: + case Intrinsic::x86_avx512_mask_cmp_ps_512: { if(X86CreateCanonicalCMP(II)) return II; + // Folding cmp(sub(a,b),0) into cmp(a,b) + if (Instruction *I = dyn_cast(II->getArgOperand(0))) { + if (I->getOpcode() == Instruction::FSub && I->hasOneUse()) { + // This folding is not valid for safe algebra, + // but it doesn't require all of the fast flags + // (No NaNs,no inf,no sign zero) + if ((I->getFastMathFlags().unsafeAlgebra() || + (I->getFastMathFlags().noNaNs() && + I->getFastMathFlags().noInfs() && + I->getFastMathFlags().noSignedZeros())) && + isa((II->getArgOperand(1)))) { + Value *LHS = I->getOperand(0); + Value *RHS = I->getOperand(1); + II->setArgOperand(0, LHS); + II->setArgOperand(1, RHS); + return II; + } + } + } break; + } case Intrinsic::x86_avx512_mask_add_ps_512: case Intrinsic::x86_avx512_mask_div_ps_512: Index: test/Transforms/InstCombine/X86FsubCmpCombine.ll =================================================================== --- /dev/null +++ test/Transforms/InstCombine/X86FsubCmpCombine.ll @@ -0,0 +1,39 @@ + ; RUN: opt < %s -instcombine -S| FileCheck %s + +; The test checks the folding of cmp(sub(a,b),0) into cmp(a,b). + +define zeroext i16 @fucntionTets(<2 x double> %a, <4 x double> %b, <8 x double> %c, <4 x float> %d, <8 x float> %e, <16 x float> %f,<2 x double> %aa, <4 x double> %bb, <8 x double> %cc, <4 x float> %dd, <8 x float> %ee, <16 x float> %ff) local_unnamed_addr #0 { +entry: + %sub.i = fsub fast <2 x double> %a, %aa + %sub.i46 = fsub fast <4 x double> %b, %bb + %sub.i45 = fsub fast <8 x double> %c, %cc + %sub.i44 = fsub fast <4 x float> %d, %dd + %sub.i43 = fsub fast <8 x float> %e, %ee + %sub.i42 = fsub fast <16 x float> %f, %ff + ; CHECK: call i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %a, <2 x double> %aa, i32 5, i8 -1) + ; CHECK: call i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %b, <4 x double> %bb, i32 5, i8 -1) + ; CHECK: call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %c, <8 x double> %cc, i32 5, i8 -1, i32 4) + ; CHECK: call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %d, <4 x float> %dd, i32 5, i8 -1) + ; CHECK: call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %e, <8 x float> %ee, i32 5, i8 -1) + ; CHECK: call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %f, <16 x float> %ff, i32 5, i16 -1, i32 4) + %0 = tail call i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %sub.i, <2 x double> zeroinitializer, i32 5, i8 -1) + %1 = tail call i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %sub.i46, <4 x double> zeroinitializer, i32 5, i8 -1) + %2 = tail call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %sub.i45, <8 x double> zeroinitializer, i32 5, i8 -1, i32 4) + %3 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %sub.i44, <4 x float> zeroinitializer, i32 5, i8 -1) + %4 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %sub.i43, <8 x float> zeroinitializer, i32 5, i8 -1) + %5 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %sub.i42, <16 x float> zeroinitializer, i32 5, i16 -1, i32 4) + %and38 = and i8 %0, %1 + %and2039 = and i8 %and38, %2 + %and2240 = and i8 %and2039, %3 + %and2441 = and i8 %and2240, %4 + %conv27 = zext i8 %and2441 to i16 + %and28 = and i16 %5, %conv27 + ret i16 %and28 +} + +declare i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double>, <2 x double>, i32, i8) +declare i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double>, <4 x double>, i32, i8) +declare i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double>, <8 x double>, i32, i8, i32) +declare i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float>, <4 x float>, i32, i8) +declare i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float>, <8 x float>, i32, i8) +declare i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float>, <16 x float>, i32, i16, i32)