Index: include/llvm/CodeGen/GlobalISel/Utils.h
===================================================================
--- include/llvm/CodeGen/GlobalISel/Utils.h
+++ include/llvm/CodeGen/GlobalISel/Utils.h
@@ -23,6 +23,7 @@
 class MachineInstr;
 class MachineOptimizationRemarkEmitter;
 class MachineOptimizationRemarkMissed;
+class MachineOperand;
 class MachineRegisterInfo;
 class MCInstrDesc;
 class RegisterBankInfo;
@@ -60,5 +61,19 @@
                         const char *PassName, StringRef Msg,
                         const MachineInstr &MI);
 
+/// Check whether \p Opc is floating point opcode
+bool isFloatingPointOpc(unsigned Opc);
+
+/// Check whether \p MO is immediate (G_CONSTANT)
+bool isConstantOperand(const MachineOperand &MO,
+                       const MachineRegisterInfo &MRI);
+
+/// Returns the integer value of an Operand \p MO
+uint64_t getConstantVal(const MachineOperand &MO,
+                        const MachineRegisterInfo &MRI);
+
+/// Helper function to get integer value from \p MI at \p Idx
+uint64_t getConstantOperandVal(const MachineInstr &MI, unsigned Idx,
+                               const MachineRegisterInfo &MRI);
 } // End namespace llvm.
 #endif
Index: lib/CodeGen/GlobalISel/Utils.cpp
===================================================================
--- lib/CodeGen/GlobalISel/Utils.cpp
+++ lib/CodeGen/GlobalISel/Utils.cpp
@@ -18,6 +18,7 @@
 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/Constants.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 
@@ -93,3 +94,46 @@
   R << Msg << ": " << ore::MNV("Inst", MI);
   reportGISelFailure(MF, TPC, MORE, R);
 }
+
+bool llvm::isFloatingPointOpc(unsigned Opc) {
+  switch (Opc) {
+  case TargetOpcode::G_FADD:
+  case TargetOpcode::G_FCMP:
+  case TargetOpcode::G_FSUB:
+  case TargetOpcode::G_FDIV:
+  case TargetOpcode::G_FMUL:
+  case TargetOpcode::G_FPOW:
+  case TargetOpcode::G_FREM:
+  case TargetOpcode::G_FPEXT:
+  case TargetOpcode::G_UITOFP:
+  case TargetOpcode::G_SITOFP:
+  case TargetOpcode::G_FPTRUNC:
+  case TargetOpcode::G_FNEG:
+  case TargetOpcode::G_FCONSTANT:
+    return true;
+  default:
+    return false;
+  }
+}
+bool llvm::isConstantOperand(const MachineOperand &MO,
+                             const MachineRegisterInfo &MRI) {
+  if (!MO.isReg())
+    return false;
+  return MRI.def_begin(MO.getReg())->getParent()->getOpcode() ==
+         TargetOpcode::G_CONSTANT;
+}
+uint64_t llvm::getConstantVal(const MachineOperand &MO,
+                              const MachineRegisterInfo &MRI) {
+  assert(MO.isReg() && "Expecting a register");
+  auto DefMI = MRI.def_begin(MO.isReg())->getParent();
+  assert(TargetOpcode::G_CONSTANT == DefMI->getOpcode() &&
+         "Expecting a G_CONSTANT");
+  auto &CMO = DefMI->getOperand(1);
+  if (CMO.isImm())
+    return CMO.getImm();
+  return CMO.getCImm()->getZExtValue();
+}
+uint64_t llvm::getConstantOperandVal(const MachineInstr &MI, unsigned Idx,
+                                     const MachineRegisterInfo &MRI) {
+  return llvm::getConstantVal(MI.getOperand(Idx), MRI);
+}