Index: lib/Target/Mips/MipsSEISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsSEISelLowering.cpp +++ lib/Target/Mips/MipsSEISelLowering.cpp @@ -1547,11 +1547,24 @@ return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm); } +static SDValue truncateVecElts(SDValue Op, SelectionDAG &DAG) { + SDLoc DL(Op); + EVT ResTy = Op->getValueType(0); + SDValue Vec = Op->getOperand(2); + bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian(); + MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32; + SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1, + DL, ResEltTy); + SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG); + + return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec); +} + static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) { EVT ResTy = Op->getValueType(0); SDLoc DL(Op); SDValue One = DAG.getConstant(1, DL, ResTy); - SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2)); + SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG)); return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), DAG.getNOT(DL, Bit, ResTy)); @@ -1687,7 +1700,7 @@ return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1), DAG.getNode(ISD::SHL, DL, VecTy, One, - Op->getOperand(2))); + truncateVecElts(Op, DAG))); } case Intrinsic::mips_bnegi_b: case Intrinsic::mips_bnegi_h: @@ -1723,7 +1736,7 @@ return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1), DAG.getNode(ISD::SHL, DL, VecTy, One, - Op->getOperand(2))); + truncateVecElts(Op, DAG))); } case Intrinsic::mips_bseti_b: case Intrinsic::mips_bseti_h: @@ -2210,7 +2223,7 @@ case Intrinsic::mips_sll_w: case Intrinsic::mips_sll_d: return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), - Op->getOperand(2)); + truncateVecElts(Op, DAG)); case Intrinsic::mips_slli_b: case Intrinsic::mips_slli_h: case Intrinsic::mips_slli_w: @@ -2240,7 +2253,7 @@ case Intrinsic::mips_sra_w: case Intrinsic::mips_sra_d: return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), - Op->getOperand(2)); + truncateVecElts(Op, DAG)); case Intrinsic::mips_srai_b: case Intrinsic::mips_srai_h: case Intrinsic::mips_srai_w: @@ -2270,7 +2283,7 @@ case Intrinsic::mips_srl_w: case Intrinsic::mips_srl_d: return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), - Op->getOperand(2)); + truncateVecElts(Op, DAG)); case Intrinsic::mips_srli_b: case Intrinsic::mips_srli_h: case Intrinsic::mips_srli_w: Index: test/CodeGen/Mips/msa/3r-s.ll =================================================================== --- test/CodeGen/Mips/msa/3r-s.ll +++ test/CodeGen/Mips/msa/3r-s.ll @@ -132,12 +132,13 @@ declare <16 x i8> @llvm.mips.sll.b(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_sll_b_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_b_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_b_ARG2) -; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sll.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.b [[WD]] +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_b_ARG2) +; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK: andi.b [[WT:\$w[0-9]+]], [[R4]], 7 +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_b_ARG1) +; CHECK: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) +; CHECK: sll.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.b [[WD]] ; CHECK: .size llvm_mips_sll_b_test ; @llvm_mips_sll_h_ARG1 = global <8 x i16> , align 16 @@ -156,12 +157,14 @@ declare <8 x i16> @llvm.mips.sll.h(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_sll_h_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_h_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_h_ARG2) -; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sll.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.h [[WD]] +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_h_ARG2) +; CHECK: ld.h [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK: ldi.h [[R3:\$w[0-9]+]], 15 +; CHECK: and.v [[WT:\$w[0-9]+]], [[R4]], [[R3]] +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_h_ARG1) +; CHECK: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) +; CHECK: sll.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.h [[WD]] ; CHECK: .size llvm_mips_sll_h_test ; @llvm_mips_sll_w_ARG1 = global <4 x i32> , align 16 @@ -180,12 +183,14 @@ declare <4 x i32> @llvm.mips.sll.w(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_sll_w_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_w_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_w_ARG2) -; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sll.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.w [[WD]] +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_w_ARG2) +; CHECK: ld.w [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK: ldi.w [[R3:\$w[0-9]+]], 31 +; CHECK: and.v [[WT:\$w[0-9]+]], [[R4]], [[R3]] +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_w_ARG1) +; CHECK: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) +; CHECK: sll.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.w [[WD]] ; CHECK: .size llvm_mips_sll_w_test ; @llvm_mips_sll_d_ARG1 = global <2 x i64> , align 16 @@ -204,12 +209,14 @@ declare <2 x i64> @llvm.mips.sll.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: llvm_mips_sll_d_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_d_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_d_ARG2) -; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sll.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.d [[WD]] +; CHECK: ldi.d [[R3:\$w[0-9]+]], 63 +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_sll_d_ARG2) +; CHECK: ld.d [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK: and.v [[WT:\$w[0-9]+]], [[R4]], [[R3]] +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_sll_d_ARG1) +; CHECK: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) +; CHECK: sll.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.d [[WD]] ; CHECK: .size llvm_mips_sll_d_test define void @sll_b_test() nounwind { @@ -300,12 +307,13 @@ declare <16 x i8> @llvm.mips.sra.b(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_sra_b_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_b_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_b_ARG2) -; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sra.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.b [[WD]] +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_b_ARG2) +; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK: andi.b [[WT:\$w[0-9]+]], [[R4]], 7 +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_b_ARG1) +; CHECK: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) +; CHECK: sra.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.b [[WD]] ; CHECK: .size llvm_mips_sra_b_test ; @llvm_mips_sra_h_ARG1 = global <8 x i16> , align 16 @@ -324,12 +332,14 @@ declare <8 x i16> @llvm.mips.sra.h(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_sra_h_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_h_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_h_ARG2) -; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sra.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.h [[WD]] +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_h_ARG2) +; CHECK: ld.h [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK: ldi.h [[R3:\$w[0-9]+]], 15 +; CHECK: and.v [[WT:\$w[0-9]+]], [[R4]], [[R3]] +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_h_ARG1) +; CHECK: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) +; CHECK: sra.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.h [[WD]] ; CHECK: .size llvm_mips_sra_h_test ; @llvm_mips_sra_w_ARG1 = global <4 x i32> , align 16 @@ -348,12 +358,14 @@ declare <4 x i32> @llvm.mips.sra.w(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_sra_w_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_w_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_w_ARG2) -; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sra.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.w [[WD]] +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_w_ARG2) +; CHECK: ld.w [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK: ldi.w [[R3:\$w[0-9]+]], 31 +; CHECK: and.v [[WT:\$w[0-9]+]], [[R4]], [[R3]] +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_w_ARG1) +; CHECK: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) +; CHECK: sra.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.w [[WD]] ; CHECK: .size llvm_mips_sra_w_test ; @llvm_mips_sra_d_ARG1 = global <2 x i64> , align 16 @@ -372,12 +384,14 @@ declare <2 x i64> @llvm.mips.sra.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: llvm_mips_sra_d_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_d_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_d_ARG2) -; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: sra.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.d [[WD]] +; CHECK: ldi.d [[R3:\$w[0-9]+]], 63 +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_sra_d_ARG2) +; CHECK: ld.d [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK: and.v [[WT:\$w[0-9]+]], [[R4]], [[R3]] +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_sra_d_ARG1) +; CHECK: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) +; CHECK: sra.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.d [[WD]] ; CHECK: .size llvm_mips_sra_d_test ; @@ -565,12 +579,13 @@ declare <16 x i8> @llvm.mips.srl.b(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_srl_b_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_b_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_b_ARG2) -; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: srl.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.b [[WD]] +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_b_ARG2) +; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK: andi.b [[WT:\$w[0-9]+]], [[R4]], 7 +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_b_ARG1) +; CHECK: ld.b [[WS:\$w[0-9]+]], 0([[R1]]) +; CHECK: srl.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.b [[WD]] ; CHECK: .size llvm_mips_srl_b_test ; @llvm_mips_srl_h_ARG1 = global <8 x i16> , align 16 @@ -589,12 +604,14 @@ declare <8 x i16> @llvm.mips.srl.h(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_srl_h_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_h_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_h_ARG2) -; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: srl.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.h [[WD]] +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_h_ARG2) +; CHECK: ld.h [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK: ldi.h [[R3:\$w[0-9]+]], 15 +; CHECK: and.v [[WT:\$w[0-9]+]], [[R4]], [[R3]] +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_h_ARG1) +; CHECK: ld.h [[WS:\$w[0-9]+]], 0([[R1]]) +; CHECK: srl.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.h [[WD]] ; CHECK: .size llvm_mips_srl_h_test ; @llvm_mips_srl_w_ARG1 = global <4 x i32> , align 16 @@ -613,15 +630,17 @@ declare <4 x i32> @llvm.mips.srl.w(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_srl_w_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_w_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_w_ARG2) -; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: srl.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.w [[WD]] +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_w_ARG2) +; CHECK: ld.w [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK: ldi.w [[R3:\$w[0-9]+]], 31 +; CHECK: and.v [[WT:\$w[0-9]+]], [[R4]], [[R3]] +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_w_ARG1) +; CHECK: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) +; CHECK: srl.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.w [[WD]] ; CHECK: .size llvm_mips_srl_w_test -; @llvm_mips_srl_d_ARG1 = global <2 x i64> , align 16 +; @llvm_mips_srl_d_ARG2 = global <2 x i64> , align 16 @llvm_mips_srl_d_RES = global <2 x i64> , align 16 @@ -637,12 +656,14 @@ declare <2 x i64> @llvm.mips.srl.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: llvm_mips_srl_d_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_srl_d_ARG1) -; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_d_ARG2) -; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) -; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: srl.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] -; CHECK-DAG: st.d [[WD]] +; CHECK: ldi.d [[R1:\$w[0-9]+]], 63 +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_srl_d_ARG2) +; CHECK: ld.d [[R3:\$w[0-9]+]], 0([[R2]]) +; CHECK: and.v [[WT:\$w[0-9]+]], [[R3]], [[R1]] +; CHECK: lw [[R4:\$[0-9]+]], %got(llvm_mips_srl_d_ARG1) +; CHECK: ld.d [[WS:\$w[0-9]+]], 0([[R4]]) +; CHECK: srl.d [[WD:\$w[0-9]+]], [[WS]], [[WT]] +; CHECK: st.d [[WD]] ; CHECK: .size llvm_mips_srl_d_test ; @llvm_mips_srlr_b_ARG1 = global <16 x i8> , align 16 Index: test/CodeGen/Mips/msa/shift_constant_pool.ll =================================================================== --- test/CodeGen/Mips/msa/shift_constant_pool.ll +++ test/CodeGen/Mips/msa/shift_constant_pool.ll @@ -0,0 +1,90 @@ +; Test whether the following functions, with vectors featuring negative or values larger than the element +; bit size have their results of operations generated correctly when placed into constant pools + +; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefix=CHECK-ALL -check-prefix=MIPS64 %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefix=CHECK-ALL -check-prefix=MIPS32 %s + +@llvm_mips_sll_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16 + +define i32 @llvm_mips_sll_w_test_const_vec() nounwind { +entry: + %0 = tail call <4 x i32> @llvm.mips.sll.w(<4 x i32> , <4 x i32> ) + store <4 x i32> %0, <4 x i32>* @llvm_mips_sll_w_test_const_vec_res + ret i32 0 +} + +declare <4 x i32> @llvm.mips.sll.w(<4 x i32>, <4 x i32>) nounwind + +; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]: +; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]: +; CHECK-ALL: .4byte 2147483648 # 0x80000000 +; CHECK-ALL: .4byte 2147483648 # 0x80000000 +; CHECK-ALL: .4byte 4 # 0x4 +; CHECK-ALL: .4byte 4 # 0x4 +; CHECK-ALL: llvm_mips_sll_w_test_const_vec: +; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]]) +; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]]) +; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_sll_w_test_const_vec_res)($[[R1]]) +; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]]) +; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]]) +; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_sll_w_test_const_vec_res)($[[R1]]) +; CHECK-ALL: ld.w $w0, 0($[[R2]]) +; CHECK-ALL: st.w $w0, 0($[[R3]]) +; CHECK-ALL: .end llvm_mips_sll_w_test_const_vec +; +@llvm_mips_srl_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16 + +define i32 @llvm_mips_srl_w_test_const_vec() nounwind { +entry: + %0 = tail call <4 x i32> @llvm.mips.srl.w(<4 x i32> , <4 x i32> ) + store <4 x i32> %0, <4 x i32>* @llvm_mips_srl_w_test_const_vec_res + ret i32 0 +} + +declare <4 x i32> @llvm.mips.srl.w(<4 x i32>, <4 x i32>) nounwind + +; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]: +; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]: +; CHECK-ALL: .4byte 1073741820 # 0x3ffffffc +; CHECK-ALL: .4byte 4 # 0x4 +; CHECK-ALL: .4byte 8 # 0x8 +; CHECK-ALL: .4byte 8 # 0x8 +; CHECK-ALL: llvm_mips_srl_w_test_const_vec: +; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]]) +; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]]) +; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_srl_w_test_const_vec_res)($[[R1]]) +; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]]) +; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]]) +; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_srl_w_test_const_vec_res)($[[R1]]) +; CHECK-ALL: ld.w $w0, 0($[[R2]]) +; CHECK-ALL: st.w $w0, 0($[[R3]]) +; CHECK-ALL: .end llvm_mips_srl_w_test_const_vec +; +@llvm_mips_sra_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16 + +define i32 @llvm_mips_sra_w_test_const_vec() nounwind { +entry: + %0 = tail call <4 x i32> @llvm.mips.sra.w(<4 x i32> , <4 x i32> ) + store <4 x i32> %0, <4 x i32>* @llvm_mips_sra_w_test_const_vec_res + ret i32 0 +} + +declare <4 x i32> @llvm.mips.sra.w(<4 x i32>, <4 x i32>) nounwind + +; MIPS32: [[LABEL:\$CPI[0-9]+_[0-9]+]]: +; MIPS64: [[LABEL:\.LCPI[0-9]+_[0-9]+]]: +; CHECK-ALL: .4byte 4294967292 # 0xfffffffc +; CHECK-ALL: .4byte 4 # 0x4 +; CHECK-ALL: .4byte 8 # 0x8 +; CHECK-ALL: .4byte 8 # 0x8 +; CHECK-ALL: llvm_mips_sra_w_test_const_vec: +; MIPS32: lw $[[R2:[0-9]+]], %got([[LABEL]])($[[R1:[0-9]+]]) +; MIPS32: addiu $[[R2]], $[[R2]], %lo([[LABEL]]) +; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_sra_w_test_const_vec_res)($[[R1]]) +; MIPS64: ld $[[R2:[0-9]+]], %got_page([[LABEL]])($[[R1:[0-9]+]]) +; MIPS64: daddiu $[[R2]], $[[R2]], %got_ofst([[LABEL]]) +; MIPS64: ld $[[R3:[0-9]+]], %got_disp(llvm_mips_sra_w_test_const_vec_res)($[[R1]]) +; CHECK-ALL: ld.w $w0, 0($[[R2]]) +; CHECK-ALL: st.w $w0, 0($[[R3]]) +; CHECK-ALL: .end llvm_mips_sra_w_test_const_vec +;