Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -11691,16 +11691,6 @@
     KnownOne &= Mask;
     return;
   }
-  if (Op.getOpcode() == ARMISD::CMOV) {
-    APInt KZ2(KnownZero.getBitWidth(), 0);
-    APInt KO2(KnownOne.getBitWidth(), 0);
-    computeKnownBits(DAG, Op.getOperand(1), KnownZero, KnownOne);
-    computeKnownBits(DAG, Op.getOperand(2), KZ2, KO2);
-
-    KnownZero &= KZ2;
-    KnownOne &= KO2;
-    return;
-  }
   return DAG.computeKnownBits(Op, KnownZero, KnownOne);
 }
 
Index: test/CodeGen/ARM/bfi.ll
===================================================================
--- test/CodeGen/ARM/bfi.ll
+++ test/CodeGen/ARM/bfi.ll
@@ -169,3 +169,19 @@
   %sel = select i1 %cmp, i32 %y2, i32 %or
   ret i32 %sel
 }
+
+; (We could probably improve the generated code here by converting the
+; or + select sequence into "orr r0, r0, r3, lsl #1" or something like that.)
+define i64 @f14(i64 %data, i1 zeroext %f1, i1 zeroext %f2) local_unnamed_addr #0 {
+; CHECK-LABEL: f14:
+; CHECK: cmp r2, #0
+; CHECK-NEXT: bfc [[RESULT:r[0-9]+]], #1, #1
+; CHECK-NEXT: moveq [[RESULT]], r0
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: orrne [[RESULT:r[0-9]+]], [[RESULT]], #2
+  %and = and i64 %data, -3
+  %and.data = select i1 %f1, i64 %and, i64 %data
+  %or = or i64 %and.data, 2
+  %data.addr.1 = select i1 %f2, i64 %or, i64 %and.data
+  ret i64 %data.addr.1
+}