Index: llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp =================================================================== --- llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -166,7 +166,8 @@ for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I; ++I) { unsigned Reg = *I; - if (!IsReturnBlock && !Pristine.test(Reg)) continue; + if (!IsReturnBlock && !(Pristine.test(Reg) || BB->isLiveIn(Reg))) + continue; for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { unsigned AliasReg = *AI; State->UnionGroups(AliasReg, 0); Index: llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp =================================================================== --- llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -73,7 +73,9 @@ BitVector Pristine = MFI.getPristineRegs(MF); for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I; ++I) { - if (!IsReturnBlock && !Pristine.test(*I)) continue; + unsigned Reg = *I; + if (!IsReturnBlock && !(Pristine.test(Reg) || BB->isLiveIn(Reg))) + continue; for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { unsigned Reg = *AI; Classes[Reg] = reinterpret_cast(-1); Index: llvm/test/CodeGen/PowerPC/pristine-and-livein.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/PowerPC/pristine-and-livein.ll @@ -0,0 +1,118 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le--linux-gnu" + +; See pr32292 for details. + +; REG, which is clobbered by an li instruction, shouldn't be a callee-saved +; register. +; CHECK-LABEL: test +; CHECK: li [[REG:[0-9]+]], 0 +; CHECK-NOT: std [[REG]], +define i64 @test(i64 %adler, i8* readonly %buf, i64 %len) { +entry: + %shr = lshr i64 %adler, 16 + %and = and i64 %shr, 65535 + %and1 = and i64 %adler, 65535 + br i1 undef, label %if.then, label %if.end11 + +if.then: ; preds = %entry + %add = add nuw nsw i64 %and1, 0 + %sub = add nsw i64 %add, -65521 + %sub.add = select i1 undef, i64 %sub, i64 %add + %add5 = add nsw i64 %sub.add, %and + %sum2.0 = select i1 false, i64 undef, i64 %add5 + %shl = shl i64 %sum2.0, 16 + %or = or i64 %shl, %sub.add + br label %cleanup + +if.end11: ; preds = %entry + br label %if.end15 + +if.end15: ; preds = %if.end11 + br i1 undef, label %while.cond.preheader, label %while.cond30.preheader + +while.cond30.preheader: ; preds = %if.end15 + br label %while.body33 + +while.cond.preheader: ; preds = %if.end15 + %sub25.adler.addr.1 = select i1 false, i64 undef, i64 %and1 + %rem = urem i64 %and, 65521 + %shl27 = shl nuw nsw i64 %rem, 16 + %or28 = or i64 %shl27, %sub25.adler.addr.1 + br label %cleanup + +while.body33: ; preds = %do.end, %while.cond30.preheader + %len.addr.1384 = phi i64 [ %sub34, %do.end ], [ %len, %while.cond30.preheader ] + %adler.addr.3382 = phi i64 [ %rem101, %do.end ], [ %and1, %while.cond30.preheader ] + %sub34 = add i64 %len.addr.1384, -5552 + %tmp12 = load i8, i8* null + %conv36 = zext i8 %tmp12 to i64 + %add37 = add i64 %adler.addr.3382, %conv36 + %add41 = add i64 %add37, 0 + %tmp14 = load i8, i8* undef + %conv44 = zext i8 %tmp14 to i64 + %add45 = add i64 %add41, %conv44 + %arrayidx47 = getelementptr inbounds i8, i8* null, i64 3 + %tmp15 = load i8, i8* %arrayidx47 + %conv48 = zext i8 %tmp15 to i64 + %add49 = add i64 %add45, %conv48 + %add53 = add i64 %add49, 0 + %add57 = add i64 %add53, 0 + %add61 = add i64 %add57, 0 + %add65 = add i64 %add61, 0 + %add69 = add i64 %add65, 0 + %arrayidx71 = getelementptr inbounds i8, i8* null, i64 9 + %tmp21 = load i8, i8* %arrayidx71 + %conv72 = zext i8 %tmp21 to i64 + %add73 = add i64 %add69, %conv72 + %arrayidx75 = getelementptr inbounds i8, i8* null, i64 10 + %tmp22 = load i8, i8* %arrayidx75 + %conv76 = zext i8 %tmp22 to i64 + %add77 = add i64 %add73, %conv76 + %add81 = add i64 %add77, 0 + %arrayidx83 = getelementptr inbounds i8, i8* null, i64 12 + %tmp24 = load i8, i8* %arrayidx83 + %conv84 = zext i8 %tmp24 to i64 + %add85 = add i64 %add81, %conv84 + %add89 = add i64 %add85, 0 + %add93 = add i64 %add89, 0 + %add97 = add i64 %add93, 0 + br label %do.end + +do.end: ; preds = %while.body33 + %rem101 = urem i64 %add97, 65521 + %cmp31 = icmp ugt i64 %sub34, 5551 + br i1 %cmp31, label %while.body33, label %while.end103 + +while.end103: ; preds = %do.end + br label %while.cond106.preheader + +while.cond106.preheader: ; preds = %while.end103 + br i1 undef, label %while.body109.preheader, label %while.body180.preheader + +while.body180.preheader: ; preds = %while.cond106.preheader + %tmp28 = add i64 %sub34, -1 + br label %while.body180.prol + +while.body180.prol: ; preds = %while.body180.prol, %while.body180.preheader + %adler.addr.6366.prol = phi i64 [ %add183.prol, %while.body180.prol ], [ %rem101, %while.body180.preheader ] + %add183.prol = add i64 %adler.addr.6366.prol, 0 + %add184.prol = add i64 %add183.prol, 0 + br i1 undef, label %while.body180.prol.loopexit.unr-lcssa, label %while.body180.prol + +while.body180.prol.loopexit.unr-lcssa: ; preds = %while.body180.prol + %tmp30 = icmp ult i64 %tmp28, 7 + %rem186 = urem i64 %add183.prol, 65521 + %rem187 = urem i64 %add184.prol, 65521 + %shl189 = shl nuw nsw i64 %rem187, 16 + %or190 = or i64 %shl189, %rem186 + br label %cleanup + +while.body109.preheader: ; preds = %while.cond106.preheader + unreachable + +cleanup: ; preds = %while.body180.prol.loopexit.unr-lcssa, %while.cond.preheader, %if.then + %retval.0 = phi i64 [ %or, %if.then ], [ %or28, %while.cond.preheader ], [ %or190, %while.body180.prol.loopexit.unr-lcssa ] + ret i64 %retval.0 +}