Index: lib/Basic/Targets.cpp =================================================================== --- lib/Basic/Targets.cpp +++ lib/Basic/Targets.cpp @@ -5989,6 +5989,8 @@ this->MCountName = "\01_mcount"; else if (Triple.getOS() == llvm::Triple::UnknownOS) this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; + + SimdDefaultAlign = 128; } StringRef getABI() const override { return ABI; } Index: lib/CodeGen/CGOpenMPRuntime.cpp =================================================================== --- lib/CodeGen/CGOpenMPRuntime.cpp +++ lib/CodeGen/CGOpenMPRuntime.cpp @@ -6654,29 +6654,19 @@ return C.getTypeSize(CDT); } -static void -emitX86DeclareSimdFunction(const FunctionDecl *FD, llvm::Function *Fn, - const llvm::APSInt &VLENVal, - ArrayRef ParamAttrs, - OMPDeclareSimdDeclAttr::BranchStateTy State) { +namespace { struct ISADataTy { char ISA; unsigned VecRegSize; }; - ISADataTy ISAData[] = { - { - 'b', 128 - }, // SSE - { - 'c', 256 - }, // AVX - { - 'd', 256 - }, // AVX2 - { - 'e', 512 - }, // AVX512 - }; +} + +static void +emitTargetDeclareSimdFunction(const FunctionDecl *FD, llvm::Function *Fn, + const llvm::APSInt &VLENVal, + ArrayRef ParamAttrs, + OMPDeclareSimdDeclAttr::BranchStateTy State, + ArrayRef ISAData) { llvm::SmallVector Masked; switch (State) { case OMPDeclareSimdDeclAttr::BS_Undefined: @@ -6696,8 +6686,13 @@ llvm::raw_svector_ostream Out(Buffer); Out << "_ZGV" << Data.ISA << Mask; if (!VLENVal) { - Out << llvm::APSInt::getUnsigned(Data.VecRegSize / - evaluateCDTSize(FD, ParamAttrs)); + auto CDT = evaluateCDTSize(FD, ParamAttrs); + auto V = llvm::APSInt::getUnsigned(Data.VecRegSize / CDT); + // Skip VLEN == 1 functions. + if (V == 1) + continue; + + Out << V; } else Out << VLENVal; for (auto &ParamAttr : ParamAttrs) { @@ -6811,8 +6806,24 @@ VLENVal = VLEN->EvaluateKnownConstInt(C); OMPDeclareSimdDeclAttr::BranchStateTy State = Attr->getBranchState(); if (CGM.getTriple().getArch() == llvm::Triple::x86 || - CGM.getTriple().getArch() == llvm::Triple::x86_64) - emitX86DeclareSimdFunction(FD, Fn, VLENVal, ParamAttrs, State); + CGM.getTriple().getArch() == llvm::Triple::x86_64) { + ISADataTy ISAData[] = { + {'b', 128}, // SSE + {'c', 256}, // AVX + {'d', 256}, // AVX2 + {'e', 512}, // AVX512 + }; + emitTargetDeclareSimdFunction(FD, Fn, VLENVal, ParamAttrs, State, + ISAData); + } + if (CGM.getTriple().getArch() == llvm::Triple::aarch64) { + ISADataTy ISAData[] = { + {'n', 64}, // double-word Advanced SIMD + {'n', 128}, // quad-word Advanced SIMD + }; + emitTargetDeclareSimdFunction(FD, Fn, VLENVal, ParamAttrs, State, + ISAData); + } } } Index: test/OpenMP/declare_simd_codegen.cpp =================================================================== --- test/OpenMP/declare_simd_codegen.cpp +++ test/OpenMP/declare_simd_codegen.cpp @@ -1,7 +1,49 @@ -// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck %s +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck --check-prefix=X86 %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck --check-prefix=X86 %s + +// RUN: %clang_cc1 -verify -triple aarch64-linux-gnu -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck --check-prefix=AARCH64 %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple aarch64-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple aarch64-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck --check-prefix=AARCH64 %s + // expected-no-diagnostics + +// X86-DAG: define {{.+}}@_Z5add_1Pf( +// X86-DAG: define {{.+}}@_Z1hIiEvPT_S1_S1_S1_( +// X86-DAG: define {{.+}}@_Z1hIfEvPT_S1_S1_S1_( +// X86-DAG: define {{.+}}@_ZN2VV3addEii( +// X86-DAG: define {{.+}}@_ZN2VV6taddpfEPfRS0_( +// X86-DAG: define {{.+}}@_ZN2VV4taddERA_iRi( +// X86-DAG: define {{.+}}@_Z1fRA_i( +// X86-DAG: define {{.+}}@_ZN3TVVILi16EfE6taddpfEPfRS1_( +// X86-DAG: define {{.+}}@_ZN3TVVILi16EfE4taddEi( +// X86-DAG: define {{.+}}@_Z3fooILi64EEvRAT__iRPf( +// X86-DAG: define {{.+}}@_Z3bar2VVPf( +// X86-DAG: define {{.+}}@_Z3baz2VVPi( +// X86-DAG: define {{.+}}@_Z3bay2VVRPd( +// X86-DAG: define {{.+}}@_Z3bax2VVPdi( +// X86-DAG: define {{.+}}@_Z3fooPffi( +// X86-DAG: define {{.+}}@_Z3food( +// X86-NOT: "_ZGV{{.+}}__Z1fRA_i + +// AARCH64-DAG: define {{.+}}@_Z5add_1Pf( +// AARCH64-DAG: define {{.+}}@_Z1hIiEvPT_S1_S1_S1_( +// AARCH64-DAG: define {{.+}}@_Z1hIfEvPT_S1_S1_S1_( +// AARCH64-DAG: define {{.+}}@_ZN2VV3addEii( +// AARCH64-DAG: define {{.+}}@_ZN2VV6taddpfEPfRS0_( +// AARCH64-DAG: define {{.+}}@_ZN2VV4taddERA_iRi( +// AARCH64-DAG: define {{.+}}@_Z1fRA_i( +// AARCH64-DAG: define {{.+}}@_ZN3TVVILi16EfE6taddpfEPfRS1_( +// AARCH64-DAG: define {{.+}}@_ZN3TVVILi16EfE4taddEi( +// AARCH64-DAG: define {{.+}}@_Z3fooILi64EEvRAT__iRPf( +// AARCH64-DAG: define {{.+}}@_Z3bar2VVPf( +// AARCH64-DAG: define {{.+}}@_Z3baz2VVPi( +// AARCH64-DAG: define {{.+}}@_Z3bay2VVRPd( +// AARCH64-DAG: define {{.+}}@_Z3bax2VVPdi( +// AARCH64-DAG: define {{.+}}@_Z3fooPffi( +// AARCH64-DAG: define {{.+}}@_Z3food( +// AARCH64-NOT: "_ZGV{{.+}}__Z1fRA_i + #ifndef HEADER #define HEADER @@ -10,6 +52,35 @@ #pragma omp declare simd notinbranch void add_1(float *d) {} +// X86-DAG: "_ZGVbM4l8__Z5add_1Pf" +// X86-DAG: "_ZGVbN4l8__Z5add_1Pf" +// X86-DAG: "_ZGVcM8l8__Z5add_1Pf" +// X86-DAG: "_ZGVcN8l8__Z5add_1Pf" +// X86-DAG: "_ZGVdM8l8__Z5add_1Pf" +// X86-DAG: "_ZGVdN8l8__Z5add_1Pf" +// X86-DAG: "_ZGVeM16l8__Z5add_1Pf" +// X86-DAG: "_ZGVeN16l8__Z5add_1Pf" +// X86-DAG: "_ZGVbM32v__Z5add_1Pf" +// X86-DAG: "_ZGVcM32v__Z5add_1Pf" +// X86-DAG: "_ZGVdM32v__Z5add_1Pf" +// X86-DAG: "_ZGVeM32v__Z5add_1Pf" +// X86-DAG: "_ZGVbN2v__Z5add_1Pf" +// X86-DAG: "_ZGVcN4v__Z5add_1Pf" +// X86-DAG: "_ZGVdN4v__Z5add_1Pf" +// X86-DAG: "_ZGVeN8v__Z5add_1Pf" + +// AARCH64-DAG: "_ZGVnM2l8__Z5add_1Pf" +// AARCH64-DAG: "_ZGVnN2l8__Z5add_1Pf" +// AARCH64-DAG: "_ZGVnM4l8__Z5add_1Pf" +// AARCH64-DAG: "_ZGVnN4l8__Z5add_1Pf" + +// AARCH64-DAG: "_ZGVnM32v__Z5add_1Pf" +// AARCH64-DAG: "_ZGVnM32v__Z5add_1Pf" +// AARCH64-DAG: "_ZGVnM32v__Z5add_1Pf" +// AARCH64-DAG: "_ZGVnM32v__Z5add_1Pf" + +// AARCH64-DAG: "_ZGVnN2v__Z5add_1Pf" + #pragma omp declare simd aligned(hp, hp2) template void h(C *hp, C *hp2, C *hq, C *lin) { @@ -26,6 +97,30 @@ h((float *)hp, (float *)hp2, (float *)hq, (float *)lin); } +// X86-DAG: "_ZGVbM2va16va16vv__Z1hIiEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVbN2va16va16vv__Z1hIiEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVcM4va16va16vv__Z1hIiEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVcN4va16va16vv__Z1hIiEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVdM4va16va16vv__Z1hIiEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVdN4va16va16vv__Z1hIiEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVeM8va16va16vv__Z1hIiEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVeN8va16va16vv__Z1hIiEvPT_S1_S1_S1_" + +// X86-DAG: "_ZGVbM2va16va16vv__Z1hIfEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVbN2va16va16vv__Z1hIfEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVcM4va16va16vv__Z1hIfEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVcN4va16va16vv__Z1hIfEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVdM4va16va16vv__Z1hIfEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVdN4va16va16vv__Z1hIfEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVeM8va16va16vv__Z1hIfEvPT_S1_S1_S1_" +// X86-DAG: "_ZGVeN8va16va16vv__Z1hIfEvPT_S1_S1_S1_" + +// AARCH64-DAG: "_ZGVnM2va16va16vv__Z1hIiEvPT_S1_S1_S1_" +// AARCH64-DAG: "_ZGVnN2va16va16vv__Z1hIiEvPT_S1_S1_S1_" + +// AARCH64-DAG: "_ZGVnM2va16va16vv__Z1hIfEvPT_S1_S1_S1_" +// AARCH64-DAG: "_ZGVnN2va16va16vv__Z1hIfEvPT_S1_S1_S1_" + class VV { public: #pragma omp declare simd uniform(this, a) linear(val(b) : a) @@ -42,6 +137,56 @@ int x[10]; } vv; +// X86-DAG: "_ZGVbM4uus1__ZN2VV3addEii" +// X86-DAG: "_ZGVbN4uus1__ZN2VV3addEii" +// X86-DAG: "_ZGVcM8uus1__ZN2VV3addEii" +// X86-DAG: "_ZGVcN8uus1__ZN2VV3addEii" +// X86-DAG: "_ZGVdM8uus1__ZN2VV3addEii" +// X86-DAG: "_ZGVdN8uus1__ZN2VV3addEii" +// X86-DAG: "_ZGVeM16uus1__ZN2VV3addEii" +// X86-DAG: "_ZGVeN16uus1__ZN2VV3addEii" + +// X86-DAG: "_ZGVbM4lla16l4a4__ZN2VV6taddpfEPfRS0_" +// X86-DAG: "_ZGVbN4lla16l4a4__ZN2VV6taddpfEPfRS0_" +// X86-DAG: "_ZGVcM8lla16l4a4__ZN2VV6taddpfEPfRS0_" +// X86-DAG: "_ZGVcN8lla16l4a4__ZN2VV6taddpfEPfRS0_" +// X86-DAG: "_ZGVdM8lla16l4a4__ZN2VV6taddpfEPfRS0_" +// X86-DAG: "_ZGVdN8lla16l4a4__ZN2VV6taddpfEPfRS0_" +// X86-DAG: "_ZGVeM16lla16l4a4__ZN2VV6taddpfEPfRS0_" +// X86-DAG: "_ZGVeN16lla16l4a4__ZN2VV6taddpfEPfRS0_" + +// X86-DAG: "_ZGVbM4vvl8__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVbN4vvl8__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVcM8vvl8__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVcN8vvl8__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVdM8vvl8__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVdN8vvl8__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVeM16vvl8__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVeN16vvl8__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVbM4vva8v__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVbN4vva8v__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVcM8vva8v__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVcN8vva8v__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVdM8vva8v__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVdN8vva8v__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVeM16vva8v__ZN2VV4taddERA_iRi" +// X86-DAG: "_ZGVeN16vva8v__ZN2VV4taddERA_iRi" + +// AARCH64-DAG: "_ZGVnM2uus1__ZN2VV3addEii" +// AARCH64-DAG: "_ZGVnN2uus1__ZN2VV3addEii" +// AARCH64-DAG: "_ZGVnM4uus1__ZN2VV3addEii" +// AARCH64-DAG: "_ZGVnN4uus1__ZN2VV3addEii" + +// AARCH64-DAG: "_ZGVnM2lla16l4a4__ZN2VV6taddpfEPfRS0_" +// AARCH64-DAG: "_ZGVnN2lla16l4a4__ZN2VV6taddpfEPfRS0_" +// AARCH64-DAG: "_ZGVnM4lla16l4a4__ZN2VV6taddpfEPfRS0_" +// AARCH64-DAG: "_ZGVnN4lla16l4a4__ZN2VV6taddpfEPfRS0_" + +// AARCH64-DAG: "_ZGVnM2vvl8__ZN2VV4taddERA_iRi" +// AARCH64-DAG: "_ZGVnN2vvl8__ZN2VV4taddERA_iRi" +// AARCH64-DAG: "_ZGVnM4vvl8__ZN2VV4taddERA_iRi" +// AARCH64-DAG: "_ZGVnN4vvl8__ZN2VV4taddERA_iRi" + template class TVV { public: @@ -77,211 +222,168 @@ foo(c, p); } +// X86-DAG: "_ZGVbM4vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" +// X86-DAG: "_ZGVbN4vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" +// X86-DAG: "_ZGVcM8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" +// X86-DAG: "_ZGVcN8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" +// X86-DAG: "_ZGVdM8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" +// X86-DAG: "_ZGVdN8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" +// X86-DAG: "_ZGVeM16vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" +// X86-DAG: "_ZGVeN16vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" + +// X86-DAG: "_ZGVbM4uu__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVbN4uu__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVcM8uu__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVcN8uu__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVdM8uu__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVdN8uu__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVeM16uu__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVeN16uu__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVbM4vv__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVbN4vv__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVcM8vv__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVcN8vv__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVdM8vv__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVdN8vv__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVeM16vv__ZN3TVVILi16EfE4taddEi" +// X86-DAG: "_ZGVeN16vv__ZN3TVVILi16EfE4taddEi" + +// X86-DAG: "_ZGVbM64va128l64__Z3fooILi64EEvRAT__iRPf" +// X86-DAG: "_ZGVbN64va128l64__Z3fooILi64EEvRAT__iRPf" +// X86-DAG: "_ZGVcM64va128l64__Z3fooILi64EEvRAT__iRPf" +// X86-DAG: "_ZGVcN64va128l64__Z3fooILi64EEvRAT__iRPf" +// X86-DAG: "_ZGVdM64va128l64__Z3fooILi64EEvRAT__iRPf" +// X86-DAG: "_ZGVdN64va128l64__Z3fooILi64EEvRAT__iRPf" +// X86-DAG: "_ZGVeM64va128l64__Z3fooILi64EEvRAT__iRPf" +// X86-DAG: "_ZGVeN64va128l64__Z3fooILi64EEvRAT__iRPf" + +// AARCH64-DAG: "_ZGVnM2vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" +// AARCH64-DAG: "_ZGVnN2vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" +// AARCH64-DAG: "_ZGVnM4vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" +// AARCH64-DAG: "_ZGVnN4vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" + +// AARCH64-DAG: "_ZGVnM2uu__ZN3TVVILi16EfE4taddEi" +// AARCH64-DAG: "_ZGVnN2uu__ZN3TVVILi16EfE4taddEi" +// AARCH64-DAG: "_ZGVnM4uu__ZN3TVVILi16EfE4taddEi" +// AARCH64-DAG: "_ZGVnN4uu__ZN3TVVILi16EfE4taddEi" + +// AARCH64-DAG: "_ZGVnM2vv__ZN3TVVILi16EfE4taddEi" +// AARCH64-DAG: "_ZGVnN2vv__ZN3TVVILi16EfE4taddEi" +// AARCH64-DAG: "_ZGVnM4vv__ZN3TVVILi16EfE4taddEi" +// AARCH64-DAG: "_ZGVnN4vv__ZN3TVVILi16EfE4taddEi" + +// AARCH64-DAG: "_ZGVnM64va128l64__Z3fooILi64EEvRAT__iRPf" +// AARCH64-DAG: "_ZGVnN64va128l64__Z3fooILi64EEvRAT__iRPf" + #pragma omp declare simd #pragma omp declare simd notinbranch aligned(a : 32) int bar(VV v, float *a) { return 0; } + +// X86-DAG: "_ZGVbM4vv__Z3bar2VVPf" +// X86-DAG: "_ZGVbN4vv__Z3bar2VVPf" +// X86-DAG: "_ZGVcM8vv__Z3bar2VVPf" +// X86-DAG: "_ZGVcN8vv__Z3bar2VVPf" +// X86-DAG: "_ZGVdM8vv__Z3bar2VVPf" +// X86-DAG: "_ZGVdN8vv__Z3bar2VVPf" +// X86-DAG: "_ZGVeM16vv__Z3bar2VVPf" +// X86-DAG: "_ZGVeN16vv__Z3bar2VVPf" +// X86-DAG: "_ZGVbN4vva32__Z3bar2VVPf" +// X86-DAG: "_ZGVcN8vva32__Z3bar2VVPf" +// X86-DAG: "_ZGVdN8vva32__Z3bar2VVPf" +// X86-DAG: "_ZGVeN16vva32__Z3bar2VVPf" + +// AARCH64-DAG: "_ZGVnM4vv__Z3bar2VVPf" +// AARCH64-DAG: "_ZGVnN4vv__Z3bar2VVPf" +// AARCH64-DAG: "_ZGVnN4vva32__Z3bar2VVPf" + #pragma omp declare simd #pragma omp declare simd notinbranch aligned(a) float baz(VV v, int a[]) { return 0; } + +// X86-DAG: "_ZGVbM4vv__Z3baz2VVPi" +// X86-DAG: "_ZGVbN4vv__Z3baz2VVPi" +// X86-DAG: "_ZGVcM8vv__Z3baz2VVPi" +// X86-DAG: "_ZGVcN8vv__Z3baz2VVPi" +// X86-DAG: "_ZGVdM8vv__Z3baz2VVPi" +// X86-DAG: "_ZGVdN8vv__Z3baz2VVPi" +// X86-DAG: "_ZGVeM16vv__Z3baz2VVPi" +// X86-DAG: "_ZGVeN16vv__Z3baz2VVPi" +// X86-DAG: "_ZGVbN4vva16__Z3baz2VVPi" +// X86-DAG: "_ZGVcN8vva16__Z3baz2VVPi" +// X86-DAG: "_ZGVdN8vva16__Z3baz2VVPi" +// X86-DAG: "_ZGVeN16vva16__Z3baz2VVPi" + +// AARCH64-DAG: "_ZGVnM2vv__Z3baz2VVPi" +// AARCH64-DAG: "_ZGVnN2vv__Z3baz2VVPi" +// AARCH64-DAG: "_ZGVnM4vv__Z3baz2VVPi" +// AARCH64-DAG: "_ZGVnN4vv__Z3baz2VVPi" +// AARCH64-DAG: "_ZGVnN2vva16__Z3baz2VVPi" +// AARCH64-DAG: "_ZGVnN4vva16__Z3baz2VVPi" + #pragma omp declare simd #pragma omp declare simd notinbranch aligned(a) double bay(VV v, double *&a) { return 0; } + +// X86-DAG: "_ZGVbM2vv__Z3bay2VVRPd" +// X86-DAG: "_ZGVbN2vv__Z3bay2VVRPd" +// X86-DAG: "_ZGVcM4vv__Z3bay2VVRPd" +// X86-DAG: "_ZGVcN4vv__Z3bay2VVRPd" +// X86-DAG: "_ZGVdM4vv__Z3bay2VVRPd" +// X86-DAG: "_ZGVdN4vv__Z3bay2VVRPd" +// X86-DAG: "_ZGVeM8vv__Z3bay2VVRPd" +// X86-DAG: "_ZGVeN8vv__Z3bay2VVRPd" +// X86-DAG: "_ZGVbN2vva16__Z3bay2VVRPd" +// X86-DAG: "_ZGVcN4vva16__Z3bay2VVRPd" +// X86-DAG: "_ZGVdN4vva16__Z3bay2VVRPd" +// X86-DAG: "_ZGVeN8vva16__Z3bay2VVRPd" + +// AARCH64-DAG: "_ZGVnM2vv__Z3bay2VVRPd" +// AARCH64-DAG: "_ZGVnN2vv__Z3bay2VVRPd" +// AARCH64-DAG: "_ZGVnN2vva16__Z3bay2VVRPd" + #pragma omp declare simd #pragma omp declare simd inbranch linear(a : b) uniform(v, b) void bax(VV v, double *a, int b) {} + +// X86-DAG: "_ZGVbM4us2u__Z3bax2VVPdi" +// X86-DAG: "_ZGVcM8us2u__Z3bax2VVPdi" +// X86-DAG: "_ZGVdM8us2u__Z3bax2VVPdi" +// X86-DAG: "_ZGVeM16us2u__Z3bax2VVPdi" +// X86-DAG: "_ZGVbM4vvv__Z3bax2VVPdi" +// X86-DAG: "_ZGVbN4vvv__Z3bax2VVPdi" +// X86-DAG: "_ZGVcM8vvv__Z3bax2VVPdi" +// X86-DAG: "_ZGVcN8vvv__Z3bax2VVPdi" +// X86-DAG: "_ZGVdM8vvv__Z3bax2VVPdi" +// X86-DAG: "_ZGVdN8vvv__Z3bax2VVPdi" +// X86-DAG: "_ZGVeM16vvv__Z3bax2VVPdi" +// X86-DAG: "_ZGVeN16vvv__Z3bax2VVPdi" + +// AARCH64-DAG: "_ZGVnM2us2u__Z3bax2VVPdi" +// AARCH64-DAG: "_ZGVnN2vvv__Z3bax2VVPdi" + #pragma omp declare simd uniform(q) aligned(q : 16) linear(k : 1) float foo(float *q, float x, int k) { return 0; } + +// X86-DAG: "_ZGVbM4ua16vl1__Z3fooPffi" +// X86-DAG: "_ZGVbN4ua16vl1__Z3fooPffi" +// X86-DAG: "_ZGVcM8ua16vl1__Z3fooPffi" +// X86-DAG: "_ZGVcN8ua16vl1__Z3fooPffi" +// X86-DAG: "_ZGVdM8ua16vl1__Z3fooPffi" +// X86-DAG: "_ZGVdN8ua16vl1__Z3fooPffi" +// X86-DAG: "_ZGVeM16ua16vl1__Z3fooPffi" +// X86-DAG: "_ZGVeN16ua16vl1__Z3fooPffi" + +// AARCH64-DAG: "_ZGVnM4ua16vl1__Z3fooPffi" +// AARCH64-DAG: "_ZGVnN4ua16vl1__Z3fooPffi" + #pragma omp declare simd notinbranch double foo(double x) { return 0; } -// CHECK-DAG: define {{.+}}@_Z5add_1Pf( -// CHECK-DAG: define {{.+}}@_Z1hIiEvPT_S1_S1_S1_( -// CHECK-DAG: define {{.+}}@_Z1hIfEvPT_S1_S1_S1_( -// CHECK-DAG: define {{.+}}@_ZN2VV3addEii( -// CHECK-DAG: define {{.+}}@_ZN2VV6taddpfEPfRS0_( -// CHECK-DAG: define {{.+}}@_ZN2VV4taddERA_iRi( -// CHECK-DAG: define {{.+}}@_Z1fRA_i( -// CHECK-DAG: define {{.+}}@_ZN3TVVILi16EfE6taddpfEPfRS1_( -// CHECK-DAG: define {{.+}}@_ZN3TVVILi16EfE4taddEi( -// CHECK-DAG: define {{.+}}@_Z3fooILi64EEvRAT__iRPf( -// CHECK-DAG: define {{.+}}@_Z3bar2VVPf( -// CHECK-DAG: define {{.+}}@_Z3baz2VVPi( -// CHECK-DAG: define {{.+}}@_Z3bay2VVRPd( -// CHECK-DAG: define {{.+}}@_Z3bax2VVPdi( -// CHECK-DAG: define {{.+}}@_Z3fooPffi( -// CHECK-DAG: define {{.+}}@_Z3food( - -// CHECK-DAG: "_ZGVbM4l8__Z5add_1Pf" -// CHECK-DAG: "_ZGVbN4l8__Z5add_1Pf" -// CHECK-DAG: "_ZGVcM8l8__Z5add_1Pf" -// CHECK-DAG: "_ZGVcN8l8__Z5add_1Pf" -// CHECK-DAG: "_ZGVdM8l8__Z5add_1Pf" -// CHECK-DAG: "_ZGVdN8l8__Z5add_1Pf" -// CHECK-DAG: "_ZGVeM16l8__Z5add_1Pf" -// CHECK-DAG: "_ZGVeN16l8__Z5add_1Pf" -// CHECK-DAG: "_ZGVbM32v__Z5add_1Pf" -// CHECK-DAG: "_ZGVcM32v__Z5add_1Pf" -// CHECK-DAG: "_ZGVdM32v__Z5add_1Pf" -// CHECK-DAG: "_ZGVeM32v__Z5add_1Pf" -// CHECK-DAG: "_ZGVbN2v__Z5add_1Pf" -// CHECK-DAG: "_ZGVcN4v__Z5add_1Pf" -// CHECK-DAG: "_ZGVdN4v__Z5add_1Pf" -// CHECK-DAG: "_ZGVeN8v__Z5add_1Pf" - -// CHECK-DAG: "_ZGVbM2va16va16vv__Z1hIiEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVbN2va16va16vv__Z1hIiEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVcM4va16va16vv__Z1hIiEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVcN4va16va16vv__Z1hIiEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVdM4va16va16vv__Z1hIiEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVdN4va16va16vv__Z1hIiEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVeM8va16va16vv__Z1hIiEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVeN8va16va16vv__Z1hIiEvPT_S1_S1_S1_" - -// CHECK-DAG: "_ZGVbM2va16va16vv__Z1hIfEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVbN2va16va16vv__Z1hIfEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVcM4va16va16vv__Z1hIfEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVcN4va16va16vv__Z1hIfEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVdM4va16va16vv__Z1hIfEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVdN4va16va16vv__Z1hIfEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVeM8va16va16vv__Z1hIfEvPT_S1_S1_S1_" -// CHECK-DAG: "_ZGVeN8va16va16vv__Z1hIfEvPT_S1_S1_S1_" - -// CHECK-DAG: "_ZGVbM4uus1__ZN2VV3addEii" -// CHECK-DAG: "_ZGVbN4uus1__ZN2VV3addEii" -// CHECK-DAG: "_ZGVcM8uus1__ZN2VV3addEii" -// CHECK-DAG: "_ZGVcN8uus1__ZN2VV3addEii" -// CHECK-DAG: "_ZGVdM8uus1__ZN2VV3addEii" -// CHECK-DAG: "_ZGVdN8uus1__ZN2VV3addEii" -// CHECK-DAG: "_ZGVeM16uus1__ZN2VV3addEii" -// CHECK-DAG: "_ZGVeN16uus1__ZN2VV3addEii" - -// CHECK-DAG: "_ZGVbM4lla16l4a4__ZN2VV6taddpfEPfRS0_" -// CHECK-DAG: "_ZGVbN4lla16l4a4__ZN2VV6taddpfEPfRS0_" -// CHECK-DAG: "_ZGVcM8lla16l4a4__ZN2VV6taddpfEPfRS0_" -// CHECK-DAG: "_ZGVcN8lla16l4a4__ZN2VV6taddpfEPfRS0_" -// CHECK-DAG: "_ZGVdM8lla16l4a4__ZN2VV6taddpfEPfRS0_" -// CHECK-DAG: "_ZGVdN8lla16l4a4__ZN2VV6taddpfEPfRS0_" -// CHECK-DAG: "_ZGVeM16lla16l4a4__ZN2VV6taddpfEPfRS0_" -// CHECK-DAG: "_ZGVeN16lla16l4a4__ZN2VV6taddpfEPfRS0_" - -// CHECK-DAG: "_ZGVbM4vvl8__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVbN4vvl8__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVcM8vvl8__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVcN8vvl8__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVdM8vvl8__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVdN8vvl8__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVeM16vvl8__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVeN16vvl8__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVbM4vva8v__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVbN4vva8v__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVcM8vva8v__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVcN8vva8v__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVdM8vva8v__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVdN8vva8v__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVeM16vva8v__ZN2VV4taddERA_iRi" -// CHECK-DAG: "_ZGVeN16vva8v__ZN2VV4taddERA_iRi" - -// CHECK-DAG: "_ZGVbM4vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" -// CHECK-DAG: "_ZGVbN4vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" -// CHECK-DAG: "_ZGVcM8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" -// CHECK-DAG: "_ZGVcN8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" -// CHECK-DAG: "_ZGVdM8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" -// CHECK-DAG: "_ZGVdN8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" -// CHECK-DAG: "_ZGVeM16vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" -// CHECK-DAG: "_ZGVeN16vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_" - -// CHECK-DAG: "_ZGVbM4uu__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVbN4uu__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVcM8uu__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVcN8uu__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVdM8uu__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVdN8uu__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVeM16uu__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVeN16uu__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVbM4vv__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVbN4vv__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVcM8vv__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVcN8vv__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVdM8vv__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVdN8vv__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVeM16vv__ZN3TVVILi16EfE4taddEi" -// CHECK-DAG: "_ZGVeN16vv__ZN3TVVILi16EfE4taddEi" - -// CHECK-DAG: "_ZGVbM64va128l64__Z3fooILi64EEvRAT__iRPf" -// CHECK-DAG: "_ZGVbN64va128l64__Z3fooILi64EEvRAT__iRPf" -// CHECK-DAG: "_ZGVcM64va128l64__Z3fooILi64EEvRAT__iRPf" -// CHECK-DAG: "_ZGVcN64va128l64__Z3fooILi64EEvRAT__iRPf" -// CHECK-DAG: "_ZGVdM64va128l64__Z3fooILi64EEvRAT__iRPf" -// CHECK-DAG: "_ZGVdN64va128l64__Z3fooILi64EEvRAT__iRPf" -// CHECK-DAG: "_ZGVeM64va128l64__Z3fooILi64EEvRAT__iRPf" -// CHECK-DAG: "_ZGVeN64va128l64__Z3fooILi64EEvRAT__iRPf" - -// CHECK-DAG: "_ZGVbM4vv__Z3bar2VVPf" -// CHECK-DAG: "_ZGVbN4vv__Z3bar2VVPf" -// CHECK-DAG: "_ZGVcM8vv__Z3bar2VVPf" -// CHECK-DAG: "_ZGVcN8vv__Z3bar2VVPf" -// CHECK-DAG: "_ZGVdM8vv__Z3bar2VVPf" -// CHECK-DAG: "_ZGVdN8vv__Z3bar2VVPf" -// CHECK-DAG: "_ZGVeM16vv__Z3bar2VVPf" -// CHECK-DAG: "_ZGVeN16vv__Z3bar2VVPf" -// CHECK-DAG: "_ZGVbN4vva32__Z3bar2VVPf" -// CHECK-DAG: "_ZGVcN8vva32__Z3bar2VVPf" -// CHECK-DAG: "_ZGVdN8vva32__Z3bar2VVPf" -// CHECK-DAG: "_ZGVeN16vva32__Z3bar2VVPf" - -// CHECK-DAG: "_ZGVbM4vv__Z3baz2VVPi" -// CHECK-DAG: "_ZGVbN4vv__Z3baz2VVPi" -// CHECK-DAG: "_ZGVcM8vv__Z3baz2VVPi" -// CHECK-DAG: "_ZGVcN8vv__Z3baz2VVPi" -// CHECK-DAG: "_ZGVdM8vv__Z3baz2VVPi" -// CHECK-DAG: "_ZGVdN8vv__Z3baz2VVPi" -// CHECK-DAG: "_ZGVeM16vv__Z3baz2VVPi" -// CHECK-DAG: "_ZGVeN16vv__Z3baz2VVPi" -// CHECK-DAG: "_ZGVbN4vva16__Z3baz2VVPi" -// CHECK-DAG: "_ZGVcN8vva16__Z3baz2VVPi" -// CHECK-DAG: "_ZGVdN8vva16__Z3baz2VVPi" -// CHECK-DAG: "_ZGVeN16vva16__Z3baz2VVPi" - -// CHECK-DAG: "_ZGVbM2vv__Z3bay2VVRPd" -// CHECK-DAG: "_ZGVbN2vv__Z3bay2VVRPd" -// CHECK-DAG: "_ZGVcM4vv__Z3bay2VVRPd" -// CHECK-DAG: "_ZGVcN4vv__Z3bay2VVRPd" -// CHECK-DAG: "_ZGVdM4vv__Z3bay2VVRPd" -// CHECK-DAG: "_ZGVdN4vv__Z3bay2VVRPd" -// CHECK-DAG: "_ZGVeM8vv__Z3bay2VVRPd" -// CHECK-DAG: "_ZGVeN8vv__Z3bay2VVRPd" -// CHECK-DAG: "_ZGVbN2vva16__Z3bay2VVRPd" -// CHECK-DAG: "_ZGVcN4vva16__Z3bay2VVRPd" -// CHECK-DAG: "_ZGVdN4vva16__Z3bay2VVRPd" -// CHECK-DAG: "_ZGVeN8vva16__Z3bay2VVRPd" - -// CHECK-DAG: "_ZGVbM4us2u__Z3bax2VVPdi" -// CHECK-DAG: "_ZGVcM8us2u__Z3bax2VVPdi" -// CHECK-DAG: "_ZGVdM8us2u__Z3bax2VVPdi" -// CHECK-DAG: "_ZGVeM16us2u__Z3bax2VVPdi" -// CHECK-DAG: "_ZGVbM4vvv__Z3bax2VVPdi" -// CHECK-DAG: "_ZGVbN4vvv__Z3bax2VVPdi" -// CHECK-DAG: "_ZGVcM8vvv__Z3bax2VVPdi" -// CHECK-DAG: "_ZGVcN8vvv__Z3bax2VVPdi" -// CHECK-DAG: "_ZGVdM8vvv__Z3bax2VVPdi" -// CHECK-DAG: "_ZGVdN8vvv__Z3bax2VVPdi" -// CHECK-DAG: "_ZGVeM16vvv__Z3bax2VVPdi" -// CHECK-DAG: "_ZGVeN16vvv__Z3bax2VVPdi" - -// CHECK-DAG: "_ZGVbM4ua16vl1__Z3fooPffi" -// CHECK-DAG: "_ZGVbN4ua16vl1__Z3fooPffi" -// CHECK-DAG: "_ZGVcM8ua16vl1__Z3fooPffi" -// CHECK-DAG: "_ZGVcN8ua16vl1__Z3fooPffi" -// CHECK-DAG: "_ZGVdM8ua16vl1__Z3fooPffi" -// CHECK-DAG: "_ZGVdN8ua16vl1__Z3fooPffi" -// CHECK-DAG: "_ZGVeM16ua16vl1__Z3fooPffi" -// CHECK-DAG: "_ZGVeN16ua16vl1__Z3fooPffi" - -// CHECK-DAG: "_ZGVbN2v__Z3food" -// CHECK-DAG: "_ZGVcN4v__Z3food" -// CHECK-DAG: "_ZGVdN4v__Z3food" -// CHECK-DAG: "_ZGVeN8v__Z3food" - -// CHECK-NOT: "_ZGV{{.+}}__Z1fRA_i +// X86-DAG: "_ZGVbN2v__Z3food" +// X86-DAG: "_ZGVcN4v__Z3food" +// X86-DAG: "_ZGVdN4v__Z3food" +// X86-DAG: "_ZGVeN8v__Z3food" + +// AARCH64-DAG: "_ZGVnN2v__Z3food" #endif