Index: lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
===================================================================
--- lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
+++ lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
@@ -166,9 +166,7 @@
       if (!PredI.getOperand(2).isImm())
         return None;
 
-      // FIXME: For simplicity, give up on non-zero shifts.
-      if (PredI.getOperand(3).getImm())
-        return None;
+
 
       // The src register must not be modified between the cmp and conditional
       // branch.  This includes a self-clobbering compare.
@@ -176,8 +174,10 @@
         return None;
 
       // We've found the Cmp that sets NZCV.
+      int32_t Imm = PredI.getOperand(2).getImm();
+      int32_t Shift = PredI.getOperand(3).getImm();
       FirstUse = PredI;
-      return RegImm(PredI.getOperand(1).getReg(), PredI.getOperand(2).getImm());
+      return RegImm(PredI.getOperand(1).getReg(), Imm << Shift);
     }
     }
 
Index: test/CodeGen/AArch64/machine-copy-remove.mir
===================================================================
--- test/CodeGen/AArch64/machine-copy-remove.mir
+++ test/CodeGen/AArch64/machine-copy-remove.mir
@@ -535,3 +535,28 @@
 
   bb.2:
     RET_ReallyLR
+...
+# Eliminate redundant MOVi32imm 4096 in bb.1 when the compare has a shifted immediate.
+# CHECK-LABEL: name: test19
+# CHECK: bb.1:
+# CHECK-NOT: MOVi32imm
+name:            test19
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    successors: %bb.1, %bb.2
+    liveins: %w0, %x1
+
+    dead %wzr = SUBSWri killed %w0, 1, 12, implicit-def %nzcv
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    successors: %bb.2
+    liveins: %x1
+
+    %w0 = MOVi32imm 4096
+    STRWui killed %w0, killed %x1, 0
+
+  bb.2:
+    RET_ReallyLR