Index: lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- lib/Target/PowerPC/PPCInstrInfo.td
+++ lib/Target/PowerPC/PPCInstrInfo.td
@@ -3158,6 +3158,28 @@
             (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
 }
 
+multiclass ExtSetCCPat2<CondCode cc, PatFrag pfrag,
+                        OutPatFrag rfrag, OutPatFrag rfrag8> {
+    def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$s2, cc)))),
+              (rfrag $s1, $s2)>;
+    def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i64:$s2, cc)))),
+              (rfrag8 $s1, $s2)>;
+    def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$s2, cc)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $s2), sub_32)>;
+    def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i64:$s2, cc)))),
+              (EXTRACT_SUBREG (rfrag8 $s1, $s2), sub_32)>;
+  }
+
+// Instead of using rlwinm Rx,Ry,32-n,n,31, the more clever way rlwinm Rx,Ry,
+// 32-n,31,31 are used to extract just one bit. Similar thing for rldicl.
+defm : ExtSetCCPat2<SETEQ,
+                    PatFrag<(ops node:$in1, node:$in2, node:$cc),
+                            (setcc $in1, $in2, $cc)>,
+                    OutPatFrag<(ops node:$in1, node:$in2),
+                               (RLWINM (CNTLZW (SUBF $in1, $in2)), 27, 31, 31)>,
+                    OutPatFrag<(ops node:$in1, node:$in2),
+                               (RLDICL (CNTLZD (SUBF8 $in1, $in2)), 58, 63)> >;
+
 // Note that we do all inversions below with i(32|64)not, instead of using
 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
 // has 2-cycle latency.
Index: test/CodeGen/PowerPC/expand-isel.ll
===================================================================
--- test/CodeGen/PowerPC/expand-isel.ll
+++ test/CodeGen/PowerPC/expand-isel.ll
@@ -212,11 +212,9 @@
   ret i32 %retval.0
 
 ; CHECK-LABEL: @testComplexISEL
-; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
-; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
-; CHECK-NEXT:  [[TRUE]]
-; CHECK-NEXT: addi r3, r12, 0
-; CHECK-NEXT: [[SUCCESSOR]]
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: cntlzd [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT: rldicl [[REG3:r[0-9]+]], [[REG2]], 58, 63
 ; CHECK-NEXT: clrldi r3, r3, 32
 ; CHECK-NEXT: blr
 }
Index: test/CodeGen/PowerPC/testComparesieqsc.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesieqsc.ll
@@ -0,0 +1,62 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b)  {
+; CHECK-LABEL: test_ieqsc:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define signext i32 @test_ieqsc_z(i8 signext %a)  {
+; CHECK-LABEL: test_ieqsc_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define void @test_ieqsc_store(i8 signext %a, i8 signext %b)  {
+; CHECK-LABEL: test_ieqsc_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1, !tbaa !2
+  ret void
+}
+
+define void @test_ieqsc_z_store(i8 signext %a)  {
+; CHECK-LABEL: test_ieqsc_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1, !tbaa !2
+  ret void
+}
+
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testComparesieqsi.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesieqsi.ll
@@ -0,0 +1,58 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b)  {
+; CHECK-LABEL: test_ieqsi:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ieqsi_z(i32 signext %a)  {
+; CHECK-LABEL: test_ieqsi_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define void @test_ieqsi_store(i32 signext %a, i32 signext %b)  {
+; CHECK-LABEL: test_ieqsi_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4, !tbaa !2
+  ret void
+}
+
+define void @test_ieqsi_z_store(i32 signext %a)  {
+; CHECK-LABEL: test_ieqsi_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4, !tbaa !2
+  ret void
+}
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git 557502b9c09889fb352025c4828621791ed9dd12)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"int", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testComparesieqsll.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesieqsll.ll
@@ -0,0 +1,61 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define signext i32 @test_ieqsll(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_ieqsll:
+; CHECK:    sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT:    cntlzd [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rldicl [[REG3:r[0-9]+]], [[REG2]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ieqsll_z(i64 %a)  {
+; CHECK-LABEL: test_ieqsll_z:
+; CHECK:    cntlzd [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], [[REG1]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define void @test_ieqsll_store(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_ieqsll_store:
+; CHECK:    sub [[REG1:r[0-9]+]], r4, r3
+; CHECK:    cntlzd [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rldicl [[REG3:r[0-9]+]], [[REG2]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8, !tbaa !2
+  ret void
+}
+
+define void @test_ieqsll_z_store(i64 %a)  {
+; CHECK-LABEL: test_ieqsll_z_store:
+; CHECK:    cntlzd [[REG1:r[0-9]+]], r3
+; CHECK:    rldicl [[REG2:r[0-9]+]], [[REG1]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"long long", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testComparesieqss.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesieqss.ll
@@ -0,0 +1,64 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+
+define signext i32 @test_ieqss(i16 signext %a, i16 signext %b)  {
+; CHECK-LABEL: test_ieqss:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_ieqss_z(i16 signext %a)  {
+; CHECK-LABEL: test_ieqss_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define void @test_ieqss_store(i16 signext %a, i16 signext %b)  {
+; CHECK-LABEL: test_ieqss_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2, !tbaa !2
+  ret void
+}
+
+
+define void @test_ieqss_z_store(i16 signext %a)  {
+; CHECK-LABEL: test_ieqss_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2, !tbaa !2
+  ret void
+}
+
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"short", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testComparesiequc.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesiequc.ll
@@ -0,0 +1,60 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b)  {
+; CHECK-LABEL: test_iequc:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_iequc_z(i8 zeroext %a)  {
+; CHECK-LABEL: test_iequc_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b)  {
+; CHECK-LABEL: test_iequc_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1, !tbaa !2
+  ret void
+}
+
+define void @test_iequc_z_store(i8 zeroext %a)  {
+; CHECK-LABEL: test_iequc_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testComparesiequi.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesiequi.ll
@@ -0,0 +1,61 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b)  {
+; CHECK-LABEL: test_iequi:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_iequi_z(i32 zeroext %a)  {
+; CHECK-LABEL: test_iequi_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b)  {
+; CHECK-LABEL: test_iequi_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4, !tbaa !2
+  ret void
+}
+
+define void @test_iequi_z_store(i32 zeroext %a)  {
+; CHECK-LABEL: test_iequi_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"int", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testComparesiequll.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesiequll.ll
@@ -0,0 +1,61 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define signext i32 @test_iequll(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_iequll:
+; CHECK:    sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT:    cntlzd [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rldicl [[REG3:r[0-9]+]], [[REG2]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_iequll_z(i64 %a)  {
+; CHECK-LABEL: test_iequll_z:
+; CHECK:    cntlzd [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], [[REG1]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define void @test_iequll_store(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_iequll_store:
+; CHECK:    sub [[REG1:r[0-9]+]], r4, r3
+; CHECK:    cntlzd [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rldicl [[REG3:r[0-9]+]], [[REG2]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8, !tbaa !2
+  ret void
+}
+
+define void @test_iequll_z_store(i64 %a)  {
+; CHECK-LABEL: test_iequll_z_store:
+; CHECK:    cntlzd [[REG1:r[0-9]+]], r3
+; CHECK:    rldicl [[REG2:r[0-9]+]], [[REG1]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"long long", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testComparesiequs.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesiequs.ll
@@ -0,0 +1,61 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b)  {
+; CHECK-LABEL: test_iequs:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_iequs_z(i16 zeroext %a)  {
+; CHECK-LABEL: test_iequs_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b)  {
+; CHECK-LABEL: test_iequs_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2, !tbaa !2
+  ret void
+}
+
+define void @test_iequs_z_store(i16 zeroext %a)  {
+; CHECK-LABEL: test_iequs_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"short", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testCompareslleqsc.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testCompareslleqsc.ll
@@ -0,0 +1,63 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+
+define i64 @test_lleqsc(i8 signext %a, i8 signext %b)  {
+; CHECK-LABEL: test_lleqsc:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_lleqsc_z(i8 signext %a)  {
+; CHECK-LABEL: test_lleqsc_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+
+define void @test_lleqsc_store(i8 signext %a, i8 signext %b)  {
+; CHECK-LABEL: test_lleqsc_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1, !tbaa !2
+  ret void
+}
+
+
+define void @test_lleqsc_z_store(i8 signext %a)  {
+; CHECK-LABEL: test_lleqsc_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testCompareslleqsi.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testCompareslleqsi.ll
@@ -0,0 +1,61 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define i64 @test_lleqsi(i32 signext %a, i32 signext %b)  {
+; CHECK-LABEL: test_lleqsi:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_lleqsi_z(i32 signext %a)  {
+; CHECK-LABEL: test_lleqsi_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_lleqsi_store(i32 signext %a, i32 signext %b)  {
+; CHECK-LABEL: test_lleqsi_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4, !tbaa !2
+  ret void
+}
+
+define void @test_lleqsi_z_store(i32 signext %a)  {
+; CHECK-LABEL: test_lleqsi_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"int", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testCompareslleqsll.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testCompareslleqsll.ll
@@ -0,0 +1,62 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define i64 @test_lleqsll(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_lleqsll:
+; CHECK:    sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT:    cntlzd [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rldicl [[REG3:r[0-9]+]], [[REG2]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_lleqsll_z(i64 %a)  {
+; CHECK-LABEL: test_lleqsll_z:
+; CHECK:    cntlzd [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], [[REG1]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_lleqsll_store(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_lleqsll_store:
+; CHECK:    sub [[REG1:r[0-9]+]], r4, r3
+; CHECK:    cntlzd [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rldicl [[REG3:r[0-9]+]], [[REG2]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8, !tbaa !2
+  ret void
+}
+
+define void @test_lleqsll_z_store(i64 %a)  {
+; CHECK-LABEL: test_lleqsll_z_store:
+; CHECK:    cntlzd [[REG1:r[0-9]+]], r3
+; CHECK:    rldicl [[REG2:r[0-9]+]], [[REG1]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8, !tbaa !2
+  ret void
+}
+
+
+attributes #0 = { norecurse nounwind  "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"long long", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testCompareslleqss.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testCompareslleqss.ll
@@ -0,0 +1,64 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define i64 @test_lleqss(i16 signext %a, i16 signext %b)  {
+; CHECK-LABEL: test_lleqss:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+
+define i64 @test_lleqss_z(i16 signext %a)  {
+; CHECK-LABEL: test_lleqss_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+
+define void @test_lleqss_store(i16 signext %a, i16 signext %b)  {
+; CHECK-LABEL: test_lleqss_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2, !tbaa !2
+  ret void
+}
+
+
+define void @test_lleqss_z_store(i16 signext %a)  {
+; CHECK-LABEL: test_lleqss_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"short", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testComparesllequc.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesllequc.ll
@@ -0,0 +1,60 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b)  {
+; CHECK-LABEL: test_llequc:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llequc_z(i8 zeroext %a)  {
+; CHECK-LABEL: test_llequc_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b)  {
+; CHECK-LABEL: test_llequc_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1, !tbaa !2
+  ret void
+}
+
+define void @test_llequc_z_store(i8 zeroext %a)  {
+; CHECK-LABEL: test_llequc_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testComparesllequi.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesllequi.ll
@@ -0,0 +1,61 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b)  {
+; CHECK-LABEL: test_llequi:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llequi_z(i32 zeroext %a)  {
+; CHECK-LABEL: test_llequi_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b)  {
+; CHECK-LABEL: test_llequi_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4, !tbaa !2
+  ret void
+}
+
+define void @test_llequi_z_store(i32 zeroext %a)  {
+; CHECK-LABEL: test_llequi_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"int", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testComparesllequll.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesllequll.ll
@@ -0,0 +1,61 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define i64 @test_llequll(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_llequll:
+; CHECK:    sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT:    cntlzd [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rldicl [[REG3:r[0-9]+]], [[REG2]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llequll_z(i64 %a)  {
+; CHECK-LABEL: test_llequll_z:
+; CHECK:    cntlzd [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], [[REG1]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llequll_store(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_llequll_store:
+; CHECK:    sub [[REG1:r[0-9]+]], r4, r3
+; CHECK:    cntlzd [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rldicl [[REG3:r[0-9]+]], [[REG2]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8, !tbaa !2
+  ret void
+}
+
+define void @test_llequll_z_store(i64 %a)  {
+; CHECK-LABEL: test_llequll_z_store:
+; CHECK:    cntlzd [[REG1:r[0-9]+]], r3
+; CHECK:    rldicl [[REG2:r[0-9]+]], [[REG1]], 58, 63
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"long long", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
Index: test/CodeGen/PowerPC/testComparesllequs.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/testComparesllequs.ll
@@ -0,0 +1,61 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b)  {
+; CHECK-LABEL: test_llequs:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llequs_z(i16 zeroext %a)  {
+; CHECK-LABEL: test_llequs_z:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b)  {
+; CHECK-LABEL: test_llequs_store:
+; CHECK:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:    cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK:    rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2, !tbaa !2
+  ret void
+}
+
+define void @test_llequs_z_store(i16 zeroext %a)  {
+; CHECK-LABEL: test_llequs_z_store:
+; CHECK:    cntlzw [[REG1:r[0-9]+]], r3
+; CHECK:    rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2, !tbaa !2
+  ret void
+}
+
+attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 5.0.0 (git@github.ibm.com:llvm/clang.git 879a2c4c5e8c11a0fab7c346212c39eaee3da9a6) (llvm/llvm.git e19a446fdba71ad318dce3ef7b421e7f1a15095f)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"short", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}