Index: lib/Target/AMDGPU/SIMachineScheduler.cpp =================================================================== --- lib/Target/AMDGPU/SIMachineScheduler.cpp +++ lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -974,12 +974,7 @@ for (unsigned SUNum : DAG->BottomUpIndex2SU) { SUnit *SU = &DAG->SUnits[SUNum]; unsigned color = CurrentColoring[SU->NodeNum]; - std::map::iterator Pos = ColorCount.find(color); - if (Pos != ColorCount.end()) { - ++ColorCount[color]; - } else { - ColorCount[color] = 1; - } + ++ColorCount[color]; } for (unsigned SUNum : DAG->BottomUpIndex2SU) { @@ -1331,13 +1326,7 @@ continue; int PredID = BlocksStruct.TopDownIndex2Block[topoInd]; - std::map::iterator RegPos = - LiveOutRegsNumUsages[PredID].find(Reg); - if (RegPos != LiveOutRegsNumUsages[PredID].end()) { - ++LiveOutRegsNumUsages[PredID][Reg]; - } else { - LiveOutRegsNumUsages[PredID][Reg] = 1; - } + ++LiveOutRegsNumUsages[PredID][Reg]; } } @@ -1377,12 +1366,8 @@ } } - if (!Found) { - if (LiveRegsConsumers.find(Reg) == LiveRegsConsumers.end()) - LiveRegsConsumers[Reg] = 1; - else - ++LiveRegsConsumers[Reg]; - } + if (!Found) + ++LiveRegsConsumers[Reg]; } } @@ -1578,12 +1563,10 @@ LiveOutRegsNumUsages[Block->getID()].begin(), E = LiveOutRegsNumUsages[Block->getID()].end(); RegI != E; ++RegI) { std::pair RegP = *RegI; - if (LiveRegsConsumers.find(RegP.first) == LiveRegsConsumers.end()) - LiveRegsConsumers[RegP.first] = RegP.second; - else { - assert(LiveRegsConsumers[RegP.first] == 0); - LiveRegsConsumers[RegP.first] += RegP.second; - } + // We produce this register, thus it must not be previously alive. + assert(LiveRegsConsumers.find(RegP.first) == LiveRegsConsumers.end() || + LiveRegsConsumers[RegP.first] == 0); + LiveRegsConsumers[RegP.first] += RegP.second; } if (LastPosHighLatencyParentScheduled[Block->getID()] > (unsigned)LastPosWaitedHighLatency)