Index: lib/CodeGen/ExecutionDepsFix.cpp =================================================================== --- lib/CodeGen/ExecutionDepsFix.cpp +++ lib/CodeGen/ExecutionDepsFix.cpp @@ -721,7 +721,7 @@ // Kill off any remaining uses that don't match available, and build a list of // incoming DomainValues that we want to merge. - SmallVector Regs; + SmallVector Regs; for (SmallVectorImpl::iterator i=used.begin(), e=used.end(); i!=e; ++i) { int rx = *i; assert(LiveRegs && "no space allocated for live registers"); @@ -733,15 +733,15 @@ } // Sorted insertion. bool Inserted = false; - for (SmallVectorImpl::iterator i = Regs.begin(), e = Regs.end(); - i != e && !Inserted; ++i) { - if (LR.Def < i->Def) { + for (SmallVectorImpl::iterator i = Regs.begin(), + e = Regs.end(); i != e && !Inserted; ++i) { + if (LR.Def < (*i)->Def) { Inserted = true; - Regs.insert(i, LR); + Regs.insert(i, &LR); } } if (!Inserted) - Regs.push_back(LR); + Regs.push_back(&LR); } // doms are now sorted in order of appearance. Try to merge them all, giving @@ -749,14 +749,14 @@ DomainValue *dv = nullptr; while (!Regs.empty()) { if (!dv) { - dv = Regs.pop_back_val().Value; + dv = Regs.pop_back_val()->Value; // Force the first dv to match the current instruction. dv->AvailableDomains = dv->getCommonDomains(available); assert(dv->AvailableDomains && "Domain should have been filtered"); continue; } - DomainValue *Latest = Regs.pop_back_val().Value; + DomainValue *Latest = Regs.pop_back_val()->Value; // Skip already merged values. if (Latest == dv || Latest->Next) continue; Index: test/CodeGen/X86/pr30284.ll =================================================================== --- /dev/null +++ test/CodeGen/X86/pr30284.ll @@ -0,0 +1,21 @@ +; ModuleID = 'bugpoint-reduced-simplified.bc' +source_filename = "bugpoint-output-21f4d9f.bc" +target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" +target triple = "i386-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @f_f___un_3C_unf_3E_un_3C_unf_3E_() #0 { +allocas: + %a_load22 = load <16 x i64>, <16 x i64>* null, align 1 + %bitop = or <16 x i64> %a_load22, + %v.i = load <16 x i64>, <16 x i64>* null + %v1.i41 = select <16 x i1> undef, <16 x i64> %bitop, <16 x i64> %v.i + store <16 x i64> %v1.i41, <16 x i64>* null + unreachable +} + +attributes #0 = { nounwind } + +!llvm.ident = !{!0} + +!0 = !{!"clang version 4.0.0 (trunk 278097)"}