Index: lib/Target/AMDGPU/AMDGPUSubtarget.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -74,15 +74,19 @@
     TrapHandlerAbiHsa = 1
   };
 
-  enum TrapCode {
-    TrapCodeBreakPoint = 0,
-    TrapCodeLLVMTrap = 1,
-    TrapCodeLLVMDebugTrap = 2,
-    TrapCodeHSADebugTrap = 3
+  enum TrapID {
+    TrapIDHardwareReserved = 0,
+    TrapIDHSADebugTrap = 1,
+    TrapIDLLVMTrap = 2,
+    TrapIDLLVMDebugTrap = 3,
+    TrapIDDebugBreakpoint = 7,
+    TrapIDDebugReserved8 = 8,
+    TrapIDDebugReservedFE = 0xfe,
+    TrapIDDebugReservedFF = 0xff
   };
 
   enum TrapRegValues {
-    TrapCodeLLVMTrapRegValue = 1
+    LLVMTrapHandlerRegValue = 1
   };
 
 protected:
Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1802,7 +1802,7 @@
         .addReg(AMDGPU::SGPR0_SGPR1, RegState::Implicit);
     } else {
       switch (TrapType) {
-      case SISubtarget::TrapCodeLLVMTrap:
+      case SISubtarget::TrapIDLLVMTrap:
         BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_ENDPGM));
         break;
       case SISubtarget::TrapCodeLLVMDebugTrap: {
Index: lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.td
+++ lib/Target/AMDGPU/SIInstrInfo.td
@@ -631,9 +631,9 @@
   int NONE = 0;
 }
 
-def TRAPTYPE {
-  int LLVM_TRAP = 1;
-  int LLVM_DEBUG_TRAP = 2;
+def TRAPID{
+  int LLVM_TRAP = 2;
+  int LLVM_DEBUG_TRAP = 3;
 }
 
 //===----------------------------------------------------------------------===//
Index: lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- lib/Target/AMDGPU/SIInstructions.td
+++ lib/Target/AMDGPU/SIInstructions.td
@@ -391,12 +391,12 @@
 let Predicates = [isGCN] in {
 def : Pat<
   (trap),
-  (S_TRAP_PSEUDO TRAPTYPE.LLVM_TRAP)
+  (S_TRAP_PSEUDO TRAPID.LLVM_TRAP)
 >;
 
 def : Pat<
   (debugtrap),
-  (S_TRAP_PSEUDO TRAPTYPE.LLVM_DEBUG_TRAP)
+  (S_TRAP_PSEUDO TRAPID.LLVM_DEBUG_TRAP)
 >;
 
 def : Pat<
Index: test/CodeGen/AMDGPU/trap.ll
===================================================================
--- test/CodeGen/AMDGPU/trap.ll
+++ test/CodeGen/AMDGPU/trap.ll
@@ -28,7 +28,7 @@
 ; GCN-LABEL: {{^}}hsa_trap:
 ; HSA-TRAP: enable_trap_handler = 1
 ; HSA-TRAP: s_mov_b64 s[0:1], s[4:5]
-; HSA-TRAP: s_trap 1
+; HSA-TRAP: s_trap 2
 
 ; for llvm.trap in hsa path without ABI, direct generate s_endpgm instruction without any warning information
 ; NO-HSA-TRAP: enable_trap_handler = 0
@@ -55,7 +55,7 @@
 ; GCN-LABEL: {{^}}hsa_debugtrap:
 ; HSA-TRAP: enable_trap_handler = 1
 ; HSA-TRAP: s_mov_b64 s[0:1], s[4:5]
-; HSA-TRAP: s_trap 2
+; HSA-TRAP: s_trap 3
 
 ; for llvm.debugtrap in non-hsa path without ABI, generate a warning and a s_endpgm instruction
 ; NO-HSA-TRAP: enable_trap_handler = 0