Index: include/llvm/Target/TargetInstrInfo.h =================================================================== --- include/llvm/Target/TargetInstrInfo.h +++ include/llvm/Target/TargetInstrInfo.h @@ -792,7 +792,8 @@ MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { llvm_unreachable("Target didn't implement " "TargetInstrInfo::storeRegToStackSlot!"); } Index: lib/CodeGen/InlineSpiller.cpp =================================================================== --- lib/CodeGen/InlineSpiller.cpp +++ lib/CodeGen/InlineSpiller.cpp @@ -386,7 +386,7 @@ } // Insert spill without kill flag immediately after def. TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot, - MRI.getRegClass(SrcReg), &TRI); + MRI.getRegClass(SrcReg), &TRI, MachineInstr::NoFlags); --MII; // Point to store instruction. LIS.InsertMachineInstrInMaps(*MII); DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII); @@ -863,7 +863,7 @@ MachineInstrSpan MIS(MI); TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot, - MRI.getRegClass(NewVReg), &TRI); + MRI.getRegClass(NewVReg), &TRI, MachineInstr::NoFlags); LIS.InsertMachineInstrRangeInMaps(std::next(MI), MIS.end()); @@ -1436,7 +1436,7 @@ unsigned LiveReg = Insert.second; MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, *BB); TII.storeRegToStackSlot(*BB, MI, LiveReg, false, Slot, - MRI.getRegClass(LiveReg), &TRI); + MRI.getRegClass(LiveReg), &TRI, MachineInstr::NoFlags); LIS.InsertMachineInstrRangeInMaps(std::prev(MI), MI); ++NumSpills; } Index: lib/CodeGen/PrologEpilogInserter.cpp =================================================================== --- lib/CodeGen/PrologEpilogInserter.cpp +++ lib/CodeGen/PrologEpilogInserter.cpp @@ -489,7 +489,7 @@ unsigned Reg = CSI[i].getReg(); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.storeRegToStackSlot(*SaveBlock, I, Reg, true, CSI[i].getFrameIdx(), - RC, TRI); + RC, TRI, MachineInstr::FrameSetup); } } // Update the live-in information of all the blocks up to the save point. Index: lib/CodeGen/RegAllocFast.cpp =================================================================== --- lib/CodeGen/RegAllocFast.cpp +++ lib/CodeGen/RegAllocFast.cpp @@ -294,7 +294,7 @@ const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg); int FI = getStackSpaceFor(LRI->VirtReg, RC); DEBUG(dbgs() << " to stack slot #" << FI << "\n"); - TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); + TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI, MachineInstr::NoFlags); ++NumStores; // Update statistics // If this register is used by DBG_VALUE then insert new DBG_VALUE to Index: lib/CodeGen/RegisterScavenging.cpp =================================================================== --- lib/CodeGen/RegisterScavenging.cpp +++ lib/CodeGen/RegisterScavenging.cpp @@ -437,7 +437,7 @@ report_fatal_error(Msg.c_str()); } TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex, - RC, TRI); + RC, TRI, MachineInstr::NoFlags); MachineBasicBlock::iterator II = std::prev(I); unsigned FIOperandNum = getFrameIndexOperandNum(*II); Index: lib/CodeGen/TargetInstrInfo.cpp =================================================================== --- lib/CodeGen/TargetInstrInfo.cpp +++ lib/CodeGen/TargetInstrInfo.cpp @@ -584,7 +584,7 @@ MachineBasicBlock::iterator Pos = MI; if (Flags == MachineMemOperand::MOStore) - storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); + storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI, MachineInstr::NoFlags); else loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI); return &*--Pos; Index: lib/Target/AArch64/AArch64InstrInfo.h =================================================================== --- lib/Target/AArch64/AArch64InstrInfo.h +++ lib/Target/AArch64/AArch64InstrInfo.h @@ -154,7 +154,8 @@ MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, Index: lib/Target/AArch64/AArch64InstrInfo.cpp =================================================================== --- lib/Target/AArch64/AArch64InstrInfo.cpp +++ lib/Target/AArch64/AArch64InstrInfo.cpp @@ -2255,7 +2255,8 @@ void AArch64InstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (MBBI != MBB.end()) DL = MBBI->getDebugLoc(); @@ -2349,7 +2350,8 @@ const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc)) .addReg(SrcReg, getKillRegState(isKill)) - .addFrameIndex(FI); + .addFrameIndex(FI) + .setMIFlags(Flags); if (Offset) MI.addImm(0); @@ -2601,7 +2603,7 @@ "Mismatched register size in non subreg COPY"); if (IsSpill) storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex, - getRegClass(SrcReg), &TRI); + getRegClass(SrcReg), &TRI, MachineInstr::NoFlags); else loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, getRegClass(DstReg), &TRI); @@ -2651,7 +2653,7 @@ if (unsigned WidenedSrcReg = TRI.getMatchingSuperReg(SrcReg, SpillSubreg, SpillRC)) { storeRegToStackSlot(MBB, InsertPt, WidenedSrcReg, SrcMO.isKill(), - FrameIndex, SpillRC, &TRI); + FrameIndex, SpillRC, &TRI, MachineInstr::NoFlags); return &*--InsertPt; } } Index: lib/Target/AMDGPU/SIFrameLowering.cpp =================================================================== --- lib/Target/AMDGPU/SIFrameLowering.cpp +++ lib/Target/AMDGPU/SIFrameLowering.cpp @@ -419,7 +419,7 @@ // Spill work group ID. int WorkGroupIDObjectIdx = MFI->getDebuggerWorkGroupIDStackObjectIndex(i); TII->storeRegToStackSlot(MBB, I, WorkGroupIDVGPR, false, - WorkGroupIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI); + WorkGroupIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI, MachineInstr::FrameSetup); // Get work item ID VGPR, and make it live-in again. unsigned WorkItemIDVGPR = MFI->getWorkItemIDVGPR(i); @@ -429,6 +429,6 @@ // Spill work item ID. int WorkItemIDObjectIdx = MFI->getDebuggerWorkItemIDStackObjectIndex(i); TII->storeRegToStackSlot(MBB, I, WorkItemIDVGPR, false, - WorkItemIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI); + WorkItemIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI, MachineInstr::FrameSetup); } } Index: lib/Target/AMDGPU/SIInstrInfo.h =================================================================== --- lib/Target/AMDGPU/SIInstrInfo.h +++ lib/Target/AMDGPU/SIInstrInfo.h @@ -144,7 +144,8 @@ MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, Index: lib/Target/AMDGPU/SIInstrInfo.cpp =================================================================== --- lib/Target/AMDGPU/SIInstrInfo.cpp +++ lib/Target/AMDGPU/SIInstrInfo.cpp @@ -514,7 +514,8 @@ unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { MachineFunction *MF = MBB.getParent(); SIMachineFunctionInfo *MFI = MF->getInfo(); MachineFrameInfo &FrameInfo = MF->getFrameInfo(); @@ -547,7 +548,8 @@ .addFrameIndex(FrameIndex) // addr .addMemOperand(MMO) .addReg(MFI->getScratchRSrcReg(), RegState::Implicit) - .addReg(MFI->getScratchWaveOffsetReg(), RegState::Implicit); + .addReg(MFI->getScratchWaveOffsetReg(), RegState::Implicit) + .setMIFlags(Flags); // Add the scratch resource registers as implicit uses because we may end up // needing them, and need to ensure that the reserved registers are // correctly handled. @@ -565,7 +567,8 @@ Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to" " spill register"); BuildMI(MBB, MI, DL, get(AMDGPU::KILL)) - .addReg(SrcReg); + .addReg(SrcReg) + .setMIFlags(Flags); return; } @@ -580,7 +583,8 @@ .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset .addImm(0) // offset - .addMemOperand(MMO); + .addMemOperand(MMO) + .setMIFlags(Flags); } static unsigned getSGPRSpillRestoreOpcode(unsigned Size) { Index: lib/Target/ARM/ARMBaseInstrInfo.h =================================================================== --- lib/Target/ARM/ARMBaseInstrInfo.h +++ lib/Target/ARM/ARMBaseInstrInfo.h @@ -193,7 +193,8 @@ MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Index: lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- lib/Target/ARM/ARMBaseInstrInfo.cpp +++ lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -894,7 +894,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); MachineFunction &MF = *MBB.getParent(); @@ -913,14 +914,16 @@ .addFrameIndex(FI) .addImm(0) .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); + .add(predOps(ARMCC::AL)) + .setMIFlags(Flags); } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(ARM::VSTRS)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI) .addImm(0) .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); + .add(predOps(ARMCC::AL)) + .setMIFlags(Flags); } else llvm_unreachable("Unknown reg class!"); break; @@ -931,10 +934,12 @@ .addFrameIndex(FI) .addImm(0) .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); + .add(predOps(ARMCC::AL)) + .setMIFlags(Flags); } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { if (Subtarget.hasV5TEOps()) { - MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); + MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)) + .setMIFlags(Flags); AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO) @@ -945,7 +950,8 @@ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STMIA)) .addFrameIndex(FI) .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); + .add(predOps(ARMCC::AL)) + .setMIFlags(Flags); AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); } @@ -961,13 +967,15 @@ .addImm(16) .addReg(SrcReg, getKillRegState(isKill)) .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); + .add(predOps(ARMCC::AL)) + .setMIFlags(Flags); } else { BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI) .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); + .add(predOps(ARMCC::AL)) + .setMIFlags(Flags); } } else llvm_unreachable("Unknown reg class!"); @@ -981,12 +989,14 @@ .addImm(16) .addReg(SrcReg, getKillRegState(isKill)) .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); + .add(predOps(ARMCC::AL)) + .setMIFlags(Flags); } else { MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) .addFrameIndex(FI) .add(predOps(ARMCC::AL)) - .addMemOperand(MMO); + .addMemOperand(MMO) + .setMIFlags(Flags); MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); @@ -1004,12 +1014,14 @@ .addImm(16) .addReg(SrcReg, getKillRegState(isKill)) .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); + .add(predOps(ARMCC::AL)) + .setMIFlags(Flags); } else { MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) .addFrameIndex(FI) .add(predOps(ARMCC::AL)) - .addMemOperand(MMO); + .addMemOperand(MMO) + .setMIFlags(Flags); MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); @@ -1023,7 +1035,8 @@ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) .addFrameIndex(FI) .add(predOps(ARMCC::AL)) - .addMemOperand(MMO); + .addMemOperand(MMO) + .setMIFlags(Flags); MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); Index: lib/Target/ARM/Thumb1InstrInfo.h =================================================================== --- lib/Target/ARM/Thumb1InstrInfo.h +++ lib/Target/ARM/Thumb1InstrInfo.h @@ -45,7 +45,8 @@ MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Index: lib/Target/ARM/Thumb1InstrInfo.cpp =================================================================== --- lib/Target/ARM/Thumb1InstrInfo.cpp +++ lib/Target/ARM/Thumb1InstrInfo.cpp @@ -74,7 +74,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { assert((RC == &ARM::tGPRRegClass || (TargetRegisterInfo::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) && "Unknown regclass!"); @@ -95,7 +96,8 @@ .addFrameIndex(FI) .addImm(0) .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); + .add(predOps(ARMCC::AL)) + .setMIFlags(Flags); } } Index: lib/Target/ARM/Thumb2InstrInfo.h =================================================================== --- lib/Target/ARM/Thumb2InstrInfo.h +++ lib/Target/ARM/Thumb2InstrInfo.h @@ -47,7 +47,8 @@ MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Index: lib/Target/ARM/Thumb2InstrInfo.cpp =================================================================== --- lib/Target/ARM/Thumb2InstrInfo.cpp +++ lib/Target/ARM/Thumb2InstrInfo.cpp @@ -126,7 +126,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -144,7 +145,8 @@ .addFrameIndex(FI) .addImm(0) .addMemOperand(MMO) - .add(predOps(ARMCC::AL)); + .add(predOps(ARMCC::AL)) + .setMIFlags(Flags); return; } @@ -160,11 +162,12 @@ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); + MIB.setMIFlags(Flags); MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL)); return; } - ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI); + ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI, Flags); } void Thumb2InstrInfo:: Index: lib/Target/BPF/BPFInstrInfo.h =================================================================== --- lib/Target/BPF/BPFInstrInfo.h +++ lib/Target/BPF/BPFInstrInfo.h @@ -38,7 +38,8 @@ MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, Index: lib/Target/BPF/BPFInstrInfo.cpp =================================================================== --- lib/Target/BPF/BPFInstrInfo.cpp +++ lib/Target/BPF/BPFInstrInfo.cpp @@ -44,7 +44,8 @@ MachineBasicBlock::iterator I, unsigned SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -53,7 +54,8 @@ BuildMI(MBB, I, DL, get(BPF::STD)) .addReg(SrcReg, getKillRegState(IsKill)) .addFrameIndex(FI) - .addImm(0); + .addImm(0) + .setMIFlags(Flags); else llvm_unreachable("Can't store this register to stack slot"); } Index: lib/Target/Hexagon/HexagonFrameLowering.cpp =================================================================== --- lib/Target/Hexagon/HexagonFrameLowering.cpp +++ lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1171,7 +1171,7 @@ bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg); int FI = CSI[i].getFrameIdx(); const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); - HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI); + HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI, MachineInstr::FrameSetup); if (IsKill) MBB.addLiveIn(Reg); } @@ -1579,7 +1579,7 @@ .addReg(TmpR0, RegState::Kill); auto *HRI = B.getParent()->getSubtarget().getRegisterInfo(); - HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI); + HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI, MachineInstr::FrameSetup); expandStoreVec(B, std::prev(It), MRI, HII, NewRegs); NewRegs.push_back(TmpR0); Index: lib/Target/Hexagon/HexagonInstrInfo.h =================================================================== --- lib/Target/Hexagon/HexagonInstrInfo.h +++ lib/Target/Hexagon/HexagonInstrInfo.h @@ -177,7 +177,8 @@ MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; /// Load the specified register of the given register class from the specified /// stack frame index. The load instruction is to be added to the given Index: lib/Target/Hexagon/HexagonInstrInfo.cpp =================================================================== --- lib/Target/Hexagon/HexagonInstrInfo.cpp +++ lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -863,7 +863,8 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, - const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { + const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { DebugLoc DL = MBB.findDebugLoc(I); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); @@ -877,51 +878,61 @@ if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); + .addReg(SrcReg, KillFlag).addMemOperand(MMO) + .setMIFlags(Flags); } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); + .addReg(SrcReg, KillFlag).addMemOperand(MMO) + .setMIFlags(Flags); } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::STriw_pred)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); + .addReg(SrcReg, KillFlag).addMemOperand(MMO) + .setMIFlags(Flags); } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::STriw_mod)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); + .addReg(SrcReg, KillFlag).addMemOperand(MMO) + .setMIFlags(Flags); } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai_128B)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); + .addReg(SrcReg, KillFlag).addMemOperand(MMO) + .setMIFlags(Flags); } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); + .addReg(SrcReg, KillFlag).addMemOperand(MMO) + .setMIFlags(Flags); } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) { unsigned Opc = Align < 128 ? Hexagon::V6_vS32Ub_ai_128B : Hexagon::V6_vS32b_ai_128B; BuildMI(MBB, I, DL, get(Opc)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); + .addReg(SrcReg, KillFlag).addMemOperand(MMO) + .setMIFlags(Flags); } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) { unsigned Opc = Align < 64 ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32b_ai; BuildMI(MBB, I, DL, get(Opc)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); + .addReg(SrcReg, KillFlag).addMemOperand(MMO) + .setMIFlags(Flags); } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) { unsigned Opc = Align < 64 ? Hexagon::PS_vstorerwu_ai : Hexagon::PS_vstorerw_ai; BuildMI(MBB, I, DL, get(Opc)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); + .addReg(SrcReg, KillFlag).addMemOperand(MMO) + .setMIFlags(Flags); } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) { unsigned Opc = Align < 128 ? Hexagon::PS_vstorerwu_ai_128B : Hexagon::PS_vstorerw_ai_128B; BuildMI(MBB, I, DL, get(Opc)) .addFrameIndex(FI).addImm(0) - .addReg(SrcReg, KillFlag).addMemOperand(MMO); + .addReg(SrcReg, KillFlag).addMemOperand(MMO) + .setMIFlags(Flags); } else { llvm_unreachable("Unimplemented"); } Index: lib/Target/Lanai/LanaiInstrInfo.h =================================================================== --- lib/Target/Lanai/LanaiInstrInfo.h +++ lib/Target/Lanai/LanaiInstrInfo.h @@ -56,7 +56,8 @@ MachineBasicBlock::iterator Position, unsigned SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, - const TargetRegisterInfo *RegisterInfo) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, Index: lib/Target/Lanai/LanaiInstrInfo.cpp =================================================================== --- lib/Target/Lanai/LanaiInstrInfo.cpp +++ lib/Target/Lanai/LanaiInstrInfo.cpp @@ -51,7 +51,8 @@ MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, - const TargetRegisterInfo * /*RegisterInfo*/) const { + const TargetRegisterInfo * /*RegisterInfo*/, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (Position != MBB.end()) { DL = Position->getDebugLoc(); @@ -64,7 +65,8 @@ .addReg(SourceRegister, getKillRegState(IsKill)) .addFrameIndex(FrameIndex) .addImm(0) - .addImm(LPAC::ADD); + .addImm(LPAC::ADD) + .setMIFlags(Flags); } void LanaiInstrInfo::loadRegFromStackSlot( Index: lib/Target/MSP430/MSP430InstrInfo.h =================================================================== --- lib/Target/MSP430/MSP430InstrInfo.h +++ lib/Target/MSP430/MSP430InstrInfo.h @@ -61,7 +61,8 @@ unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, Index: lib/Target/MSP430/MSP430InstrInfo.cpp =================================================================== --- lib/Target/MSP430/MSP430InstrInfo.cpp +++ lib/Target/MSP430/MSP430InstrInfo.cpp @@ -38,7 +38,8 @@ MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); MachineFunction &MF = *MBB.getParent(); @@ -52,11 +53,13 @@ if (RC == &MSP430::GR16RegClass) BuildMI(MBB, MI, DL, get(MSP430::MOV16mr)) .addFrameIndex(FrameIdx).addImm(0) - .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); + .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO) + .setMIFlags(Flags); else if (RC == &MSP430::GR8RegClass) BuildMI(MBB, MI, DL, get(MSP430::MOV8mr)) .addFrameIndex(FrameIdx).addImm(0) - .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); + .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO) + .setMIFlags(Flags); else llvm_unreachable("Cannot store this register to stack slot!"); } Index: lib/Target/Mips/Mips16InstrInfo.h =================================================================== --- lib/Target/Mips/Mips16InstrInfo.h +++ lib/Target/Mips/Mips16InstrInfo.h @@ -52,7 +52,8 @@ unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - int64_t Offset) const override; + int64_t Offset, + MachineInstr::MIFlag Flags) const override; void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Index: lib/Target/Mips/Mips16InstrInfo.cpp =================================================================== --- lib/Target/Mips/Mips16InstrInfo.cpp +++ lib/Target/Mips/Mips16InstrInfo.cpp @@ -93,7 +93,8 @@ unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - int64_t Offset) const { + int64_t Offset, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); @@ -103,7 +104,7 @@ assert(Opc && "Register class not handled!"); BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)). addFrameIndex(FI).addImm(Offset) - .addMemOperand(MMO); + .addMemOperand(MMO).setMIFlags(Flags); } void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB, Index: lib/Target/Mips/MipsInstrInfo.h =================================================================== --- lib/Target/Mips/MipsInstrInfo.h +++ lib/Target/Mips/MipsInstrInfo.h @@ -100,8 +100,9 @@ MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override { - storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override { + storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0, Flags); } void loadRegFromStackSlot(MachineBasicBlock &MBB, @@ -117,7 +118,8 @@ unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - int64_t Offset) const = 0; + int64_t Offset, + MachineInstr::MIFlag Flags) const = 0; virtual void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Index: lib/Target/Mips/MipsSEFrameLowering.cpp =================================================================== --- lib/Target/Mips/MipsSEFrameLowering.cpp +++ lib/Target/Mips/MipsSEFrameLowering.cpp @@ -192,7 +192,7 @@ BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) .addReg(Src, getKillRegState(I->getOperand(0).isKill())); - TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); + TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0, MachineInstr::NoFlags); } void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I, @@ -237,9 +237,9 @@ DebugLoc DL = I->getDebugLoc(); BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); - TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0); + TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0, MachineInstr::NoFlags); BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); - TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); + TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize, MachineInstr::NoFlags); } bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) { @@ -320,9 +320,9 @@ if (!Subtarget.isLittle()) std::swap(LoReg, HiReg); TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, - &RegInfo, 0); + &RegInfo, 0, MachineInstr::NoFlags); TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, - &RegInfo, 4); + &RegInfo, 4, MachineInstr::NoFlags); TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0); return true; } @@ -380,7 +380,7 @@ // We re-use the same spill slot each time so that the stack frame doesn't // grow too much in functions with a large number of moves. int FI = MF.getInfo()->getMoveF64ViaSpillFI(RC); - TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0); + TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0, MachineInstr::NoFlags); TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset); return true; } @@ -504,7 +504,7 @@ if (!MBB.isLiveIn(ABI.GetEhDataReg(I))) MBB.addLiveIn(ABI.GetEhDataReg(I)); TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false, - MipsFI->getEhDataRegFI(I), RC, &RegInfo); + MipsFI->getEhDataRegFI(I), RC, &RegInfo, MachineInstr::FrameSetup); } // Emit .cfi_offset directives for eh data registers. @@ -611,7 +611,8 @@ STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false, MipsFI->getISRRegFI(0), PtrRC, - STI.getRegisterInfo(), 0); + STI.getRegisterInfo(), 0, + MachineInstr::FrameSetup); // Fetch and Spill Status MBB.addLiveIn(Mips::COP012); @@ -622,7 +623,8 @@ STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false, MipsFI->getISRRegFI(1), PtrRC, - STI.getRegisterInfo(), 0); + STI.getRegisterInfo(), 0, + MachineInstr::FrameSetup); // Build the configuration for disabling lower priority interrupts. Non EIC // interrupts need to be masked off with zero, EIC from the Cause register. @@ -829,7 +831,7 @@ bool IsKill = !IsRAAndRetAddrIsTaken; const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, - CSI[i].getFrameIdx(), RC, TRI); + CSI[i].getFrameIdx(), RC, TRI, MachineInstr::FrameSetup); } return true; Index: lib/Target/Mips/MipsSEInstrInfo.h =================================================================== --- lib/Target/Mips/MipsSEInstrInfo.h +++ lib/Target/Mips/MipsSEInstrInfo.h @@ -52,7 +52,8 @@ unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - int64_t Offset) const override; + int64_t Offset, + MachineInstr::MIFlag Flags) const override; void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Index: lib/Target/Mips/MipsSEInstrInfo.cpp =================================================================== --- lib/Target/Mips/MipsSEInstrInfo.cpp +++ lib/Target/Mips/MipsSEInstrInfo.cpp @@ -183,7 +183,7 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - int64_t Offset) const { + int64_t Offset, MachineInstr::MIFlag Flags) const { DebugLoc DL; MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); @@ -229,23 +229,23 @@ const Function *Func = MBB.getParent()->getFunction(); if (Func->hasFnAttribute("interrupt")) { if (Mips::HI32RegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); + BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0).setMIFlags(Flags); SrcReg = Mips::K0; } else if (Mips::HI64RegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64); + BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64).setMIFlags(Flags); SrcReg = Mips::K0_64; } else if (Mips::LO32RegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); + BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0).setMIFlags(Flags); SrcReg = Mips::K0; } else if (Mips::LO64RegClass.hasSubClassEq(RC)) { - BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64); + BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64).setMIFlags(Flags); SrcReg = Mips::K0_64; } } assert(Opc && "Register class not handled!"); BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) - .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); + .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO).setMIFlags(Flags); } void MipsSEInstrInfo:: Index: lib/Target/PowerPC/PPCFrameLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCFrameLowering.cpp +++ lib/Target/PowerPC/PPCFrameLowering.cpp @@ -1978,7 +1978,7 @@ } else { const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.storeRegToStackSlot(MBB, MI, Reg, true, - CSI[i].getFrameIdx(), RC, TRI); + CSI[i].getFrameIdx(), RC, TRI, MachineInstr::FrameSetup); } } return true; Index: lib/Target/PowerPC/PPCInstrInfo.h =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.h +++ lib/Target/PowerPC/PPCInstrInfo.h @@ -81,7 +81,8 @@ unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs, - bool &NonRI, bool &SpillsVRS) const; + bool &NonRI, bool &SpillsVRS, + MachineInstr::MIFlag Flags) const; bool LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, @@ -200,7 +201,8 @@ MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Index: lib/Target/PowerPC/PPCInstrInfo.cpp =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.cpp +++ lib/Target/PowerPC/PPCInstrInfo.cpp @@ -946,7 +946,8 @@ int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs, - bool &NonRI, bool &SpillsVRS) const{ + bool &NonRI, bool &SpillsVRS, + MachineInstr::MIFlag Flags) const{ // Note: If additional store instructions are added here, // update isStoreToStackSlot. @@ -955,61 +956,71 @@ PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); return true; } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); return true; } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); NonRI = true; } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { unsigned Op = Subtarget.hasP9Vector() ? PPC::STXVX : PPC::STXVD2X; NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); NonRI = true; } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf64 : PPC::STXSDX; NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); NonRI = true; } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf32 : PPC::STXSSPX; NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); NonRI = true; } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { @@ -1017,25 +1028,29 @@ "VRSAVE only needs spill/restore on Darwin"); NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); SpillsVRS = true; } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); NonRI = true; } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); NonRI = true; } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb)) .addReg(SrcReg, - getKillRegState(isKill)), + getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx)); NonRI = true; } else { @@ -1050,7 +1065,8 @@ MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { MachineFunction &MF = *MBB.getParent(); SmallVector NewMIs; @@ -1068,7 +1084,7 @@ bool NonRI = false, SpillsVRS = false; if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs, - NonRI, SpillsVRS)) + NonRI, SpillsVRS, Flags)) FuncInfo->setSpillsCR(); if (SpillsVRS) Index: lib/Target/Sparc/SparcInstrInfo.h =================================================================== --- lib/Target/Sparc/SparcInstrInfo.h +++ lib/Target/Sparc/SparcInstrInfo.h @@ -89,7 +89,8 @@ MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Index: lib/Target/Sparc/SparcInstrInfo.cpp =================================================================== --- lib/Target/Sparc/SparcInstrInfo.cpp +++ lib/Target/Sparc/SparcInstrInfo.cpp @@ -396,7 +396,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -409,24 +410,30 @@ // On the order of operands here: think "[FrameIdx + 0] = SrcReg". if (RC == &SP::I64RegsRegClass) BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); + .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO) + .setMIFlags(Flags); else if (RC == &SP::IntRegsRegClass) BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); + .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO) + .setMIFlags(Flags); else if (RC == &SP::IntPairRegClass) BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); + .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO) + .setMIFlags(Flags); else if (RC == &SP::FPRegsRegClass) BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); + .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO) + .setMIFlags(Flags); else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); + .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO) + .setMIFlags(Flags); else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) // Use STQFri irrespective of its legality. If STQ is not legal, it will be // lowered into two STDs in eliminateFrameIndex. BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); + .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO) + .setMIFlags(Flags); else llvm_unreachable("Can't store this register to stack slot"); } Index: lib/Target/SystemZ/SystemZFrameLowering.cpp =================================================================== --- lib/Target/SystemZ/SystemZFrameLowering.cpp +++ lib/Target/SystemZ/SystemZFrameLowering.cpp @@ -210,7 +210,7 @@ if (SystemZ::FP64BitRegClass.contains(Reg)) { MBB.addLiveIn(Reg); TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(), - &SystemZ::FP64BitRegClass, TRI); + &SystemZ::FP64BitRegClass, TRI, MachineInstr::FrameSetup); } } Index: lib/Target/SystemZ/SystemZInstrInfo.h =================================================================== --- lib/Target/SystemZ/SystemZInstrInfo.h +++ lib/Target/SystemZ/SystemZInstrInfo.h @@ -235,7 +235,8 @@ MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIdx, Index: lib/Target/SystemZ/SystemZInstrInfo.cpp =================================================================== --- lib/Target/SystemZ/SystemZInstrInfo.cpp +++ lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -875,7 +875,8 @@ void SystemZInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); // Callers may expect a single instruction, so keep 128-bit moves @@ -883,7 +884,8 @@ unsigned LoadOpcode, StoreOpcode; getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode); addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode)) - .addReg(SrcReg, getKillRegState(isKill)), + .addReg(SrcReg, getKillRegState(isKill)) + .setMIFlags(Flags), FrameIdx); } Index: lib/Target/X86/X86FrameLowering.cpp =================================================================== --- lib/Target/X86/X86FrameLowering.cpp +++ lib/Target/X86/X86FrameLowering.cpp @@ -1957,7 +1957,7 @@ const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC, - TRI); + TRI, MachineInstr::FrameSetup); --MI; MI->setFlag(MachineInstr::FrameSetup); ++MI; Index: lib/Target/X86/X86InstrInfo.h =================================================================== --- lib/Target/X86/X86InstrInfo.h +++ lib/Target/X86/X86InstrInfo.h @@ -354,7 +354,8 @@ MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl &Addr, Index: lib/Target/X86/X86InstrInfo.cpp =================================================================== --- lib/Target/X86/X86InstrInfo.cpp +++ lib/Target/X86/X86InstrInfo.cpp @@ -6712,7 +6712,8 @@ MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const { + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { const MachineFunction &MF = *MBB.getParent(); assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= RC->getSize() && "Stack slot too small for store"); @@ -6723,7 +6724,7 @@ unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); DebugLoc DL = MBB.findDebugLoc(MI); addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) - .addReg(SrcReg, getKillRegState(isKill)); + .addReg(SrcReg, getKillRegState(isKill)).setMIFlags(Flags); } void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, Index: lib/Target/XCore/XCoreFrameLowering.cpp =================================================================== --- lib/Target/XCore/XCoreFrameLowering.cpp +++ lib/Target/XCore/XCoreFrameLowering.cpp @@ -439,7 +439,7 @@ // Add the callee-saved register as live-in. It's killed at the spill. MBB.addLiveIn(Reg); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI); + TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI, MachineInstr::FrameSetup); if (emitFrameMoves) { auto Store = MI; --Store; Index: lib/Target/XCore/XCoreInstrInfo.h =================================================================== --- lib/Target/XCore/XCoreInstrInfo.h +++ lib/Target/XCore/XCoreInstrInfo.h @@ -71,7 +71,8 @@ MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const override; + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Index: lib/Target/XCore/XCoreInstrInfo.cpp =================================================================== --- lib/Target/XCore/XCoreInstrInfo.cpp +++ lib/Target/XCore/XCoreInstrInfo.cpp @@ -361,7 +361,8 @@ unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const + const TargetRegisterInfo *TRI, + MachineInstr::MIFlag Flags) const { DebugLoc DL; if (I != MBB.end() && !I->isDebugValue()) @@ -376,7 +377,8 @@ .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIndex) .addImm(0) - .addMemOperand(MMO); + .addMemOperand(MMO) + .setMIFlags(Flags); } void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,