Index: lib/Target/ARM/ARMISelDAGToDAG.cpp =================================================================== --- lib/Target/ARM/ARMISelDAGToDAG.cpp +++ lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -4123,11 +4123,10 @@ // The flags here are common to those allowed for apsr in the A class cores and // those allowed for the special registers in the M class cores. Returns a // value representing which flags were present, -1 if invalid. -static inline int getMClassFlagsMask(StringRef Flags, bool hasDSP) { - if (Flags.empty()) - return 0x2 | (int)hasDSP; - +static inline int getMClassFlagsMask(StringRef Flags) { return StringSwitch(Flags) + .Case("", 0x2) // no flags means nzcvq for psr registers, and 0x2 is + // correct when flags are not permitted .Case("g", 0x1) .Case("nzcvq", 0x2) .Case("nzcvqg", 0x3) @@ -4170,7 +4169,7 @@ } // We know we are now handling a write so need to get the mask for the flags. - int Mask = getMClassFlagsMask(Flags, Subtarget->hasDSP()); + int Mask = getMClassFlagsMask(Flags); // Only apsr, iapsr, eapsr, xpsr can have flags. The other register values // shouldn't have flags present. @@ -4185,10 +4184,7 @@ // The register was valid so need to put the mask in the correct place // (the flags need to be in bits 11-10) and combine with the SYSmvalue to // construct the operand for the instruction node. - if (SYSmvalue < 0x4) - return SYSmvalue | Mask << 10; - - return SYSmvalue; + return SYSmvalue | Mask << 10; } static int getARClassRegisterMask(StringRef Reg, StringRef Flags) { @@ -4201,7 +4197,7 @@ // The flags permitted for apsr are the same flags that are allowed in // M class registers. We get the flag value and then shift the flags into // the correct place to combine with the mask. - Mask = getMClassFlagsMask(Flags, true); + Mask = getMClassFlagsMask(Flags); if (Mask == -1) return -1; return Mask << 2; Index: test/CodeGen/ARM/msr-it-block.ll =================================================================== --- test/CodeGen/ARM/msr-it-block.ll +++ test/CodeGen/ARM/msr-it-block.ll @@ -20,8 +20,8 @@ ; V6M: msr apsr, {{r[0-9]+}} ; V7M: msr apsr_nzcvq, {{r[0-9]+}} ; V7M: msr apsr_nzcvq, {{r[0-9]+}} -; V7A: msr APSR_nzcvqg, {{r[0-9]+}} -; V7A: msr APSR_nzcvqg, {{r[0-9]+}} +; V7A: msr APSR_nzcvq, {{r[0-9]+}} +; V7A: msr APSR_nzcvq, {{r[0-9]+}} br label %exit exit: @@ -41,8 +41,8 @@ ; V6M: msr apsr, {{r[0-9]+}} ; V7M: msr apsr_nzcvq, {{r[0-9]+}} ; V7M: msr apsr_nzcvq, {{r[0-9]+}} -; V7A: msr APSR_nzcvqg, {{r[0-9]+}} -; V7A: msr APSR_nzcvqg, {{r[0-9]+}} +; V7A: msr APSR_nzcvq, {{r[0-9]+}} +; V7A: msr APSR_nzcvq, {{r[0-9]+}} br label %exit exit: Index: test/CodeGen/ARM/special-reg-mcore.ll =================================================================== --- test/CodeGen/ARM/special-reg-mcore.ll +++ test/CodeGen/ARM/special-reg-mcore.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE +; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 --show-mc-encoding 2>&1 | FileCheck %s --check-prefix=MCORE ; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE ; RUN: not llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE @@ -8,20 +8,20 @@ define i32 @read_mclass_registers() nounwind { entry: ; MCORE-LABEL: read_mclass_registers: - ; MCORE: mrs r0, apsr - ; MCORE: mrs r1, iapsr - ; MCORE: mrs r1, eapsr - ; MCORE: mrs r1, xpsr - ; MCORE: mrs r1, ipsr - ; MCORE: mrs r1, epsr - ; MCORE: mrs r1, iepsr - ; MCORE: mrs r1, msp - ; MCORE: mrs r1, psp - ; MCORE: mrs r1, primask - ; MCORE: mrs r1, basepri - ; MCORE: mrs r1, basepri_max - ; MCORE: mrs r1, faultmask - ; MCORE: mrs r1, control + ; MCORE: mrs r0, apsr @ encoding: [0xef,0xf3,0x00,0x80] + ; MCORE: mrs r1, iapsr @ encoding: [0xef,0xf3,0x01,0x81] + ; MCORE: mrs r1, eapsr @ encoding: [0xef,0xf3,0x02,0x81] + ; MCORE: mrs r1, xpsr @ encoding: [0xef,0xf3,0x03,0x81] + ; MCORE: mrs r1, ipsr @ encoding: [0xef,0xf3,0x05,0x81] + ; MCORE: mrs r1, epsr @ encoding: [0xef,0xf3,0x06,0x81] + ; MCORE: mrs r1, iepsr @ encoding: [0xef,0xf3,0x07,0x81] + ; MCORE: mrs r1, msp @ encoding: [0xef,0xf3,0x08,0x81] + ; MCORE: mrs r1, psp @ encoding: [0xef,0xf3,0x09,0x81] + ; MCORE: mrs r1, primask @ encoding: [0xef,0xf3,0x10,0x81] + ; MCORE: mrs r1, basepri @ encoding: [0xef,0xf3,0x11,0x81] + ; MCORE: mrs r1, basepri_max @ encoding: [0xef,0xf3,0x12,0x81] + ; MCORE: mrs r1, faultmask @ encoding: [0xef,0xf3,0x13,0x81] + ; MCORE: mrs r1, control @ encoding: [0xef,0xf3,0x14,0x81] %0 = call i32 @llvm.read_register.i32(metadata !0) %1 = call i32 @llvm.read_register.i32(metadata !4) @@ -56,32 +56,32 @@ define void @write_mclass_registers(i32 %x) nounwind { entry: ; MCORE-LABEL: write_mclass_registers: - ; MCORE: msr apsr_nzcvqg, r0 - ; MCORE: msr apsr_nzcvq, r0 - ; MCORE: msr apsr_g, r0 - ; MCORE: msr apsr_nzcvqg, r0 - ; MCORE: msr iapsr_nzcvqg, r0 - ; MCORE: msr iapsr_nzcvq, r0 - ; MCORE: msr iapsr_g, r0 - ; MCORE: msr iapsr_nzcvqg, r0 - ; MCORE: msr eapsr_nzcvqg, r0 - ; MCORE: msr eapsr_nzcvq, r0 - ; MCORE: msr eapsr_g, r0 - ; MCORE: msr eapsr_nzcvqg, r0 - ; MCORE: msr xpsr_nzcvqg, r0 - ; MCORE: msr xpsr_nzcvq, r0 - ; MCORE: msr xpsr_g, r0 - ; MCORE: msr xpsr_nzcvqg, r0 - ; MCORE: msr ipsr, r0 - ; MCORE: msr epsr, r0 - ; MCORE: msr iepsr, r0 - ; MCORE: msr msp, r0 - ; MCORE: msr psp, r0 - ; MCORE: msr primask, r0 - ; MCORE: msr basepri, r0 - ; MCORE: msr basepri_max, r0 - ; MCORE: msr faultmask, r0 - ; MCORE: msr control, r0 + ; MCORE: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88] + ; MCORE: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88] + ; MCORE: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84] + ; MCORE: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c] + ; MCORE: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88] + ; MCORE: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88] + ; MCORE: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84] + ; MCORE: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c] + ; MCORE: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88] + ; MCORE: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88] + ; MCORE: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84] + ; MCORE: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c] + ; MCORE: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88] + ; MCORE: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88] + ; MCORE: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84] + ; MCORE: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c] + ; MCORE: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88] + ; MCORE: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x88] + ; MCORE: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x88] + ; MCORE: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x88] + ; MCORE: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x88] + ; MCORE: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x88] + ; MCORE: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x88] + ; MCORE: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x88] + ; MCORE: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x88] + ; MCORE: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x88] call void @llvm.write_register.i32(metadata !0, i32 %x) call void @llvm.write_register.i32(metadata !1, i32 %x) Index: test/CodeGen/ARM/special-reg-v8m-main.ll =================================================================== --- test/CodeGen/ARM/special-reg-v8m-main.ll +++ test/CodeGen/ARM/special-reg-v8m-main.ll @@ -90,19 +90,19 @@ define void @write_mclass_registers(i32 %x) nounwind { entry: ; MAINLINE-LABEL: write_mclass_registers: - ; MAINLINE: msr apsr_nzcvqg, r0 + ; MAINLINE: msr apsr_nzcvq, r0 ; MAINLINE: msr apsr_nzcvq, r0 ; MAINLINE: msr apsr_g, r0 ; MAINLINE: msr apsr_nzcvqg, r0 - ; MAINLINE: msr iapsr_nzcvqg, r0 + ; MAINLINE: msr iapsr_nzcvq, r0 ; MAINLINE: msr iapsr_nzcvq, r0 ; MAINLINE: msr iapsr_g, r0 ; MAINLINE: msr iapsr_nzcvqg, r0 - ; MAINLINE: msr eapsr_nzcvqg, r0 + ; MAINLINE: msr eapsr_nzcvq, r0 ; MAINLINE: msr eapsr_nzcvq, r0 ; MAINLINE: msr eapsr_g, r0 ; MAINLINE: msr eapsr_nzcvqg, r0 - ; MAINLINE: msr xpsr_nzcvqg, r0 + ; MAINLINE: msr xpsr_nzcvq, r0 ; MAINLINE: msr xpsr_nzcvq, r0 ; MAINLINE: msr xpsr_g, r0 ; MAINLINE: msr xpsr_nzcvqg, r0