Index: lib/Target/ARM/ARMISelDAGToDAG.cpp =================================================================== --- lib/Target/ARM/ARMISelDAGToDAG.cpp +++ lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -4123,11 +4123,10 @@ // The flags here are common to those allowed for apsr in the A class cores and // those allowed for the special registers in the M class cores. Returns a // value representing which flags were present, -1 if invalid. -static inline int getMClassFlagsMask(StringRef Flags, bool hasDSP) { - if (Flags.empty()) - return 0x2 | (int)hasDSP; - +static inline int getMClassFlagsMask(StringRef Flags) { return StringSwitch(Flags) + .Case("", 0x2) // no flags means nzcvq for psr registers, and 0x2 is + // correct when flags are not permitted .Case("g", 0x1) .Case("nzcvq", 0x2) .Case("nzcvqg", 0x3) @@ -4170,7 +4169,7 @@ } // We know we are now handling a write so need to get the mask for the flags. - int Mask = getMClassFlagsMask(Flags, Subtarget->hasDSP()); + int Mask = getMClassFlagsMask(Flags); // Only apsr, iapsr, eapsr, xpsr can have flags. The other register values // shouldn't have flags present. @@ -4185,10 +4184,7 @@ // The register was valid so need to put the mask in the correct place // (the flags need to be in bits 11-10) and combine with the SYSmvalue to // construct the operand for the instruction node. - if (SYSmvalue < 0x4) - return SYSmvalue | Mask << 10; - - return SYSmvalue; + return SYSmvalue | Mask << 10; } static int getARClassRegisterMask(StringRef Reg, StringRef Flags) { @@ -4201,7 +4197,7 @@ // The flags permitted for apsr are the same flags that are allowed in // M class registers. We get the flag value and then shift the flags into // the correct place to combine with the mask. - Mask = getMClassFlagsMask(Flags, true); + Mask = getMClassFlagsMask(Flags); if (Mask == -1) return -1; return Mask << 2; Index: test/CodeGen/ARM/msr-it-block.ll =================================================================== --- test/CodeGen/ARM/msr-it-block.ll +++ test/CodeGen/ARM/msr-it-block.ll @@ -20,8 +20,8 @@ ; V6M: msr apsr, {{r[0-9]+}} ; V7M: msr apsr_nzcvq, {{r[0-9]+}} ; V7M: msr apsr_nzcvq, {{r[0-9]+}} -; V7A: msr APSR_nzcvqg, {{r[0-9]+}} -; V7A: msr APSR_nzcvqg, {{r[0-9]+}} +; V7A: msr APSR_nzcvq, {{r[0-9]+}} +; V7A: msr APSR_nzcvq, {{r[0-9]+}} br label %exit exit: @@ -41,8 +41,8 @@ ; V6M: msr apsr, {{r[0-9]+}} ; V7M: msr apsr_nzcvq, {{r[0-9]+}} ; V7M: msr apsr_nzcvq, {{r[0-9]+}} -; V7A: msr APSR_nzcvqg, {{r[0-9]+}} -; V7A: msr APSR_nzcvqg, {{r[0-9]+}} +; V7A: msr APSR_nzcvq, {{r[0-9]+}} +; V7A: msr APSR_nzcvq, {{r[0-9]+}} br label %exit exit: Index: test/CodeGen/ARM/special-reg-mcore.ll =================================================================== --- test/CodeGen/ARM/special-reg-mcore.ll +++ test/CodeGen/ARM/special-reg-mcore.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE +; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 -filetype=obj | llvm-objdump -d -triple=thumbv7m - -mattr=+dsp | FileCheck %s --check-prefix=MCORE-DISAS ; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE ; RUN: not llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE @@ -23,6 +24,22 @@ ; MCORE: mrs r1, faultmask ; MCORE: mrs r1, control + ; MCORE-DISAS-LABEL: read_mclass_registers: + ; MCORE-DISAS: ef f3 00 80 mrs r0, apsr + ; MCORE-DISAS: ef f3 01 81 mrs r1, iapsr + ; MCORE-DISAS: ef f3 02 81 mrs r1, eapsr + ; MCORE-DISAS: ef f3 03 81 mrs r1, xpsr + ; MCORE-DISAS: ef f3 05 81 mrs r1, ipsr + ; MCORE-DISAS: ef f3 06 81 mrs r1, epsr + ; MCORE-DISAS: ef f3 07 81 mrs r1, iepsr + ; MCORE-DISAS: ef f3 08 81 mrs r1, msp + ; MCORE-DISAS: ef f3 09 81 mrs r1, psp + ; MCORE-DISAS: ef f3 10 81 mrs r1, primask + ; MCORE-DISAS: ef f3 11 81 mrs r1, basepri + ; MCORE-DISAS: ef f3 12 81 mrs r1, basepri_max + ; MCORE-DISAS: ef f3 13 81 mrs r1, faultmask + ; MCORE-DISAS: ef f3 14 81 mrs r1, control + %0 = call i32 @llvm.read_register.i32(metadata !0) %1 = call i32 @llvm.read_register.i32(metadata !4) %add1 = add i32 %1, %0 @@ -56,19 +73,19 @@ define void @write_mclass_registers(i32 %x) nounwind { entry: ; MCORE-LABEL: write_mclass_registers: - ; MCORE: msr apsr_nzcvqg, r0 + ; MCORE: msr apsr_nzcvq, r0 ; MCORE: msr apsr_nzcvq, r0 ; MCORE: msr apsr_g, r0 ; MCORE: msr apsr_nzcvqg, r0 - ; MCORE: msr iapsr_nzcvqg, r0 + ; MCORE: msr iapsr_nzcvq, r0 ; MCORE: msr iapsr_nzcvq, r0 ; MCORE: msr iapsr_g, r0 ; MCORE: msr iapsr_nzcvqg, r0 - ; MCORE: msr eapsr_nzcvqg, r0 + ; MCORE: msr eapsr_nzcvq, r0 ; MCORE: msr eapsr_nzcvq, r0 ; MCORE: msr eapsr_g, r0 ; MCORE: msr eapsr_nzcvqg, r0 - ; MCORE: msr xpsr_nzcvqg, r0 + ; MCORE: msr xpsr_nzcvq, r0 ; MCORE: msr xpsr_nzcvq, r0 ; MCORE: msr xpsr_g, r0 ; MCORE: msr xpsr_nzcvqg, r0 @@ -83,6 +100,34 @@ ; MCORE: msr faultmask, r0 ; MCORE: msr control, r0 + ; MCORE-DISAS-LABEL: write_mclass_registers: + ; MCORE-DISAS: 80 f3 00 88 msr apsr_nzcvq, r0 + ; MCORE-DISAS: 80 f3 00 88 msr apsr_nzcvq, r0 + ; MCORE-DISAS: 80 f3 00 84 msr apsr_g, r0 + ; MCORE-DISAS: 80 f3 00 8c msr apsr_nzcvqg, r0 + ; MCORE-DISAS: 80 f3 01 88 msr iapsr_nzcvq, r0 + ; MCORE-DISAS: 80 f3 01 88 msr iapsr_nzcvq, r0 + ; MCORE-DISAS: 80 f3 01 84 msr iapsr_g, r0 + ; MCORE-DISAS: 80 f3 01 8c msr iapsr_nzcvqg, r0 + ; MCORE-DISAS: 80 f3 02 88 msr eapsr_nzcvq, r0 + ; MCORE-DISAS: 80 f3 02 88 msr eapsr_nzcvq, r0 + ; MCORE-DISAS: 80 f3 02 84 msr eapsr_g, r0 + ; MCORE-DISAS: 80 f3 02 8c msr eapsr_nzcvqg, r0 + ; MCORE-DISAS: 80 f3 03 88 msr xpsr_nzcvq, r0 + ; MCORE-DISAS: 80 f3 03 88 msr xpsr_nzcvq, r0 + ; MCORE-DISAS: 80 f3 03 84 msr xpsr_g, r0 + ; MCORE-DISAS: 80 f3 03 8c msr xpsr_nzcvqg, r0 + ; MCORE-DISAS: 80 f3 05 88 msr ipsr, r0 + ; MCORE-DISAS: 80 f3 06 88 msr epsr, r0 + ; MCORE-DISAS: 80 f3 07 88 msr iepsr, r0 + ; MCORE-DISAS: 80 f3 08 88 msr msp, r0 + ; MCORE-DISAS: 80 f3 09 88 msr psp, r0 + ; MCORE-DISAS: 80 f3 10 88 msr primask, r0 + ; MCORE-DISAS: 80 f3 11 88 msr basepri, r0 + ; MCORE-DISAS: 80 f3 12 88 msr basepri_max, r0 + ; MCORE-DISAS: 80 f3 13 88 msr faultmask, r0 + ; MCORE-DISAS: 80 f3 14 88 msr control, r0 + call void @llvm.write_register.i32(metadata !0, i32 %x) call void @llvm.write_register.i32(metadata !1, i32 %x) call void @llvm.write_register.i32(metadata !2, i32 %x) Index: test/CodeGen/ARM/special-reg-v8m-main.ll =================================================================== --- test/CodeGen/ARM/special-reg-v8m-main.ll +++ test/CodeGen/ARM/special-reg-v8m-main.ll @@ -90,19 +90,19 @@ define void @write_mclass_registers(i32 %x) nounwind { entry: ; MAINLINE-LABEL: write_mclass_registers: - ; MAINLINE: msr apsr_nzcvqg, r0 + ; MAINLINE: msr apsr_nzcvq, r0 ; MAINLINE: msr apsr_nzcvq, r0 ; MAINLINE: msr apsr_g, r0 ; MAINLINE: msr apsr_nzcvqg, r0 - ; MAINLINE: msr iapsr_nzcvqg, r0 + ; MAINLINE: msr iapsr_nzcvq, r0 ; MAINLINE: msr iapsr_nzcvq, r0 ; MAINLINE: msr iapsr_g, r0 ; MAINLINE: msr iapsr_nzcvqg, r0 - ; MAINLINE: msr eapsr_nzcvqg, r0 + ; MAINLINE: msr eapsr_nzcvq, r0 ; MAINLINE: msr eapsr_nzcvq, r0 ; MAINLINE: msr eapsr_g, r0 ; MAINLINE: msr eapsr_nzcvqg, r0 - ; MAINLINE: msr xpsr_nzcvqg, r0 + ; MAINLINE: msr xpsr_nzcvq, r0 ; MAINLINE: msr xpsr_nzcvq, r0 ; MAINLINE: msr xpsr_g, r0 ; MAINLINE: msr xpsr_nzcvqg, r0